JP6869376B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6869376B2 JP6869376B2 JP2019559958A JP2019559958A JP6869376B2 JP 6869376 B2 JP6869376 B2 JP 6869376B2 JP 2019559958 A JP2019559958 A JP 2019559958A JP 2019559958 A JP2019559958 A JP 2019559958A JP 6869376 B2 JP6869376 B2 JP 6869376B2
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Description
(構成)
図1は、本実施の形態1に係るMOSFET501(半導体装置)のユニットセルUCにおける半導体層(図2および図3におけるエピタキシャル層70)の構成を概略的に示す上面図である。なお、図1、および、後述する他の上面図において、図を見やすくするために、ウェルコンタクト領域25にはドット模様が付されている。図2および図3のそれぞれは、MOSFET501の構成を、図1の線II−IIおよび線III−IIIに沿う断面で概略的に示す断面図である。MOSFET501の能動領域には、マトリクス状に配置された複数のユニットセルUCが設けられており、図1は、そのうちのひとつを示している。図1においてはユニットセルUCが四角形の形状を有しているが、ユニットセルの形状は他の形状であってもよく、例えば六角形、八角形または円形でもよい。能動領域の外側には、終端領域(図示せず)が設けられている。
図4は、図1の変形例のMOSFET501S1(半導体装置)を示す上面図である。MOSFET501S1は、ストライプ形状(櫛形形状)で配置された複数のユニットセルUCが設けられた構造を有している。図4は、複数のユニットセルUCのうちのひとつを示している。各ユニットセルUCはストライプ形状が延びる方向(図中、縦方向)に延在している。複数のユニットセルUCは、この延在方向に交差する方向(図4における横方向)に配列されている。
次に、MOSFET501の製造方法の例について、図9〜図13の断面図を参照しつつ、以下に説明する。なお、図9〜図11および図13の視野は図2の視野に対応しており、図12の視野は図3の視野に対応している。
図14は、本実施の形態2に係るMOSFET502(半導体装置)の構成を、図2と同様の視野で概略的に示す断面図である。MOSFET502においては、ソース抵抗領域15は、ウェル領域20上に配置された高濃度部分15H(第1の部分)と、高濃度部分15H上に配置された低濃度部分15L(第2の部分)とを有している。高濃度部分15Hは低濃度部分15Lとウェル領域20との間に位置している。高濃度部分15Hの抵抗率は低濃度部分15Lの抵抗率よりも低い。これらの抵抗率を得るためには、高濃度部分15Hの不純物濃度が低濃度部分15Lの不純物濃度よりも高くされればよい。
図15は、本実施の形態3に係るMOSFET503(半導体装置)のユニットセルUCにおける半導体層(図16および図17におけるエピタキシャル層70)の構成を概略的に示す上面図である。図16および図17のそれぞれは、MOSFET503の構成を、図15の線XVI−XVIおよび線XVII−XVIIに沿う断面で概略的に示す断面図である。
(構成)
図19は、本実施の形態4に係るMOSFET504(半導体装置)のユニットセルUCにおける半導体層(図20および図21におけるエピタキシャル層70)の構成を概略的に示す上面図である。図20および図21のそれぞれは、MOSFET504の構成を、図19の線XX−XXおよび線XXI−XXIに沿う断面で概略的に示す断面図である。
MOSFET504の製造方法について、以下に説明する。
図25は、本実施の形態5に係るMOSFET505(半導体装置)のユニットセルUCにおける半導体層(図26および図27におけるエピタキシャル層70)の構成を概略的に示す上面図である。図26および図27のそれぞれは、MOSFET505の構成を、図25の線XXVI−XXVIおよび線XXVII−XXVIIに沿う断面で概略的に示す断面図である。
図29は、本実施の形態6に係るMOSFET506(半導体装置)の構成を、図26と同様の視野で概略的に示す断面図である。MOSFET506は、トレンチTRの底部に設けられp型を有するトレンチ底部保護領域21を有している。これにより、トレンチTRの底部へ印加される電界が抑制される。よってゲート絶縁膜30のリーク電流が低減する。よってMOSFETの信頼性を高めることができる。
Claims (14)
- チャネルを有する半導体装置であって、
第1の主面と、前記第1の主面と反対の第2の主面とを有し、前記第2の主面に平行な面内方向を有する半導体基板と、
前記半導体基板の前記第1の主面上に設けられたドレイン電極と
前記半導体基板の前記第2の主面上に設けられ、第1の導電型を有するドリフト層と、
前記ドリフト層上に設けられ、前記第1の導電型と異なる第2の導電型を有し、前記半導体装置の前記チャネルをなす部分を有するウェル領域と、
前記ウェル領域上に設けられ、前記第2の導電型を有し、前記ウェル領域の抵抗率よりも低い抵抗率を有するウェルコンタクト領域と、
前記ウェル領域によって前記ドリフト層から隔てられて前記ウェル領域上に設けられ、前記第1の導電型を有するソースコンタクト領域と、
前記ウェル領域によって前記ドリフト層から隔てられて前記ウェル領域上に設けられ、前記面内方向において前記ソースコンタクト領域に隣接し、前記第1の導電型を有し、前記ソースコンタクト領域のシート抵抗に比して高いシート抵抗を有するソース抵抗領域と、
前記ウェル領域の前記チャネルを覆うゲート絶縁膜と、
前記ゲート絶縁膜上に設けられたゲート電極と、
前記ソースコンタクト領域と前記ウェルコンタクト領域と前記ソース抵抗領域とに接し、前記チャネルへ少なくとも前記ソース抵抗領域を介してつながるソース電極と、
を備える、半導体装置。 - 前記半導体装置は、前記ゲート絶縁膜を含む絶縁層を有しており、前記絶縁層には、前記ソース電極が埋め込まれたコンタクトホールが設けられており、前記コンタクトホールは、前記ソース抵抗領域を横切る外周を有している、請求項1に記載の半導体装置。
- 前記チャネルは前記面内方向に沿って延びていることを特徴とする、請求項1または2に記載の半導体装置。
- 前記ウェル領域を貫通して前記ドリフト層に達する側壁を有するトレンチが設けられており、前記チャネルは前記側壁上に配置されていることを特徴とする、請求項1または2に記載の半導体装置。
- 前記トレンチの底部に設けられ、前記第2の導電型を有するトレンチ底部保護領域と、
前記トレンチの前記側壁の一部に設けられ、前記トレンチ底部保護領域と前記ウェル領域とに接し、前記第2の導電型を有するトレンチ側壁保護領域と、
をさらに備える、請求項4に記載の半導体装置。 - 平面視において、前記トレンチ側壁保護領域の少なくとも一部は、前記ウェルコンタクト領域と隣接するかまたは重なるように配置されていることを特徴とする、請求項5に記載の半導体装置。
- 前記ソース抵抗領域に隣接し、前記ソースコンタクト領域から離れ、前記ウェル領域によって前記ドリフト層から隔てられ、前記第1の導電型を有するソースエクステンション領域をさらに備え、前記ソース抵抗領域は前記ソースエクステンション領域を介して前記チャネルへつながっていることを特徴とする、請求項1から6のいずれか1項に記載の半導体装置。
- 前記ソース抵抗領域および前記ウェルコンタクト領域の各々は、面内方向において、前記ソースコンタクト領域と前記ソースエクステンション領域との間に配置されていることを特徴とする、請求項7に記載の半導体装置。
- 前記面内方向において前記ソース抵抗領域は前記ウェルコンタクト領域に隣接していることを特徴とする、請求項1から8のいずれか1項に記載の半導体装置。
- 前記ソース抵抗領域は、前記ウェル領域上に配置された第1の部分と、前記第1の部分上に配置された第2の部分とを有しており、前記第1の部分の抵抗率は前記第2の部分の抵抗率よりも低いことを特徴とする、請求項1から9のいずれか1項に記載の半導体装置。
- 前記ウェルコンタクト領域は、前記ゲート絶縁膜のみを介して前記ゲート電極に接する部分を有しないように配置されていることを特徴とする、請求項1から10のいずれか1項に記載の半導体装置。
- 前記ソース電極と前記ソース抵抗領域との間のコンタクト抵抗は、前記ソース電極と前記ソースコンタクト領域との間のコンタクト抵抗より、10倍以上大きいことを特徴とする、請求項1から11のいずれか1項に記載の半導体装置。
- 前記半導体装置は、ストライプ形状で配置された複数のユニットセルを有し、
前記ウェルコンタクト領域は、前記ストライプ形状が延びる方向に交差する方向において前記ソースコンタクト領域を介して互いに対向する部分を有し、前記対向する部分の中心は前記ストライプ形状が延びる方向においてずらされている、請求項1から12のいずれか1項に記載の半導体装置。 - 前記半導体基板、前記ドリフト層、および前記ウェル領域は、炭化珪素からなる、請求項1から13のいずれか1項に記載の半導体装置。
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