JP5687364B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5687364B2 JP5687364B2 JP2013552393A JP2013552393A JP5687364B2 JP 5687364 B2 JP5687364 B2 JP 5687364B2 JP 2013552393 A JP2013552393 A JP 2013552393A JP 2013552393 A JP2013552393 A JP 2013552393A JP 5687364 B2 JP5687364 B2 JP 5687364B2
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- 239000004065 semiconductor Substances 0.000 title claims description 141
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Description
「MOS」という用語は、古くは金属/酸化物/半導体の接合構造に用いられており、Metal-Oxide-Semiconductorの頭文字を採ったものとされている。しかしながら特にMOS構造を有する電界効果トランジスタ(以下、単に「MOSトランジスタ」と称す)においては、近年の集積化や製造プロセスの改善などの観点からゲート絶縁膜やゲート電極の材料が改善されている。
<装置構成>
図1は、本発明に係る実施の形態1の半導体装置、より具体的には、炭化珪素(SiC)基板上に形成されたMOS構造を有する電界効果トランジスタ(炭化珪素MOSトランジスタ)100の上面構成を模式的に示す平面図である。
<第1の効果>
図11は、本発明に係る実施の形態1の炭化珪素MOSトランジスタ100による効果を説明する図である。
また、図16には、本発明に係る実施の形態1の炭化珪素MOSトランジスタ100による別の効果を説明する図である。
例えば、図7に示す単位鎖状構造CLUにおいては、炭化珪素半導体基板(ドリフト層2)内で隣り合う単位鎖状構造CLUのウェル領域20どうしが接続しないように配置されているが、その終端部の平面視形状については様々な形態を取りうる。
以上説明した本実施の形態1の炭化珪素MOSトランジスタ100においては、図3に示すソースパッド41の平面視形状と相似のほぼ四角形状である能動領域ARにおいて、単位鎖状構造CLUは、能動領域ARの一辺(左右上下の何れかの辺)に対して45度の角度をなすようにオフセット配置された構成について説明したが、単位鎖状構造CLUの配置はこれに限定されるものではない。
次に、実施の形態1に係る炭化珪素MOSトランジスタ100の製造方法について、製造工程を順に示す断面図である図27〜図33を用いて説明する。なお、図27〜図33に示す断面図は、図1および図3におけるB−B線での断面図であり、図3に示すように隣り合う2つの単位格子UCを切断した図である。
以上説明したように、実施の形態1に係る炭化珪素MOSトランジスタ100においては、ドリフト層2の主面における平面視形状が所定の形状に規定された単位格子UCが、括れ部分を有して鎖状に複数連結されることで単位鎖状構造CLUを構成し、単位格子の所定の形状は、ソース領域12およびウェル領域20を内包するように設定されたドリフト層2の仮想領域の外縁と、他の単位格子との連結部におけるソース領域12およびウェル領域20の外縁とで規定され、隣り合う単位鎖状構造CLUにおいて、単位格子間に隙間が生じないように単位鎖状構造CLUを複数配列することで能動領域ARが構成されている。このため、チャネル幅密度が向上し、オン抵抗が低減されて低抵抗化が可能になる。さらに帰還容量が減少してスイッチング損失を減ずることができ、高速スイッチング動作を行う上で有利となる。
図34は、本発明に係る実施の形態2の炭化珪素MOSトランジスタ200における能動領域を構成する単位鎖状構造の配列を示す平面図であり、実施の形態1における図7に対応する図である。また、図34におけるD−D線での炭化珪素MOSトランジスタ200の断面構造を図35に示す。なお、実施の形態1の炭化珪素MOSトランジスタ100と同一の構成については同一の符号を付し、重複する説明は省略する。
図36は、本発明に係る実施の形態3の炭化珪素MOSトランジスタ300における能動領域を構成する単位鎖状構造の配列を示す平面図であり、実施の形態1における図7に対応する図である。また、図36におけるE−E線での炭化珪素MOSトランジスタ300の断面構造を図37に示す。なお、実施の形態1の炭化珪素MOSトランジスタ100と同一の構成については同一の符号を付し、重複する説明は省略する。
図38は、本発明に係る実施の形態4の炭化珪素MOSトランジスタ400における能動領域を構成する単位鎖状構造の配列を示す平面図であり、実施の形態1における図7に対応する図である。また、図38におけるF−F線での炭化珪素MOSトランジスタ400の断面構造を図39に示す。なお、実施の形態1の炭化珪素MOSトランジスタ100と同一の構成については同一の符号を付し、重複する説明は省略する。
Claims (14)
- 第1導電型の半導体基板と、
前記半導体基板の第1の主面上に配設された第1導電型の半導体層と、
前記半導体層の主面表面内に選択的に配設された第2導電型のウェル領域と、
前記ウェル領域の表面内に選択的に配設された第1導電型のソース領域と、を備え、
前記半導体層、前記ウェル領域および前記ソース領域によって単位格子が構成され、
前記半導体層の前記主面における平面視形状が所定の形状に規定された前記単位格子が、鎖状に複数連結されることで括れ部分を有した単位鎖状構造を構成し、
前記単位格子の前記所定の形状は、
前記ソース領域および前記ウェル領域を内包するように設定された前記半導体層の仮想領域の外縁と、他の単位格子との連結部における前記ソース領域および前記ウェル領域の外縁とで規定され、
隣り合う前記単位鎖状構造において、前記単位格子間に隙間が生じないようにオフセットをつけて前記単位鎖状構造を複数配列することで能動領域が構成され、
隣り合う前記単位鎖状構造で規定される前記ウェル領域の間隔が、前記能動領域内で一定であることを特徴とする半導体装置。 - 前記単位格子の前記所定の形状は、
一組の対向する角部の内角が共に90°である六角形であり、
前記角部を構成する辺以外の対向する2辺が前記連結部をなし、前記連結部で前記単位格子どうしが接続されることで、前記単位鎖状構造において前記ソース領域および前記ウェル領域が連続し、
前記単位格子内において、
前記ソース領域の外縁に沿って前記ウェル領域が存在し、前記角部を構成する辺に沿うように前記ソース領域および前記ウェル領域の外縁部は直線状をなし、
前記ソース領域および前記ウェル領域は、
前記角部に対向する部分においては、それぞれが同一の第1の曲率中心を有し、かつ異なる第1および第2の曲率半径を有する中心角90°の円弧状の凸部をなし、
前記ウェル領域の外縁と前記ソース領域の外縁との距離は、前記単位格子内のどの部分においても前記第2の曲率半径と前記第1の曲率半径との差分の距離に設定される、請求項1記載の半導体装置。 - 前記単位鎖状構造は、
前記単位格子の前記連結部において、中心角90°の円弧状の凹部を有し、
前記単位鎖状構造内において、
前記ソース領域および前記ウェル領域は、
前記凹部においては、それぞれが同一の第2の曲率中心を有し、かつ異なる第3および第4の曲率半径を有する中心角90°の円弧状をなす、請求項2記載の半導体装置。 - 隣り合う前記単位鎖状構造の角部において、
一方の前記単位鎖状構造の中心角90°の円弧状の凸部における前記第1の曲率中心と、
もう一方の前記単位鎖状構造の中心角90°の円弧状の凹部における前記第2の曲率中心とが同じである、請求項3記載の半導体装置。 - 前記単位鎖状構造は、
前記単位格子における前記ウェル領域の直線状の外縁部の何れもが、前記半導体基板および前記半導体層のオフ方向と垂直ではない方向に延在するように配列される、請求項1記載の半導体装置。 - 前記能動領域の端縁部を規定する第2導電型の終端ウェル領域を備え、
前記単位鎖状構造は、
その終端部において、前記鎖状単位構造内の前記ウェル領域が前記終端ウェル領域と接続する構成と接続しない構成を含み、両者が交互に配列される、請求項1記載の半導体装置。 - 前記能動領域の端縁部を規定する第1導電型の終端ソース領域を備え、
前記単位鎖状構造は、
その終端部において、前記鎖状単位構造内の前記ソース領域が終端ソース領域と接続する構成と接続しない構成を含み、
前記鎖状単位構造内の前記ソース領域が終端ソース領域と接続しない構成においては、その終端部における前記半導体層と、それに対応する前記終端ソース領域との間にも前記ウェル領域を有し、隣り合う前記単位鎖状構造の前記ウェル領域どうしが連続する、請求項1記載の半導体装置。 - 前記能動領域の端縁部を規定する第2導電型の終端ウェル領域を備え、
前記単位鎖状構造は、
少なくとも一方の終端部において、前記鎖状単位構造内の前記ウェル領域が前記終端ウェル領域と接続している構成を含む、請求項1記載の半導体装置。 - 前記能動領域の端縁部を規定する第2導電型の終端ウェル領域を備え、
前記単位鎖状構造は、
両方の終端部において、前記鎖状単位構造内の前記ウェル領域が前記終端ウェル領域と接続しておらず
前記単位鎖状構造間での前記ウェル領域間の距離と、前記単位鎖状構造内の前記ウェル領域と、前記終端ウェル領域との間の距離が一定である、請求項1記載の半導体装置。 - 前記単位鎖状構造は、
前記ソース領域と前記ウェル領域内に設けられた第2導電型のウェルコンタクト領域とに接続する第1のオーミック電極を有する第1の単位格子と、
前記ウェルコンタクト領域に接続し前記ソース領域には接続しない第2のオーミック電極を有する第2の単位格子とが接続されて構成される、請求項1記載の半導体装置。 - 前記単位鎖状構造は、
前記ウェル領域内に設けられた第2導電型のウェルコンタクト領域に接続し前記ソース領域には接続しない第2のオーミック電極を有する第2の単位格子と、
前記ソース領域のみに接続する第3のオーミック電極を有する第3の単位格子とが接続されて構成される、請求項1記載の半導体装置。 - 前記第2の単位格子において、前記ウェルコンタクト領域と前記ソース領域とでトンネル接合を形成する、請求項10または請求項11記載の半導体装置。
- 前記単位鎖状構造は、
前記ソース領域と前記ウェル領域内に設けられた第2導電型のウェルコンタクト領域とに接続する第1のオーミック電極を有する第1の単位格子と、
前記ソース領域のみに接続する第3のオーミック電極を有する第3の単位格子とが接続されて構成される、請求項1記載の半導体装置。 - 前記半導体層は、炭化珪素で構成される、請求項1記載の半導体装置。
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