JP7139679B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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Description
本発明の実施の形態に係る半導体装置は、図1に示すように、SiC半導体基板を用いたn型のドリフト領域2と、ドリフト領域2の上部に設けられた複数のp型のベース領域3a,3bとを備えるMOSFETである。ドリフト領域2の上部には、ベース領域3a,3bからドリフト領域2に亘ってトレンチ4が設けられている。
そしてドレイン領域1からソース領域7a,7bに向かって、トレンチ4の左右の側壁のそれぞれに沿って主電流IL1,IR1が流れる。主電流IL1,IR1の流れは、n型のドリフト領域2の中で保護層11aの側方を上昇し、保護層11aの上側に到達した後、保護層11aの端部の上面に沿うように約90度向きが変わる。その後、主電流IL1,IR1は、反転層11binvの端部の内部に進入する。
一方、図3に示すように、導電路形成層を有さない比較例に係る半導体装置の場合、オン状態での主電流ILz,IRzは、保護層11zの端部の階段形状に沿って流れる。比較例に係る半導体装置は、本発明の実施の形態に係る半導体装置と比べ、導電路形成層11bを含む2層型の保護導通領域(11a,11b)を有しておらず、1層型の保護層11zのみを有する点が異なる。すなわち比較例に係る半導体装置の保護層11zの外縁の形状は、本発明の実施の形態に係る半導体装置の保護導通領域(11a,11b)の外縁の形状と等価であるが、内部の導電型が高濃度のp+型のみであって、反転層は形成されない。比較例に係る半導体装置の保護層11zの不純物元素の濃度は、例えば5.0×1018cm-3程度である。一方、本発明の実施の形態に係る半導体装置の保護導通領域(11a,11b)の導電路形成層11bの不純物元素の濃度は、ドリフト領域2の濃度と同等である、4.0×1017cm-3程度に低く設定されている。
次に本発明の実施の形態に係る半導体装置の製造方法を、図6~図14を参照して例示的に説明する。まず図6に示すように、例えば、n+型の4H-SiCの半導体基板1subを用意し、エピタキシャル成長方法を用いて、半導体基板1subの上にn型の4H-SiCの半導体層をエピタキシャル成長させ、ドリフト領域2とする。次にドリフト領域2の上面上に、第1マスク用皮膜16を所定の厚みで堆積させる。第1マスク用皮膜16としては、熱酸化処理により形成や化学的気相成長(CVD)法等により堆積された酸化シリコン(SiO2)膜や窒化シリコン(Si3N4)膜等が使用できる。
次に本発明の実施の形態の第1変形例に係る半導体装置の製造方法を、図15~図18を参照して説明する。例えば、n+型の4H-SiCの半導体基板1subを用意し、エピタキシャル成長方法を用いて、半導体基板1subの上にn型の4H-SiCの半導体層をエピタキシャル成長させ、ドリフト領域2とする。次にドリフト領域2の上面上に、第1マスク用皮膜16を所定の厚みで堆積させる。第1マスク用皮膜16としては、熱酸化処理により形成やCVD法等により堆積されたSiO2膜やSi3N4膜等が使用できる。ここまでの工程は、前記図6を用いて説明した場合と同様である。
次に本発明の実施の形態の変形例に係る半導体装置を、図19~図26を参照して説明する。図19に示した第2変形例に係る半導体装置のように、上面がトレンチ4の底部に接して設けられるp型の導電路形成層(21b1~21b3)の内部の不純物元素濃度を、それぞれの領域毎にトレンチ4の幅方向に沿って異ならせてもよい。第2変形例に係る半導体装置の保護導通領域(21a,21b1~21b3)は、保護層21a及び導電路形成層(21b1~21b3)からなる2層構造である。
図21に示した第3変形例に係る半導体装置のように、上面がトレンチ4の底部に接して設けられるp型の導電路形成層(31b1~31b5)の内部の不純物元素濃度を、トレンチ4の溝幅方向に沿って、第2変形例よりも更に複数段階で異ならせてもよい。第3変形例に係る半導体装置の保護導通領域(31a,31b1~31b5)は、保護層31a及び導電路形成層(31b1~31b5)からなる2層構造である。
第2変形例及び第3変形例の場合、内部に複数の領域を有する導電路形成層は、トレンチ4の中央に対応する中央部分の領域の不純物元素濃度が最も濃いと共に、中央から外側に向かう方向に沿って、領域の濃度が薄くなるように設定されていた。しかし図23に示す第4変形例に係る半導体装置のように、上面がトレンチ4の底部に接して設けられるp型の導電路形成層(41b1,41b2)の内部の不純物元素濃度を、トレンチ4の深さ方向に沿って異ならせてもよい。第4変形例に係る半導体装置の保護導通領域(41a,41b1,41b2)は、保護層41a及び導電路形成層(41b1,41b2)からなる2層構造である。
図25に示した第5変形例に係る半導体装置のように、保護層51aの張り出し幅と導電路形成層51bの張り出し幅とが等しく、保護層51a及び導電路形成層51bからなる保護導通領域(51a,51b)の断面形状の外縁が矩形状であってもよい。導電路形成層51bの不純物元素濃度は、オン状態で導電型がn型に反転する低濃度のp-型に設定されている。第5変形例に係る半導体装置の導電路形成層51b以外の構造については、図1に示した半導体装置における同名の部材と等価であるため、重複説明を省略する。
本発明は上記の開示した実施の形態によって説明したが、この開示の一部をなす論述及び図面は、本発明を限定するものであると理解すべきではない。本開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかになると考えられるべきである。
1sub 半導体基板
2 ドリフト領域
3a,3b ベース領域
3a1,3b1 チャネル領域
4 トレンチ
5 ゲート絶縁膜
6 ゲート電極
7a,7b ソース領域
8 層間絶縁膜
9 ソース電極
10 ドレイン電極
11a,11a2 保護層
11a0,11a1 保護層予定領域
11b,11b4 導電路形成層
11b0,11b3 導電路形成層予定領域
11b1 第1導電路形成領域
11b1inv 反転層
11b2 第2導電路形成領域
11b2inv 反転層
11binv 反転層
11c 中央保護領域
11z 保護層
12a,12b ベースコンタクト領域
13a,13b 第1コンタクト下ベース領域
14a,14b 第2コンタクト下ベース領域
15 バリアメタル層
16 第1マスク用皮膜
16p 第1マスク
17 第2マスク用皮膜
17p 第2マスク
21a 保護層
21b1 中央保護領域
21b1inv 反転層
21b2 左側導電路形成領域
21b2inv 反転層
21b3 右側導電路形成領域
31a 保護層
31b1 中央保護領域
31b2 左側第1導電路形成領域
31b2inv 反転層
31b3 右側第1導電路形成領域
31b3inv 反転層
31b4 左側第2導電路形成領域
31b4inv 反転層
31b5 右側第2導電路形成領域
31b5inv 反転層
41a 保護層
41b1 下側導電路形成領域
41b2 上側導電路形成領域
41b1inv 反転層
41b2inv 反転層
51a 保護層
51b 導電路形成層
51binv 反転層
IL1,IR1 主電流
IL2,IR2 主電流
ILz,IRz 主電流
d 厚み
w 幅
Claims (12)
- 第1導電型のドリフト領域と、
前記ドリフト領域の上部に設けられた第2導電型のベース領域と、
前記ドリフト領域の上部で前記ベース領域から前記ドリフト領域に亘るトレンチの内側に設けられたゲート絶縁膜と、
前記トレンチの内側に前記ゲート絶縁膜を介して埋め込まれたゲート電極と、
前記ベース領域の上部に設けられた第1導電型の第1主電極領域と、
前記ドリフト領域の下に設けられた第1導電型の第2主電極領域と、
前記ドリフト領域の内部で、前記トレンチの下に前記トレンチの溝幅より外側に張り出して設けられた第2導電型の保護層と、
前記保護層と前記トレンチの底部との間に、前記溝幅より外側に張り出して設けられ、オン時に反転層が形成されるように不純物元素の濃度が設定された張り出し領域を有する第2導電型の導電路形成層と、
を備え、前記導電路形成層の厚みは、10nm以下であることを特徴とする半導体装置。 - 前記ベース領域の不純物元素の濃度が前記導電路形成層の不純物元素の濃度より濃いことを特徴とする請求項1に記載の半導体装置。
- 前記保護層と前記導電路形成層のそれぞれの不純物元素の濃度が同じであることを特徴とする請求項1又は2に記載の半導体装置。
- 前記導電路形成層の不純物元素の濃度は、前記トレンチの中央から外側に向かって薄くなることを特徴とする請求項1又は2に記載の半導体装置。
- 前記導電路形成層の不純物元素の濃度は、前記トレンチの底部から下側に向かって濃くなることを特徴とする請求項1又は2に記載の半導体装置。
- 第1導電型のドリフト領域の上部に第2導電型のベース領域を形成する工程と、
前記ドリフト領域の上部に、前記ベース領域から前記ドリフト領域に亘ってトレンチを掘る工程と、
前記トレンチの内側にゲート絶縁膜を介してゲート電極を埋め込む工程と、
前記ベース領域の上部に第1導電型の第1主電極領域を形成する工程と、
前記ドリフト領域の下に第1導電型の第2主電極領域を形成する工程と、
前記ドリフト領域の内部で、前記トレンチの下に、前記トレンチの溝幅より外側に張り出すように第2導電型の保護層を形成する工程と、
前記保護層と前記トレンチの底部との間に、前記保護層と前記トレンチの底部との間に、前記溝幅より外側に張り出す領域を有する第2導電型の導電路形成層を、オン時に張り出し領域で反転層が形成されるように不純物元素濃度を制御しながら形成する工程と、
を含み、前記導電路形成層の厚みは、10nm以下であることを特徴とする半導体装置の製造方法。 - 前記保護層を形成する工程及び前記導電路形成層を形成する工程は、前記保護層及び前記導電路形成層のそれぞれの不純物元素の濃度が同じになるように行うことを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記導電路形成層を形成する工程を、前記トレンチを形成する工程の後で行うことを特徴とする請求項6又は7に記載の半導体装置の製造方法。
- 前記導電路形成層を形成する工程は、前記導電路形成層の上面が前記トレンチの底部の前記ゲート絶縁膜に接触するように行うことを特徴とする請求項6~8のいずれか一項に記載の半導体装置の製造方法。
- 前記ベース領域を形成する工程は、第2導電型の不純物元素イオンの注入により行い、
前記導電路形成層を形成する時の不純物元素イオンのドーズ量は、前記ベース領域を形成する時の不純物元素イオンのピークドーズ量より低いことを特徴とする請求項9に記載の半導体装置の製造方法。 - 前記保護層を形成する工程は、前記トレンチを掘る工程で形成されたマスクを連続して用いて行うことを特徴とする請求項6~10のいずれか一項に記載の半導体装置の製造方法。
- 前記ドリフト領域の内部で複数の前記トレンチの間に、前記導電路形成層と同じ深さに第2導電型のコンタクト下ベース領域を形成する工程を更に含み、
前記導電路形成層を形成する工程と前記コンタクト下ベース領域を形成する工程とをそれぞれ別々に行うことを特徴とする請求項6~11のいずれか一項に記載の半導体装置の製造方法。
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