WO2016125490A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2016125490A1 WO2016125490A1 PCT/JP2016/000562 JP2016000562W WO2016125490A1 WO 2016125490 A1 WO2016125490 A1 WO 2016125490A1 JP 2016000562 W JP2016000562 W JP 2016000562W WO 2016125490 A1 WO2016125490 A1 WO 2016125490A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- contact
- emitter
- semiconductor device
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 225
- 238000004519 manufacturing process Methods 0.000 title claims description 70
- 238000000034 method Methods 0.000 title claims description 36
- 239000010410 layer Substances 0.000 claims abstract description 112
- 239000002344 surface layer Substances 0.000 claims abstract description 36
- 239000012535 impurity Substances 0.000 claims description 98
- 150000002500 ions Chemical class 0.000 claims description 76
- 239000000758 substrate Substances 0.000 claims description 61
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- 230000004888 barrier function Effects 0.000 claims description 52
- 239000011229 interlayer Substances 0.000 claims description 42
- 238000002347 injection Methods 0.000 claims description 41
- 239000007924 injection Substances 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 28
- 239000001257 hydrogen Substances 0.000 claims description 16
- 229910052739 hydrogen Inorganic materials 0.000 claims description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 15
- 230000001747 exhibiting effect Effects 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 230000001133 acceleration Effects 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims 1
- 230000000737 periodic effect Effects 0.000 claims 1
- -1 aluminum-copper-silicon Chemical compound 0.000 description 33
- 230000001965 increasing effect Effects 0.000 description 26
- 238000005530 etching Methods 0.000 description 24
- 238000010586 diagram Methods 0.000 description 22
- 230000008569 process Effects 0.000 description 16
- 229910052796 boron Inorganic materials 0.000 description 15
- 238000007667 floating Methods 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229910052785 arsenic Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 230000001681 protective effect Effects 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000011084 recovery Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000001994 activation Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device related to an IGBT or the like having a trench structure and a technique effectively applied to the method of manufacturing the same.
- an insulated gate bipolar transistor (hereinafter referred to as an IGBT) having a trench structure in which a trench is provided on a main surface of a semiconductor substrate and a gate electrode is embedded inside the trench via a gate insulating film.
- trench type IGBTs can increase the channel density and lower the on-state voltage, and thus the application field is increasing in recent years.
- an IGBT having a trench structure there is an IGBT in which n-type emitter regions and p-type contact regions are alternately arranged along the longitudinal direction of the island region in an island region sandwiched by adjacent trenches.
- the latch injection resistance to a parasitic thyristor is improved by narrowing the gate injection width by narrowing the emitter injection width measured in the longitudinal direction of the island region at the pn junction interface between the n-type emitter region and the p-type base region. It can be done.
- the emitter injection width is relatively dependent on the surface width (emitter region contact width) of the n-type emitter region defined in the longitudinal direction of the island region. Therefore, if the emitter injection width is narrowed and the gate width is narrowed, the surface area of the n-type emitter region is reduced and the contact resistance with the emitter electrode electrically connected to the n-type emitter region is increased. There was a problem that the voltage was high.
- the width of the island region tends to be narrowed to increase the number of island regions in order to achieve high current density. Therefore, the surface area of the n-type emitter region is reduced by narrowing the width of the island region, and the contact resistance with the emitter electrode is increased. Therefore, the surface area of the emitter region needs to be secured as much as possible. There is.
- An object of the present invention is to provide a technology capable of improving the latch-up tolerance and lowering the on-state voltage of a semiconductor device operating similar to an IGBT or an IGBT used for an individual device or a power IC.
- a drift layer of a first conductivity type, a mesa region sandwiched between adjacent trenches on the drift layer, and a trench A plurality of gate electrodes are formed periodically along the longitudinal direction of the trench in the surface layer portion of the gate region provided through the gate insulating film, the base region of the second conductivity type provided in the mesa region, and the base region.
- An emitter region of the first conductivity type and an emitter region are alternately arranged along the longitudinal direction so as to sandwich each of the emitter regions, are formed deeper than the emitter region, and are spaced apart from each other immediately below the emitter region And forming a contact region of a mold.
- the present invention it is possible to improve the latch-up resistance and lower the on-state voltage of the IGBT or the semiconductor device operating in a similar manner to the IGBT.
- FIG. 1 is a plan view of relevant parts of a semiconductor device according to a first embodiment of the present invention. It is principal part sectional drawing which shows the cross-section which followed the IIa-IIa line of FIG. It is principal part sectional drawing which shows the cross-section which followed the IIb-IIb line
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 1 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1). It is a figure (principal part top view which shows the plane pattern of the mask for impurity introduction) for demonstrating the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention.
- FIG. 13 is a main part cross-sectional view showing a cross-sectional structure along the line IIIa-IIIa of FIG. 12;
- FIG. 13 is an essential part cross sectional view showing a cross sectional structure along a IIIb-IIIb line in FIG.
- FIG. 16 is a main part cross-sectional view showing a cross-sectional structure along the line IVa-IVa of FIG. 15;
- FIG. 16 is an essential part cross sectional view showing a cross sectional structure along an IVb-IVb line in FIG. 15;
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 16 is a main part cross-sectional view showing a cross-sectional structure along the line IVa-IVa of FIG. 15
- FIG. 16 is an essential part cross sectional view showing a cross sectional structure along an IVb-IVb line in FIG. 15
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIb-IIb line in FIG. 1);
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIc-IIc line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 1 is a diagram for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIb-IIb line in FIG. 1);
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 1 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 7 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 1 is a diagram for illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention (a cross-sectional view of relevant parts at a position corresponding to the IIa-IIa line in FIG. 1).
- FIG. 6 is a process flow diagram showing a part of the manufacturing process for describing the method of manufacturing a semiconductor device according to the first embodiment of the present invention. It is a principal part top view of the semiconductor device concerning a 2nd embodiment of the present invention.
- FIG. 30 is a cross-sectional view of essential parts showing a cross-sectional structure along the line Va-Va in FIG. 29.
- FIG. 30 is a cross-sectional view of essential parts showing a cross-sectional structure along the line Vb-Vb in FIG. 29.
- FIG. 33 is a cross-sectional view of essential parts showing a cross-sectional structure along the line VIa-VIa of FIG. 32.
- FIG. 30 is a cross-sectional view of essential parts showing a cross-sectional structure along the line VIa-VIa of FIG. 32.
- FIG. 33 is a cross-sectional view of essential parts showing a cross-sectional structure along the line VIb-VIb of FIG. 32.
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 38 is a cross-sectional view of essential parts showing a cross-sectional structure along a VIIa-VIIa line in FIG. 37.
- FIG. 38 is a cross-sectional view of essential parts showing a cross-sectional structure along the line VIIb-VIIb in FIG. 37.
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 38 is a cross-sectional view of essential parts showing a cross-sectional structure along a VIIa-VIIa line in FIG. 37.
- FIG. 38 is a cross-sectional view of essential parts showing a cross-sectional structure along the line VIIb-VIIb in FIG. 37.
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- FIG. 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
- 35 is a diagram (cross-sectional view of essential parts at a position corresponding to the line VIa-VIa in FIG. 32) for describing the method of manufacturing a semiconductor device according to the third embodiment of the present invention. It is a principal part top view which shows the modification of the semiconductor device concerning a 3rd embodiment of the present invention. It is principal part sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention. It is principal part sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention. It is an enlarged view of A part in FIG. It is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention.
- first conductivity type is n-type and the second conductivity type is p-type
- the first conductivity type may be p-type
- the second conductivity type may be n-type.
- electrons or holes are the majority carriers in a layer or a region where n or p is marked.
- + or ⁇ attached to n or p means that the semiconductor region has a relatively high or low impurity concentration, respectively, as compared with the semiconductor region to which + and ⁇ are not appended.
- the first and second directions orthogonal to each other in the same plane will be referred to as an X direction and a Y direction, respectively.
- the horizontal direction is defined as the X direction
- the vertical direction is defined as the Y direction.
- the horizontal direction is defined as the X direction.
- FIG. 4 to FIG. 6, FIG. 14, FIG. 17, FIG. 20, and FIG. 46 the horizontal direction is defined as the Y direction.
- hatching representing a cross section is omitted in order to make the drawings easy to see.
- FIGS. 1 to 4 an IGBT having a trench structure in which a part of a semiconductor substrate is formed as a drift layer 3 will be described as an example.
- the X direction and the Y direction orthogonal to each other are defined in the main surface of the semiconductor substrate including the drift layer 3 inside, and as shown in FIG. Mesa regions 5 are respectively partitioned.
- FIG. 1 the X direction and the Y direction orthogonal to each other are defined in the main surface of the semiconductor substrate including the drift layer 3 inside, and as shown in FIG. Mesa regions 5 are respectively partitioned.
- each of the trenches 4 and the mesa region 5 is periodically arranged along the X direction, and forms a planar pattern extending in parallel in the stripe direction along the Y direction. .
- a plurality of fine pattern transistor cells 2 are electrically connected in parallel. As a result, it has a multi-cell structure to obtain a large current.
- 1 to 3 exemplarily show, as a part of the semiconductor device 1A according to the first embodiment, although not limited to this, a portion in which three transistor cells 2 and three mesa regions 5 are arranged.
- a plurality of trenches 4 adjacent to each other in the X direction are dug on the drift layer 3.
- a region sandwiched between a pair of opposing trenches 4 among the plurality of trenches 4 is defined as a mesa region 5.
- a gate insulating film 6 is provided along the inner wall of each of the plurality of trenches 4.
- Gate electrodes 8 are provided in the interior of the trenches 4 via the gate insulating film 6.
- each of the transistor cells 2 is provided with the base region 9 of the second conductivity type (p type) provided in the surface layer portion of the mesa region 5.
- emitter regions 11 of the first conductivity type (n + type) periodically arranged along the Y direction are provided. Further, contact regions 12 of the second conductivity type (n + type) are provided to sandwich each of the emitter regions 11.
- a plurality of emitter regions 11 and contact regions 12 are alternately arranged along the Y direction. Furthermore, the depth of the contact region 12 is formed deeper than the emitter region 11 and extends below the emitter region 11 so as to be separated from each other.
- the plurality of transistor cells 2 includes a common drift layer 3 formed of a semiconductor substrate as a common region, a buffer layer 21 of the first conductivity type (n type) provided on the back surface of the drift layer 3 and a second conductivity type. And a collector region 22 of (p + type).
- the drift layer 3 is formed of, for example, single crystal silicon.
- Each of trench 4 and mesa region 5 extends in the depth direction from the surface of mesa region 5.
- the trench 4 is formed, for example, with a width of about 1 ⁇ m and a depth of about 5 ⁇ m to 10 ⁇ m, but is not limited thereto.
- the mesa region 5 may have a width of, for example, 0.1 ⁇ m to 1.0 ⁇ m in the X direction, for example, 0.5 ⁇ m.
- the gate insulating film 6 is formed of, for example, a silicon dioxide (SiO 2 ) film by a thermal oxidation method.
- the gate insulating film 6 may be a silicon oxide film or a silicon nitride (Si 3 N 4 ) film which is a deposited film formed by a chemical vapor deposition (CVD) method or the like in addition to the thermal oxidation method, or a film thereof.
- a stacked film which is a plurality of combinations can be used.
- a SiO 2 film by a thermal oxidation method that is advantageous for the compactness.
- a polycrystalline silicon film (doped polysilicon film) to which an impurity is added can be adopted as a conductive film having a low specific resistance.
- Base region 9 is formed shallower than the depth of the bottom of trench 4. When a voltage equal to or higher than the threshold is applied to the gate electrode 8, a channel of the inversion layer is formed in the base region 9 immediately below the emitter region 11 and in contact with the sidewall of the trench 4.
- Emitter region 11 and contact region 12 are formed to connect the side wall portions of adjacent trenches 4 as mutually opposing side wall portions.
- the emitter region 11 and the contact region 12 are provided with the same width as the width in the X direction of the mesa region 5.
- the emitter region 11 and the contact region 12 are formed across the pair of gate insulating films 6 located opposite to each other in the X direction of the mesa region 5.
- Base region 9 is formed at a higher impurity concentration than drift layer 3.
- Emitter region 11 is formed at a higher impurity concentration than base region 9 and contact region 12.
- the contact region 12 is formed with a higher impurity concentration than the base region 9 for the purpose of reducing the contact resistance between the emitter electrode 20 and the base region 9 described later.
- Buffer layer 21 is provided at a position between drift layer 3 and collector region 22.
- the buffer layer 21 and the collector region 22 are formed at a higher impurity concentration than the drift layer 3.
- the n ⁇ -type drift layer 3 is formed, for example, with an impurity concentration of about 7 ⁇ 10 13 / cm 3 .
- the p-type base region 9 is formed, for example, at about 1 ⁇ 10 17 / cm 3 .
- the n + -type emitter region 11 is, for example, about 1 ⁇ 10 20 / cm 3
- the p + -type contact region 12 is about 3 ⁇ 10 18 / cm 3 to 3 ⁇ 10 19 / cm 3 , for example, 1 ⁇ 10
- the impurity concentration is approximately 19 / cm 3 .
- the n-type buffer layer 21 is formed at an impurity concentration of, for example, about 1 ⁇ 10 16 / cm 3
- the p + -type collector region 22 is, for example, at an impurity concentration of about 1 ⁇ 10 18 / cm 3 .
- an interlayer insulating film 15 made of, for example, a SiO 2 film is provided so as to cover the entire surfaces of the trench 4 and the mesa region 5.
- the interlayer insulating film 15 is provided with contact holes 16 penetrating the interlayer insulating film 15 so as to reach from the surface of the interlayer insulating film 15 to the surface of the mesa region 5.
- the contact holes 16 extend on the mesa region 5 along the Y direction (longitudinal direction of the mesa region 5) as shown by dotted lines in FIG.
- the contact holes 16 are provided in a striped or rectangular pattern having a width of, for example, about 0.5 ⁇ m in the X direction at the mask level.
- the contact hole 16 is selectively formed along the inner wall of the contact hole 16 and the surfaces of the emitter region 11 and the contact region 12 exposed at the bottom of the contact hole 16.
- a barrier metal film 17 is provided.
- a contact plug 19 is embedded in the contact hole 16 via the barrier metal film 17.
- the barrier metal film 17 is formed of, for example, a composite film including a titanium (Ti) film / titanium nitride (TiN) film from the lower side.
- the contact plug 19 is formed of, for example, a tungsten (W) film which is a high melting point metal.
- the barrier metal film 17 is provided for the purpose of preventing the metal atoms of the contact plug 19 from diffusing into the semiconductor of the mesa region 5.
- the barrier metal film 17 is not provided on the surface of the interlayer insulating film 15 but is selectively provided in the contact hole 16.
- an emitter electrode 20 is provided on the trench 4 and the mesa region 5 so as to cover the interlayer insulating film 15 and the contact plug 19.
- the emitter electrode 20 is electrically connected to each of the emitter region 11 and the contact region 12 via the contact plug 19 and the barrier metal film 17 provided inside the contact hole 16.
- the emitter electrode 20 is formed of, for example, an aluminum (Al) film, or an aluminum alloy film such as aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), etc. It is done.
- a protective film 23 is provided on the emitter electrode 20 so as to cover the emitter electrode 20. Although not shown, the protective film 23 is provided with a bonding opening for electrically connecting a bonding pad formed of a part of the emitter electrode 20 and the outside.
- the protective film 23 is formed of, for example, a polyimide-based insulating resin.
- a collector electrode 24 is metallurgically connected to the collector region 22 so as to make the contact resistance electrically low.
- the collector electrode 24 is formed of, for example, a composite layer containing a plurality of metals (Al, Ni, etc.) having a gold (Au) film as the outermost layer.
- a voltage higher than the built-in voltage (about 0.8 V) of the pn junction between the collector region 22 and the buffer layer 21 is applied so that the collector electrode 24 is positively biased. Electrons are injected from the emitter electrode 20 into the collector region 22 through the n + -type emitter region 11 and the channel of the p-type base region 9 and the n -- type drift layer 3. Further, holes are injected from the collector region 22 to the drift layer 3 via the buffer layer 21. Thereby, the IGBT is turned on. In this on state, the voltage drop between the emitter electrode 20 and the collector electrode 24 is the on voltage of the IGBT.
- the charge stored in the gate electrode 8 is gate drive circuit through the gate resistance. Discharged to At that time, the channel which has been inverted to n-type returns to p-type, and by the absence of the channel, the supply of electrons is not performed, and the IGBT is turned off.
- n + -type emitter regions 11 and p + -type contact regions 12 are arranged along the longitudinal direction of trench 4, and contact regions 12 adjacent to each other with emitter region 11 interposed therebetween are , And is formed deeper than the emitter region 11.
- the contact regions 12 are embedded immediately below the emitter region 11 and separated from each other.
- the depth d bc of the contact region 12 is, for example, about 1.5 ⁇ m
- the depth d e of the emitter region 11 is, for example, about 0.5 ⁇ m.
- the contact area contact width W bc which is a length measured in the Y direction (longitudinal direction of trench 4 or mesa area 5) of the surface of contact area 12, is in the Y direction of the surface of emitter area 11. It is narrower than the emitter area contact width W e which is the measured length.
- the contact region 12 and the emitter region 11 are in contact with the emitter electrode 20 via the contact plug 19 and the barrier metal film 17.
- a distance on a straight line connecting both ends of the contact / base interface 12p in the Y direction which is measured in the Y direction of the contact / base interface 12p where the p + -type contact region 12 and the p type base region 9 contact each other It is defined as "effective contact area width W eff ".
- a straight line connecting both ends of the emitter-base pn junction interface 11n1 in the Y direction measured in the Y direction of the emitter-base pn junction interface 11n1 at which the n + -type emitter region 11 and the p-type base region 9 contact each other.
- the upper distance is defined as “emitter injection width W inj ".
- the effective contact area width W eff is wider than the emitter injection width W inj .
- the contact area contact width W bc is, for example, about 2 ⁇ m
- the emitter area contact width W e is, for example, about 3 ⁇ m.
- the contact area contact width W bc is the length of the surface of the contact area 12
- the emitter area contact width W e is the length of the surface of the emitter area 11.
- the effective contact region width W eff is about 4 ⁇ m
- the emitter injection width W inj is about 1 ⁇ m.
- the half length A of the emitter injection width W inj is a curve on the sectional view along the Y direction of the pn junction interface 11n2 between the emitter and the contact where the emitter region 11 and the contact region 12 contact. It is shorter than the creepage distance d crp along.
- the semiconductor device 1A according to the first embodiment has a structure in which n + -type emitter regions 11 and p + -type contact regions 12 are alternately arranged along the Y direction. It has become. In such a structure, referring to FIG.
- the contact regions 12 adjacent to each other across the emitter region 11 are formed deeper than the emitter region 11. Furthermore, they are embedded immediately below the emitter region 11 and separated from each other. Therefore, unlike the vertical trench IGBT disclosed in Patent Document 1, the emitter injection width Winj does not relatively depend on the emitter region contact width We measured in the Y direction on the surface of the emitter region 11. As a result, the emitter injection width Winj can be narrowed without narrowing the emitter region contact width We in contact with the emitter electrode 20 via the contact plug 19 and the barrier metal film 17. Conversely, the emitter region contact width W e can be increased without increasing the emitter injection width W inj .
- the emitter injection width W inj is determined by the separation distance of the contact region 12 in the lower part of the emitter region 11, so the emitter region contact width W e is increased to lengthen the emitter region 11 itself.
- the emitter injection width Winj does not change. Accordingly, the semiconductor device 1A according to the first embodiment, without narrowing the emitter region contact width W e in the surface of the emitter region 11, the total channel length immediately below emitter region 11 to narrow the emitter injection width W inj the It can be short (low channel density). Further, the emitter region contact width W e is increased without increasing the emitter injection width W inj . As a result, it is possible to improve the latch-up resistance of the IGBT having a trench structure and to reduce the on-state voltage.
- the emitter region contact width W e may be smaller than the contact region contact width W bc . That is, the two contact regions 12 in contact with the emitter region 11 may be sandwiched between the bottom of the emitter region 11 and the emitter region 11. As shown in FIG. 5, in the structure in which n + -type emitter regions 11 and p + -type contact regions 12 are alternately arranged along the Y direction (longitudinal direction of trench 4 or mesa region 5), the region directly below emitter region 11 The p-type base region 9 is a substantial formation region of the channel.
- the emitter region contact width W e and emitter injection width W inj forms the emitter region 11 of the same length periodically, comparing the emitter region 11 and the conventional structure of continuously formed in a stripe shape along the Y-direction This tends to lower the channel density. As the channel density decreases, the on voltage may increase.
- the emitter injection width Winj should be increased .
- the voltage drop due to holes passing immediately below the emitter region 11 at the turn-off may easily latch up beyond the built-in voltage of the pn junction between the emitter region 11 and the base region 9.
- the contact regions 12 are also alternately and repeatedly arranged along with the emitter regions 11. That is, since the emitter region 11 is provided so as to connect the trenches 4 adjacent to shown in FIG. 2, if the holes to flow to the p + -type contact region 12 proceeds in the Y direction in FIG. 5 It does not.
- the voltage drop increases by the length of the emitter injection width Winj , which is the length of the emitter-base pn junction interface 11n1, and latch-up becomes easy. Therefore, in the structure in which the emitter regions 11 and the contact regions 12 are alternately arranged along the Y direction, the emitter injection width Winj , which is the length of the pn junction interface 11n1 between the emitter and the base, is absolutely predetermined length (several ⁇ m) It is difficult to extend beyond.
- each of the emitter region contact width W e and emitter injection width W inj varying the length of each of the emitter region contact width W e and emitter injection width W inj. More specifically, contact regions 12 in contact with both sides of the emitter region 11 sandwich the emitter region 11 deeper than the emitter region 11 and directly below the bottom surface of the emitter region 11.
- the length of an interval (emitter injection width W inj ) sandwiched by the contact region 12 immediately below the bottom surface of the emitter region 11 is, for example, 0.1 ⁇ m to 2.0 ⁇ m, and more preferably 0.1 ⁇ m to 2.0 ⁇ m. It is also good.
- the channel density can be increased even if the length (the number) of the emitter regions is increased by simply shortening the length in the Y direction of the contact region 12 itself relatively.
- the length (direction) of the emitter region 11 is increased by simply shortening the length of the contact region 12 itself in the Y direction relatively, then the current density of holes increases immediately below the emitter region 11.
- the reason is that the increase of electron injection also increases the concentration of holes drawn by the electrons in the channel.
- the latchup is determined not only by the resistance component of the location where the hole passes but also by the current density of the hole. Therefore, simply increasing the ratio (number) of the emitter regions 11 by relatively shortening the length in the Y direction of the contact region 12 itself makes it easy to latch up even if the channel density can be increased.
- the above-mentioned hole current density can be reduced by widening the effective contact region width W eff .
- the contact area contact width W bc is narrower than the emitter area contact width W e .
- the effective contact region width W eff is wider than the emitter injection width W inj .
- the effective contact area width W eff can be made wider than the contact area contact width W bc . For this reason, it is possible to increase the ratio of holes drawn by electrons in the channel and flowing to the p + -type contact region 12 along the potential. As a result, the hole current density immediately below the n + -type emitter region 11 decreases.
- the contact area contact width W bc on the surface of the contact area 12 is relatively narrowed and the ratio of the emitter area contact width W e is increased to increase the latch density of the emitter area 11 even if the channel density is increased. Can. Furthermore, since the channel density can be increased, the on voltage can be lowered.
- the resistivity of base region 9 immediately below emitter region 11 is higher than that of contact region 12.
- one half of the length A of the emitter injection width W inj is shorter than the creepage distance d crp. Therefore, the resistance R1 from the center of the emitter injection width W inj of the base region 9 immediately below the emitter region 11 to the contact region 12 can be reduced, and the latch-up resistance can be improved.
- contact region 12 is formed to be deeper than emitter region 11 and directly below the bottom surface of emitter region 11, hole current I hole can be dispersed to the side of contact region 12. Thus, holes accumulated immediately below the emitter region 11 can be quickly extracted to the emitter electrode 20 via the contact region 12.
- the latch-up resistance can be increased by making the contact region 12 deeper than the emitter region 11 to lower the saturation current value, but it decreases when it is too deep. Therefore, the depth d bc of the contact region is preferably 0.5 ⁇ m or more and 2 ⁇ m or less from the depth d e of the emitter region 11.
- the upper edge 17 d of the barrier metal film 17 is one step lower than the upper edge 16 d of the contact hole 16.
- the surface 19a of the contact plug 19 has a concave shape in which the central portion is recessed. As described above, by forming the surface 19 a of the contact plug 19 in a concave shape, the contact area between the contact plug 19 and the emitter electrode 20 in the upper layer of the contact plug 19 can be increased. Therefore, the contact resistance between emitter region 11 and contact region 12 and emitter electrode 20 can be reduced. As a result, even if the width of the contact hole 16 is reduced along with the miniaturization, the on-voltage of the IGBT can be reduced.
- the n -- type semiconductor substrate 3 SUB is prepared. Then, as shown in FIG. 8, a plurality of trenches 4 are formed on the main surface of the semiconductor substrate 3 SUB , and a mesa region 5 partitioned by the trenches 4 adjacent to each other is formed.
- the trench 4 and the mesa region 5 are formed in a stripe-like parallel pattern of, for example, a width of 1 ⁇ m and a depth of about 5 ⁇ m to 10 ⁇ m, as shown in FIG.
- Trench 4 is formed by selectively etching the main surface of semiconductor substrate 3 SUB by dry etching such as RIE using photolithography technology. As a result, a plurality of mesa regions 5 are arranged along the X direction (the width direction of the trench 4 or the mesa region 5).
- the gate insulating film 6 made of a SiO 2 film is formed inside the trench 4 by thermal oxidation, for example.
- gate insulating film 6 is formed on the main surface of semiconductor substrate 3 SUB and also on the upper surface of mesa region 5 and continuously formed inside trench 4 and over the upper surface of mesa region 5.
- Ru is formed as the gate material 7 so as to completely fill the inside of the trench 4 on the main surface of the semiconductor substrate 3SUB .
- the gate material 7 is formed to have a film thickness of about 1 ⁇ m for a trench width of 1 ⁇ m, for example.
- the gate material 7 is etched back by dry etching such as RIE to selectively remove the gate material 7 on the trench 4 and on the mesa region 5 as shown in FIG.
- the gate electrode 8 made of the gate material 7 is formed in the inside of the element 4.
- gate electrode 8 is selectively buried in trench 4 via gate insulating film 6, and the main surface side of semiconductor substrate 3 SUB is substantially flat.
- the gate insulating film 6 on the mesa region 5 functions as an etching stopper. Surface etching can be prevented.
- the gate insulating film 6 on the upper surface of the mesa region 5 is selectively removed by wet etching or the like to expose the upper surface of the mesa region 5.
- the p-type base region 9 is formed in the surface layer portion of the mesa region 5.
- the base region 9 is implanted with, for example, boron ions ( 11 B + ) or boron difluoride ions ( 49 BF 2 + ) as impurity ions exhibiting p-type, and then heat treatment for activating the implanted impurity ions. It is formed by applying.
- the base region 9 is formed shallower than the trench 4.
- the base region 9 is formed to a depth of about 2 to 8 ⁇ m with respect to the depth 5 to 10 ⁇ m of the trench 4.
- the base region 9 is formed after the gate electrode 8 is formed inside the trench 4, but the base region 9 forms the trench 4 in the main surface of the semiconductor substrate 3 SUB. It may be formed on the entire surface layer portion of the main surface of the semiconductor substrate 3SUB before. In this case, trench 4 is formed on the main surface of semiconductor substrate 3 SUB so as to penetrate through base region 9.
- first impurity ions exhibiting p-type conductivity are selectively implanted in the Y direction into a plurality of periodical regions in the surface layer portion of the base region 9.
- first masks RM1 as a plurality of impurity introduction masks are formed at predetermined intervals b1 in the Y direction on the surface layer portion of base region 9. .
- the first mask RM1 is formed by the entire surface to form a photosensitive resist film on the main surface of the semiconductor substrate 3 SUB, then processed the photosensitive resist film is subjected to a photosensitive and developed into a predetermined pattern Be done.
- the first mask RM1 is formed in a stripe parallel pattern extending continuously in the X direction across the trenches 4 between the mesa regions 5 adjacent to each other.
- the first masks RM1 are formed, for example, with a width a1 of about 4 ⁇ m, and are arranged at an arrangement pitch of about 2 ⁇ m and a pitch of about 6 ⁇ m along the Y direction.
- FIGS. 13 and 14 are a main part cross-sectional view showing a cross-sectional structure along the line IIIa-IIIa in FIG.
- FIG. 14 is a cross-sectional view of essential parts showing a cross-sectional structure along the line IIIb-IIIb in FIG.
- the implantation of boron ions ( 11 B + ) is performed, for example, under the conditions of a dose of about 1 ⁇ 10 15 / cm 2 to 1 ⁇ 10 16 / cm 2 and an acceleration energy of about 120 keV.
- the first impurity ion implanted region 12A which is the implanted region of the first impurity ion (boron ion ( 11 B + )), in the surface layer portion of the base region 9 has an arrangement pitch of the first mask RM1 along the Y direction.
- a plurality of arrays are periodically arranged by MP1.
- the second mask RM2 has an interval b2 in the same direction wider than the interval b1 between the adjacent first masks RM1 on the first impurity ion implanted region 12A, and has the same direction as the width a1 of the first mask RM1.
- the width a2 is narrow.
- the second mask RM2 is formed by processing the photosensitive resist film formed on the entire main surface of the semiconductor substrate 3SUB into a predetermined pattern, as in the above-described first mask RM1.
- the second mask RM2 is formed in a stripe-like parallel pattern continuously extending in the X direction so as to cross the trenches 4 between the mesa regions 5 adjacent to each other, similarly to the above-described first mask RM1. Be done.
- the second masks RM2 are formed, for example, with a width a2 of about 3 ⁇ m, and are arranged at an interval b2 of about 3 ⁇ m along the Y direction and at the same arrangement pitch as the first mask RM1.
- FIG. 16 is a cross-sectional view of relevant parts showing a cross-sectional structure taken along line IVa-IVa of FIG.
- FIG. 17 is a cross-sectional view of essential parts showing a cross-sectional structure taken along line IVb-IVb of FIG.
- the implantation of arsenic ions ( 75 As + ) is performed, for example, under conditions of a dose of about 1 ⁇ 10 15 / cm 2 to 1 ⁇ 10 16 / cm 2 and an acceleration energy of about 120 keV.
- the second impurity which is the implantation region of the second impurity ion (arsenic ion ( 75 As + )) in the surface layer portion of the base region 9 between the first impurity ion implantation regions 12A.
- the ion implantation region 11A is shallower than the first impurity ion implantation region 12A.
- a plurality of second impurity ion implanted regions 11A are arranged at the same arrangement pitch as the first impurity ion implanted regions 12A.
- the width a2 of the second mask RM2 in the Y direction is wider than the distance b1 between the first masks RM1 adjacent to each other.
- the space b2 between the second masks RM2 adjacent to each other is narrower than the width a1 of the first mask RM1 in the Y direction. Therefore, as shown in FIG. 17, a part of the second impurity ion implanted area 11A is folded on a part of the first impurity ion implanted area 12A.
- the first and second impurity ions are activated. That is, the p + -type contact region 12 is formed by the first impurity ion-implanted region 12A into which the first impurity ion (boron ion ( 11 B + )) is implanted. Further, an n + -type emitter region 11 is formed in the second impurity ion implanted region 11A into which the second impurity ion (arsenic ion ( 75 As + )) is implanted. Specifically, heat treatment for activating the implanted boron ions ( 11 B + ) and arsenic ions ( 75 As + ) is collectively performed.
- the p + -type contact region 12 is formed.
- FIG. 18 is a cross-sectional view of relevant parts at a position corresponding to the line IIa-IIa of FIG.
- FIG. 19 is a cross-sectional view of essential parts at a position corresponding to the IIb-IIb line in FIG.
- FIG. 20 is a cross-sectional view of main parts at a position corresponding to the IIc-IIc line in FIG.
- arsenic ions 75 As +
- boron ions 11 B +
- n + type a region in which a part of the region into which boron ions ( 11 B + ) are implanted and a part of the region into which arsenic ions ( 75 As + ) are implanted is n + type
- the emitter region 11 is formed.
- arsenic ions ( 75 As + ) are selectively implanted as follows. That is, the second impurity ion implanted region 11A into which the arsenic ion ( 75 As + ) is implanted is an array of a plurality of first impurity ion implanted regions 12A into which the first impurity ion (boron ion ( 11 B + )) is implanted. The spacing is wider than the spacing of the patterns.
- the second impurity ion implanted regions 11A are implanted at the same arrangement pitch as the plurality of first impurity ion implanted regions 12A and at an acceleration energy lower than that of the first impurity ions.
- the second impurity ion implanted region 11A is implanted along the Y direction into the surface layer portion of the base region 9 between the plurality of first impurity ion implanted regions 12A. For this reason, as shown in FIG. 20, the contact regions 12 adjacent to each other with the emitter region 11 formed are deeper than the emitter region 11 and have a structure in which they are directly below the emitter region 11 and separated from each other. it can.
- the emitter injection width W inj shown in FIG. 20 depends on the separation distance between the adjacent contact regions 12 in the Y direction, that is, the width a1 of the first mask RM1 in the Y direction. Therefore, it is possible to suppress the variation in the emitter injection width Winj due to misalignment between the first mask RM1 for forming the contact region 12 and the second mask RM2 for forming the emitter region 11. Further, as shown in FIG. 5, narrower than the collector region contact width W bc emitter region contact width W e, the effective contact area width W eff is able to wider structure than the emitter injection width W inj.
- the part of the second impurity ion implanted area 11A may not be folded up to about 0.3 ⁇ m at the maximum in a part of the first impurity ion implanted area 12A.
- contact regions 12 in contact with both sides of emitter region 11 are buried deeper than emitter region 11 and directly under the bottom of emitter region 11 to sandwich emitter region 11. The structure can be achieved.
- an interlayer insulating film 15 made of a SiO 2 film is formed by the CVD method, for example, on the entire main surface of the semiconductor substrate 3 SUB including the trench 4 and the mesa region 5.
- contact holes 16 are formed through the interlayer insulating film 15 so as to reach the upper surface of the mesa region 5 from the upper surface of the interlayer insulating film 15 by using a photolithography technique and a dry etching technique.
- the contact holes 16 are formed on the mesa region 5 in a stripe parallel plane pattern along the Y direction (longitudinal direction of the trench 4 or the mesa region 5), as shown by dotted lines in FIG.
- the contact hole 16 is formed over the emitter region 11 and the contact region 12 provided in the surface layer portion of the mesa region 5.
- a barrier metal film 17 is formed along the inner wall of the contact hole 16, the surface of the mesa region 5, and the surface of the interlayer insulating film 15 by, for example, the PVD method.
- the barrier metal film 17 is formed of a composite film including a titanium (Ti) film / titanium nitride (TiN) film from the lower side.
- the titanium film is formed to a film thickness of, for example, about 40 nm.
- the titanium nitride film is formed to a film thickness of, for example, about 100 nm.
- a tungsten (W) film for example, is formed as the plug material 18 by the CVD method so as to fill the inside of the contact hole 16.
- the plug material 18 is formed, for example, to have a film thickness of about 0.7 ⁇ m with respect to the 0.5 ⁇ m width of the contact hole 16.
- the tungsten film formed by the CVD method is excellent in the step coverage at the fine step portion as compared with the aluminum film or the aluminum alloy film formed by the sputtering method.
- the tungsten film can be completely filled in the inside of the contact hole 16 with a good step coverage.
- the aspect ratio (width / depth) of the width and the depth in the X direction of the contact hole 16 may be about 0.8 to 1.5.
- the plug material 18 and the barrier metal film 17 are etched back by dry etching such as RIE to selectively remove the plug material 18 on the contact hole 16 and the interlayer insulating film 15. Further, the barrier metal film 17 on the interlayer insulating film 15 is selectively removed, and as shown in FIG. 24, the contact plug 19 made of the plug material 18 is embedded in the contact hole 16. Further, the barrier metal film 17 selectively remaining in the contact hole 16 is formed. In this step, the contact plug 19 is selectively embedded in the contact hole 16 via the barrier metal film 17, and the surface side of the interlayer insulating film 15 becomes substantially flat. Further, in this step, as shown in FIG.
- contact plug 19 is provided with n + -type emitter region 11 and p + -type contact provided on the surface layer portion of base region 9 via barrier metal film 17. It is electrically connected to the area 12. Further, as shown in FIG. 24, the upper edge 17 d of the barrier metal film 17 remaining inside the contact hole 16 is one step lower than the upper edge 16 d of the contact hole 16. Further, the surface 19 a of the contact plug 19 is formed in a concave shape in which the central portion is recessed.
- the entire main surface of the semiconductor substrate 3 SUB including the upper surface of the interlayer insulating film 15 and the upper surface of the contact plug 19 is sputtered or the like to form, for example, an Al film or Al-Si, Al-Cu, Al-.
- a metal film made of an aluminum alloy film such as Cu-Si is formed.
- the metal film is patterned by etching and, as shown in FIG. 25, an emitter electrically connected to the barrier metal film 17 and the contact plug 19 in the contact hole 16 on the interlayer insulating film 15
- An electrode 20 is formed. In this step, as shown in FIG.
- emitter electrode 20 is formed of n + -type emitter region 11 and p + -type contact region 12 and contact plug 19 provided on the surface layer of p-type base region 9. It is electrically connected through the barrier metal film 17.
- the surface 19a of the contact plug 19 in contact with the emitter electrode 20 has a concave shape in which the central portion is recessed. Therefore, the contact area between emitter electrode 20 and contact plug 19 is increased as compared to the case where the surface of contact plug 19 is flat, and the contact resistance between emitter region 11 and contact region 12 and emitter electrode 20 is lowered. can do.
- the back surface of the semiconductor substrate 3SUB is ground, for example, by the back grinding method to reduce the thickness of the semiconductor substrate 3SUB .
- the n-type buffer layer 21 and the p + -type collector region 22 are formed in the surface layer portion of the back surface of the semiconductor substrate 3 SUB by the buffer layer and collector region forming step S12 of FIG. .
- phosphorus ions ( 31 P + ) are implanted as impurity ions exhibiting n-type on the back surface of the semiconductor substrate 3 SUB , and as impurity ions exhibiting p-type.
- Implant boron ions 11 B + ). Thereafter, heat treatment is performed to activate the implanted impurity ions, whereby the buffer layer 21 and the collector region 22 are formed. Buffer layer 21 is formed at a position deeper than the collector region 22 in the depth direction from the back surface of the semiconductor substrate 3 SUB, the residual of the semiconductor substrate 3 SUB is drift layer 3.
- the impurity ions for forming the n-type buffer layer 21 are implanted under the condition that the acceleration energy is higher than the impurity ions for forming the p-type collector region 22. By this process, a plurality of transistor cells 2 constituting an IGBT having a trench structure are formed in parallel.
- the semiconductor substrate 3 SUB is subjected to hydrogen annealing to recover defects generated by irradiation of charged particles in the lifetime control step S14 of FIG.
- the hydrogen annealing is performed, for example, by exposing the semiconductor substrate 3 SUB in a hydrogen atmosphere at about 360 degrees Celsius for about 60 minutes.
- hydrogen (H 2 ) can not pass through the barrier metal film 17 including a titanium film.
- barrier metal film 17 is selectively formed in contact hole 16 and is not provided on the surface of interlayer insulating film 15. Therefore, hydrogen passes through the protective film 23, the emitter electrode 20, the interlayer insulating film 15, etc.
- a collector electrode 24 is formed in the collector region 22 in a collector electrode forming step S16 of FIG.
- the method of manufacturing the semiconductor device 1A according to the first embodiment of the present invention does not require application of the lifetime control step S14 and the hydrogen annealing step S15.
- the on-voltage reduction and the switching loss (turn-off loss etc.) reduction of the IGBT is generally achieved by reducing the hole injection efficiency from the collector region 22. Therefore, if there is no need to reduce the lifetime of minority carriers, the above-mentioned lifetime control step S14 and hydrogen annealing step S15 may not be performed.
- arsenic ions ( 75 As + ) are selectively implanted as follows. That is, on the first impurity ion implanted region 12A into which the first impurity ions (boron ions ( 11 B + ) are implanted, the distance between the second masks RM2 is smaller than the distance b1 between the adjacent first masks RM1. The width a2 of the second mask RM2 is narrower than the width a1 of the first mask RM1.
- arsenic ions 75 %) are formed in the surface layer of the base region 9 between the first impurity ion implanted regions 12A. As + ) is injected. The implantation of arsenic ions ( 75 As + ) is performed by selecting an acceleration energy which makes the projection range shallower than the first impurity ions.
- contact regions 12 adjacent to each other with emitter region 11 interposed therebetween are formed deeper than emitter region 11. Be done.
- the contact regions 12 adjacent to each other with the emitter region 11 interposed therebetween may be provided immediately below the emitter region 11 so as to be separated from each other.
- the variation of the emitter injection width Winj due to the misalignment between the first mask RM1 shown in FIGS. 12 and 14 and the second mask RM2 shown in FIGS. 15 and 17 for forming the emitter region 11 is suppressed. can do.
- narrower than the collector region contact width W bc emitter region contact width W e the effective contact area width W eff is able to wider structure than the emitter injection width W inj.
- the irradiation of charged particles in the lifetime control step and the hydrogen annealing step may be performed as necessary as described above.
- hydrogen can not pass through the titanium film when performing recovery of defects generated by irradiation of charged particles in the lifetime control process of the previous stage and recovery of threshold fluctuation of the IGBT.
- the barrier metal film 17 including a titanium film is selectively formed in the contact hole 16 and is not provided on the surface of the interlayer insulating film 15. Therefore, hydrogen can be easily supplied to the main surface of the semiconductor substrate 3SUB from above the main surface side of the semiconductor substrate 3SUB through the protective film 23, the emitter electrode 20, the interlayer insulating film 15, and the like.
- the effect of hydrogen annealing that is, recovery of defects generated by irradiation of charged particles and recovery of threshold fluctuation of IGBT can be sufficiently performed.
- the barrier metal film 17 can be used, it is possible to suppress an increase in contact resistance due to diffusion of atoms in the contact plug 19. As a result, the switching speed of the IGBT can be increased.
- the barrier metal film 17 on the interlayer insulating film 15 is removed by etch back of the plug material 18, and the contact metal 16 is selectively selected.
- a barrier metal film 17 is formed.
- the number of manufacturing steps can be reduced, and cost reduction of the semiconductor device 1A having an IGBT with a high switching speed can be achieved.
- the barrier metal film 17 on the interlayer insulating film 15 is removed by etch back of the plug material 18. Further, the barrier metal film 17 selectively remaining in the contact hole 16 is formed.
- the barrier metal film 17 inside the contact hole 16 is formed in self-alignment with the contact hole 16. Therefore, it is not necessary to consider the positional deviation of the patterning of the barrier metal film 17 with respect to the position of the contact hole 16, so that the IGBT formed of the fine transistor cells 2 can be easily manufactured.
- the second impurity ions for forming the emitter region 11 and the first impurity ions for forming the contact region 12 are first of all made of the base region 9. It was injected into the surface layer. Then, although the case where heat treatment for activating these impurity ions is collectively performed to form the emitter region 11 and the contact region 12 has been described, the present invention is not limited to this. For example, each heat treatment may be performed in separate steps. In this case, any of the emitter region 11 and the contact region 12 may be formed first.
- boron ions ( 11 B + ) and boron difluoride ions ( 49 BF 2 + ), which are impurity ions exhibiting p-type, are arsenic ions ( 75 As + ) and phosphorus ions ( 31 The diffusion coefficient is large compared to P + ). Therefore, perform the heat treatment for activating the impurity ions first by implanting boron ions ( 11 B + ) and boron difluoride ions ( 49 BF 2 + ) that are p-type impurity ions first. Is preferred.
- the semiconductor device 1A which is an individual device having a single IGBT is described.
- a semiconductor device 1B in which an IGBT having a trench structure and a diode are integrated will be described.
- a part of an n ⁇ -type semiconductor substrate made of, for example, single crystal silicon is configured as the drift layer 3.
- the semiconductor device 1B according to the second embodiment is a reverse conducting IGBT (Reverse Conducting IGBT, RC-IGBT) in which an IGBT and a diode having a trench structure are connected in antiparallel to a semiconductor substrate.
- X and Y directions orthogonal to each other are defined in the main surface of the semiconductor substrate including the drift layer 3 therein.
- a plurality of trenches 4 adjacent to each other in the X direction include a transistor mesa region 5a, a diode mesa region 5b and a floating mesa region 5c.
- Mesa region 5 is partitioned.
- a plurality of trenches 4 are periodically arranged in the X direction.
- a plurality of transistor mesa regions 5a and a plurality of diode mesa regions 5b are alternately and periodically arranged along the X direction.
- the floating mesa region 5c is disposed, for example, between the transistor mesa region 5a and the diode mesa region 5b to realize an integrated structure.
- Each of the trench 4, the transistor mesa region 5a, the diode mesa region 5b, and the floating mesa region 5c constitutes a planar pattern extending in parallel in a stripe shape along the Y direction.
- the IGBT having the trench structure has a multi-cell structure in which a plurality of fine pattern transistor cells 2a are electrically connected in parallel to obtain a large current.
- the diodes also have a multi-cell structure in which a plurality of fine patterns of diode cells 2b are electrically connected in parallel to obtain high withstand voltage.
- FIGS. 29 to 31 show a semiconductor device according to the second embodiment in which one transistor cell 2a, one diode cell 2b, one transistor mesa region 5a, one diode mesa region 5b and one floating mesa region 5c are arranged. It is illustrated as part of 1B. However, the present invention is not limited to this.
- a plurality of trenches 4 adjacent to each other in the X direction are dug on the drift layer 3.
- a plurality of mesa regions 5 are defined by being sandwiched between a pair of opposing trenches 4 among the plurality of trenches 4 respectively.
- a gate insulating film 6 is provided along the inner wall of each of the plurality of trenches 4, and a gate electrode 8 is provided inside each of the trenches 4 via the gate insulating film 6.
- the transistor cell 2a is formed along the Y direction on the p-type base region 9 provided on the surface layer portion of the transistor mesa region 5a and on the surface layer portion of the base region 9. And a plurality of n + -type emitter regions 11 periodically arranged. Further, a plurality of transistor cells 2a are alternately arranged along the Y direction so as to sandwich each of emitter regions 11, formed deeper than emitter regions 11, and directly below emitter regions 11 and separated from each other. A p + -type contact region 12 is provided.
- the transistor cell 2a has a common drift layer 3 formed of a semiconductor substrate, an n-type buffer layer 21 provided on the back surface of the drift layer 3, and a collector region 22 of the second conductivity type and high impurity concentration. Have as.
- a floating mesa region 5c is formed between a diode cell 2b and a transistor cell 2a described later.
- an electrically floating p-type floating region 9a which does not form the emitter region 11 and is not electrically connected to the emitter electrode 20 is formed.
- a collector region 22 on the back surface opposite to the transistor cell 2a extends on the other main surface side (back surface) opposite to the floating mesa region 5c.
- the diode cell 2 b includes an anode region 29 of the second conductivity type provided on the surface layer portion of the diode mesa region 5 b.
- the diode cell 2 b includes a common drift layer 3 made of a semiconductor substrate, a buffer layer 21 of the first conductivity type provided on the surface layer of the back surface of the drift layer 3, and a diode on the surface layer of the back surface of the drift layer 3.
- a cathode region 22b of a first conductivity type and high impurity concentration provided opposite to the mesa region 5b.
- the anode region 29 is formed shallower than the trench 4 and is formed, for example, in the same step as the base region 9.
- Cathode region 22 b is arranged at a position shallower than buffer layer 21 in the depth direction from the back surface of drift layer 3 together with n + -type collector region 22, and collector electrode 24 provided on the back surface of drift layer 3. It is electrically and metallurgically connected.
- the cathode region 22 b is formed with a higher impurity concentration than the buffer layer 21.
- An interlayer insulating film 15 is provided so as to cover the entire surfaces of the trench 4, the transistor mesa region 5a, the diode mesa region 5b, and the floating mesa region 5c.
- the interlayer insulating film 15 is provided with a contact hole 16 a penetrating the interlayer insulating film 15 so as to reach the transistor mesa region 5 a from the surface of the interlayer insulating film 15.
- the interlayer insulating film 15 is provided with a contact hole 16 b penetrating the interlayer insulating film 15 so as to reach the diode mesa region 5 b from the surface of the interlayer insulating film 15.
- the contact hole 16a extends along the Y direction (longitudinal direction of the trench 4 or the mesa region 5a for transistor) on the transistor mesa region 5a as shown by a dotted line in FIG. 29, and the arrangement of the emitter region 11 and the contact region 12 It is provided to correspond to the position.
- the contact hole 16b extends along the Y direction (longitudinal direction of the trench 4 or the diode mesa region 5b) on the diode mesa region 5b so as to face the anode region 29, as shown by a dotted line in FIG. Is provided.
- the contact holes 16a and 16b are formed, for example, in a stripe-like parallel plane pattern with a width of 0.5 ⁇ m, like the contact holes 16 of the first embodiment described above.
- a barrier metal film 17 is provided inside the contact hole 16a, similarly to the contact hole 16 of the first embodiment.
- the barrier metal film 17 is selectively formed along the inner wall of the contact hole 16a and the surfaces of the emitter region 11 and the contact region 12 exposed at the bottom of the contact hole 16a.
- a contact plug 19 is embedded in the contact hole 16 a via the barrier metal film 17.
- a barrier selectively formed along the inner wall of the contact hole 16a and the surface of the anode region 29 exposed at the bottom of the contact hole 16b inside the contact hole 16b.
- a metal film 17 is provided.
- the contact plug 19 is also embedded in the contact hole 16 b via the barrier metal film 17.
- the barrier metal film 17 is not provided on the surface of the interlayer insulating film 15, but is selectively provided in each of the contact holes 16a and 16b.
- an emitter electrode 20 is provided on the trench 4 and the mesa region 5 so as to cover the interlayer insulating film 15 and the contact plug 19.
- the emitter electrode 20 is electrically connected to each of the emitter region 11 and the contact region 12 via the contact plug 19 and the barrier metal film 17 provided inside the contact hole 16 a.
- the emitter electrode 20 is electrically connected to the anode region 29 through the contact plug 19 and the barrier metal film 17 provided inside the contact hole 16 b.
- a protective film 23 is provided on the emitter electrode 20 so as to cover the emitter electrode 20.
- a collector electrode 24 is provided on the back surface of the drift layer 3 so as to cover the back surface.
- the collector electrode 24 is metallurgically connected with the collector region 22 and the cathode region 22b so as to have a low contact resistance.
- Contact region of the second embodiment the n + -type emitter region 11 and p + -type according to Embodiment 12, similarly to the n + -type emitter region 11 and p + -type contact region 12 of the of the first embodiment described above It is the composition of. That is, referring to FIG. 5, the p + -type contact regions 12 adjacent to each other with the n + -type emitter region 11 interposed therebetween are formed deeper than the emitter region 11. The contact regions 12 are embedded immediately below the emitter region 11 and separated from each other.
- the contact area contact width W bc of the contact area 12 is narrower than the emitter area contact width W e of the surface of the emitter area 11 in contact with the emitter electrode 20 via the contact plug 19 and the barrier metal film 17.
- the effective contact region width W eff measured in the Y direction of the contact-base interface 12 p is wider than the emitter injection width Win j measured in the Y direction of the emitter-base pn junction interface 11 n 1.
- the half length A of the emitter injection width Winj measured in the Y direction of the emitter-base pn junction interface 11n1 is a cross section along the Y direction of the emitter junction pn junction interface 11n2. The creeping distance d crp along the curved surface in the figure is shorter.
- the barrier metal film 17 and the contact plug 19 according to the second embodiment have the same configuration as the barrier metal film 17 and the contact plug 19 according to the above-described first embodiment. That is, referring to FIG. 7, the upper edge 17d of the barrier metal film 17 is one step lower than the upper edge 16d of the contact hole 16 corresponding to the contact holes 16a and 16b. In addition, the surface 19a of the contact plug 19 has a concave shape in which the central portion is recessed.
- the semiconductor device 1B according to the second embodiment includes a diode cell 2b that constitutes a diode, and a mesa region 5c for floating. Therefore, the semiconductor device 1B according to the second embodiment is formed by substantially the same manufacturing method as the semiconductor device 1A according to the first embodiment described above mainly by changing the mask pattern for impurity introduction. Can. Therefore, also in the semiconductor device 1B according to the second embodiment configured as described above, the same effects as those of the semiconductor device 1A according to the above-described first embodiment can be obtained.
- a semiconductor device 1C according to the third embodiment of the present invention has substantially the same configuration as the semiconductor device 1A according to the first embodiment of the present invention described above, as shown in FIGS. , The configuration of the gate insulating film 36 is different.
- a semiconductor device 1C according to the third embodiment includes a gate insulating film 36 having a different film thickness, instead of the gate insulating film 6 of the first embodiment.
- a semiconductor device 1C according to the third embodiment of the present invention is configured of a part of a semiconductor substrate, similarly to the semiconductor device 1A according to the first embodiment described above.
- a drift layer 3 is provided.
- the gate electrode 8 provided.
- the p-type base region 9 provided in the surface layer portion of the mesa region 5 and the surface layer portion of the base region 9 are periodically provided in plural along the Y direction.
- the semiconductor device 1C according to the third embodiment is alternately disposed along the Y direction so as to sandwich each of the emitter regions 11, is formed deeper than the emitter regions 11, and It is provided with p + -type contact regions 12 which are directly below and separated from each other.
- the semiconductor device 1C according to the third embodiment includes the interlayer insulating film 15 provided on the drift layer 3 so as to cover the emitter region 11 and the contact region 12.
- the interlayer insulating film 15 is provided with a contact hole 16 provided opposite to the emitter region 11 and the contact region 12.
- the semiconductor device 1C according to the third embodiment is provided inside the contact hole 16 and selectively along the surfaces of the emitter region 11 and the contact region 12 exposed at the inner wall of the contact hole 16 and the bottom of the contact hole 16.
- a barrier metal film 17 is provided.
- the contact plug 19 provided inside the contact hole 16 via the barrier metal film 17 and the contact plug 19 provided on the interlayer insulating film 15 are provided. And an emitter electrode 20.
- the gate insulating film 36 has a first portion 36a (see FIGS. 32 and 33) provided at least between the base region 9 immediately below the emitter region 11 and the gate electrode 8. Have.
- the gate insulating film 36 also has a second portion 36 b (see FIGS. 32 and 34) provided at least between the base region 9 immediately below the contact region 12 and the gate electrode 8.
- the gate insulating film 36 has the first portion 36 a provided on the side wall of the trench 4 at a position sandwiching the base region 9 immediately below the emitter region 11 at least.
- the gate insulating film 36 is formed to have a film thickness thicker than that of the first portion 36a, and is provided on the sidewall of the trench 4 at a position sandwiching the base region 9 immediately below the contact region 12 at least. have.
- the gate insulating film 36 is formed to have a film thickness thicker than that of the first portion 36a, and a third portion 36c provided at least at the bottom of the trench 4 (between the drift layer 3 and the gate electrode 8). (See FIG. 33 and FIG. 34).
- the first portion 36a, the second portion 36b and the third portion 36c are respectively integrally formed integrally.
- the first portion 36 a extends from between the base region 9 immediately below the emitter region 11 and the gate electrode 8 to between the base region 9 immediately below the contact region 12 and the gate electrode 8. Is provided. In the Y direction, part of the first portion 36 a protrudes to the side of the base region 9 immediately below the contact region 12 and is connected to the second portion 36 b. Further, as shown in FIG. 33, the first portion 36a is provided from between the base region 9 immediately below the emitter region 11 and the gate electrode 8 to between the emitter region 11 and the gate electrode 8 Extend to the side of the emitter region 11 and terminate at the upper surface of the mesa region 5.
- the first portion 36 a extends from between the base region 9 immediately below the emitter region 11 and the gate electrode 8 to between the bottom of the trench 4 and the gate electrode 8 (between the drift layer 3 and the gate electrode 8). Is provided. A portion of the first portion 36 a protrudes to the bottom side (drift layer 3 side) of the trench 4 and is connected to the third portion 36 c.
- the second portion 36b also extends from between the base region 9 immediately below the contact region 12 and the gate electrode 8 to between the contact region 12 and the gate electrode 8 It is provided throughout. A portion of the second portion 36 b protrudes toward the contact region 12 and terminates at the surface of the mesa region 5. The second portion 36 b also extends from between the base region 9 and the gate electrode 8 immediately below the contact region 12 to between the bottom of the trench 4 and the gate electrode 8 (between the drift layer 3 and the gate electrode 8). Is provided. A portion of the second portion 36 b protrudes to the bottom side (drift layer 3 side) of the trench 4 and is connected to the third portion 36 c.
- the first portion 36 a is formed of, for example, a SiO 2 film made of a thermal oxide film by a thermal oxidation method.
- the second portion 36 b and the third portion 36 c are formed of, for example, a SiO 2 film made of a deposited film by a deposition method such as a CVD method.
- the first portion 36a is formed to have a film thickness of, for example, about 100 nm.
- the second portion 36 b is formed to have a film thickness of, for example, about 150 nm.
- the third portion 36c is formed to have a film thickness of, for example, about 200 nm.
- the charge of the channel in the base region 9 immediately below the emitter region 11 via the gate insulating film 36 provided between the base region 9 immediately below the emitter region 11 and the gate electrode 8 Is induced. Therefore, the first portion 36 a provided between the base region 9 immediately below the emitter region 11 and the gate electrode 8 substantially functions as a gate film for inducing channel charge.
- the second portion 36b between the base region 9 immediately below the contact region 12 and the gate electrode 8 and the third portion 36c provided at the bottom of the trench 4 substantially form a gate film for inducing channel charge.
- the film thickness of the second portion 36b and the third portion 36c is larger than that of the first portion 36a.
- the gate-emitter capacitance, and Gate-collector capacitance can be reduced.
- the switching time and switching loss of the trench IGBT can be improved.
- the switching speed of the IGBT having a trench structure can be increased.
- the width of the mesa region 5 tends to be narrowed to increase the number of mesa regions 5.
- the number of trenches 4 also increases, and the second portion 36 b and the third portion 36 c that do not function as gate films that substantially induce channel charge inevitably increase. Therefore, as in the semiconductor device 1C according to the third embodiment, making the film thickness of the second portion 36b and the third portion 36c thicker than the first portion 36a increases the switching speed of the IGBT. It is useful in
- the semiconductor device 1C according to the third embodiment is substantially the same as the method of manufacturing the semiconductor device 1A according to the first embodiment described above except for the step of forming the gate insulating film 36. And detailed description of the other steps is omitted.
- n -- type semiconductor substrate 3 SUB is prepared. Thereafter, the same steps as those in the first embodiment described above are performed to form trenches 4 on the main surface of the semiconductor substrate 3 SUB as shown in FIG. 8 and to be sandwiched between the trenches 4 adjacent to each other in the X direction. To form a partitioned mesa region 5.
- a deposition film 31 made of a SiO 2 film is formed by, eg, CVD so as to completely fill the inside of the trench 4 on the main surface of the semiconductor substrate 3SUB .
- the deposited film 31 is formed to have a film thickness of about 1 ⁇ m for a trench width of 1 ⁇ m, for example.
- the deposited film 31 is etched back by dry etching such as RIE.
- dry etching such as RIE.
- FIG. 37 is a plan view of relevant parts showing a plan pattern of the etching mask.
- FIG. 38 is a cross-sectional view of essential parts showing a cross-sectional structure along the line VIIa-VIIa in FIG. 39 is a cross-sectional view of essential parts showing a cross-sectional structure along the line VIIb-VIIb in FIG.
- the third mask RM3 is a stripe in which first portions m3a as shown in FIGS. 37 and 38 and second portions m3b as shown in FIGS. 37 and 39 are alternately arranged along the Y direction.
- the first portion m3a has a width xa in the X direction substantially equal to the width 5x in the X direction of the mesa region 5, and the second portion m3b has a width xb in the X direction the width 5x of the mesa region 5 in the X direction. It is wider than.
- the side surfaces opposite to each other in the X direction of the first portion m3a are flush with the side surfaces opposite to each other in the X direction of the mesa region 5.
- the side surfaces opposite to each other in the X direction of the second portion m3b are located outside the side surfaces opposite to each other in the X direction of the mesa region 5.
- the dimensional difference between the position of the side surface of the second portion m3b and the position of the side surface of the mesa region 5 corresponds to the film thickness of the second portion 36b of the gate insulating film 36.
- the width xa of the first portion m3a is, for example, about 0.5 ⁇ m
- the width xb of the second portion m3b is, for example, about 0.7 ⁇ m.
- the third mask RM3 has a predetermined pattern of a photosensitive resist film formed on the entire main surface of the semiconductor substrate 3SUB. It is formed by processing into.
- the deposited film 31 embedded in the trench 4 is sequentially etched from the surface by highly directional dry etching such as RIE or ion milling.
- highly directional dry etching such as RIE or ion milling.
- a deposited film 31c remaining in a film thickness of, for example, about 200 nm is formed at the bottom of the trench 4 between the third masks RM3.
- a deposited film 31b is formed on the side wall of the mesa region 5 immediately below the second portion m3b of the third mask RM3 to a film thickness of, for example, about 150 nm.
- the deposited film 31 c is formed in a stripe shape along the longitudinal direction (Y direction) of the trench 4 and the mesa region 5.
- the deposited film 31 b extends from the top to the bottom of the mesa region 5 and is integrally connected to the deposited film 31 c.
- the deposited film 31b is not formed on the side wall of the mesa region 5 immediately below the first portion m3a of the third mask RM3, as shown in FIG. That is, the deposition film 31 c is formed on the sidewalls of the mesa region 5 so as to periodically expose the sidewalls of the mesa region 5 along the longitudinal direction (Y direction) of the mesa region 5.
- thermal oxidation is applied to form a sidewall of the mesa region 5 on the portion not covered with the deposited film 31b and the deposited film 31c as shown in FIG.
- a thermal oxide film 32 made of, for example, a SiO 2 film with a thickness of about 100 nm is formed. That is, the thermally oxidized film 32 having a thickness smaller than that of the deposited film 31 b and the deposited film 31 c is formed on the exposed portion of the side wall of the mesa region 5 between the deposited films 31 b adjacent in the longitudinal direction (Y direction) of the mesa region 5.
- Y direction longitudinal direction
- a thermal oxide film 32 is also formed on the upper surface of mesa region 5. Further, in this step, the gate insulating film 36 having the first portion 36a of the thermal oxide film 32, the second portion 36b of the deposition film 31b, and the third portion 36c of the deposition film 31c is formed. Be done.
- the gate material 7 is formed on the main surface of the semiconductor substrate 3 SUB so as to completely fill the inside of the trench 4. Thereafter, the gate material 7 is etched back by dry etching such as RIE to form a gate electrode 8 inside the trench 4 as shown in FIG. In this process, a thermal oxide film 32 is formed on the upper surface of mesa region 5. Therefore, as in the first embodiment described above, by etching back the gate material 7 at an etching rate having selectivity to the thermal oxide film 32, the thermal oxide film on the mesa region 5 functions as an etching stopper. , Etching of the upper surface of the mesa region 5 can be prevented.
- the same steps as in the first embodiment described above are performed to obtain a p-type base region 9, an n + -type emitter region 11, a p + -type contact region 12, an interlayer insulating film 15, a contact hole 16, The barrier metal film 17, the contact plug 19, etc. are formed. Further, the emitter electrode 20, the n-type buffer layer 21, the p + -type collector region 22, the protective film 23, the collector electrode 24 and the like are formed by performing the same steps as in the first embodiment. In addition, by performing the lifetime control step (S14) and the hydrogen annealing step (S15), the wafer process of the semiconductor device 3C according to the third embodiment of the present invention is almost completed.
- the gate insulating films 36 having different thicknesses can be formed.
- the first portion 36a of the gate insulating film 36 is the base region 9 immediately below the contact region 12 from between the base region 9 immediately below the emitter region 11 and the gate electrode 8. And the gate electrode 8. Then, as shown in FIGS. 32 and 33, when a part of the first portion 36a of the gate insulating film 36 protrudes to the side of the base region 9 immediately below the contact region 12 and is connected to the second portion 36b.
- the present invention is not limited to this.
- the gate insulating film 36 has a second portion 36 b between the base region 9 immediately below the contact region 12 and the gate electrode 8 to the region between the base region 9 immediately below the emitter region 11 and the gate electrode 8. May be provided. Then, a part of the gate insulating film 36 may protrude to the side of the base region 9 immediately below the emitter region 11 to be connected to the first portion 36 a.
- the width of the second portion m3b in the Y direction is widened, and the width of the first portion 3ma in the Y direction is narrowed, whereby the gate insulating film 36 is easily formed.
- the width in the Y direction of the second portion 36b can be increased. Further, the width in the Y direction of the first portion 36a can be narrowed.
- FIG. 46 is a cross-sectional view of essential parts at a position corresponding to the IIc-IIc line in FIG.
- FIG. 47 is a cross-sectional view of essential parts at a position corresponding to the line IIa-IIa of FIG.
- the thickness of the gate insulating film 46 located at the same height as the resistance lowering layer 41 of the semiconductor device according to the fourth embodiment may be thinner than the gate insulating film 46 at other positions.
- the thickness of the region of the gate insulating film 46 located at the same height as the resistance lowering layer 41 is set to the emitter region 11 on the upper side of the resistance lowering layer 41 and the base region on the lower side of the resistance lowering layer 41. 9 and the region under the base region 9 in contact with the drift layer 3 are thinner than the gate insulating film 46.
- the thickness of the portion of the gate insulating film 46 located at the same height as the resistance lowering layer 41 is thin by providing a recess in which the interface side with the gate electrode 48 is recessed toward the resistance lowering layer 41, as shown in FIG. It has been
- the thickness t of the thinned region is set in consideration that the surface potential of the surface of the low resistance layer 41 on the sidewall side of the trench 4 changes when the gate voltage is applied, and a desired inversion layer is formed. There is.
- the structures of the semiconductor device 1D according to the fourth embodiment other than the resistance lowering layer 41 and the gate insulating film 46 are the same as or similar to those in the semiconductor devices according to the first to third embodiments. Since this is equivalent to each of the members, layers or regions, redundant description will be omitted.
- the semiconductor device 1D according to the fourth embodiment by providing the high concentration low resistance layer 41 below the emitter region 11, the resistance of the region below the emitter region 11 is reduced. And the pn junction becomes difficult to conduct.
- the semiconductor device 1D according to the fourth embodiment can be made difficult to latch up by suppressing the potential rise in the region of the resistance reduction layer 41 when the hole current flows during the turn-off operation. Further, it is possible to increase the channel density by increasing the emitter region contact width W e, and it is possible to reduce the on voltage.
- the thickness of the gate insulating film 46 at the position in contact with the resistance reducing layer 41 is thin. If the thickness of the gate insulating film 46 is made uniform along the sidewall of the trench 4, it becomes difficult to form an inversion layer on the surface of the resistance reducing layer 41 under the emitter region 11, and the gate threshold voltage rises. It becomes difficult for the device to turn on. Therefore, control of the surface potential of the resistance reducing layer 41 is facilitated by making the thickness of the gate insulating film 46 at a position in contact with the resistance reducing layer 41 relatively thinner than that of the end region. It is possible to suppress the rise. As described above, by combining the installation of the resistance reduction layer 41 and the control of the film thickness of the gate insulating film 46, it is difficult to latch up, and an increase in gate threshold voltage is suppressed according to the fourth embodiment. A semiconductor device can be provided.
- the thickness of the gate insulating film at a position in contact with the top of the drift layer 3 below the emitter region 11 and not further between the emitter region 11 and the base region 9 is thinner than that at other positions.
- a reverse bias is applied to the gate electrode, the conductivity type of the portion of the drift layer 3 in the vicinity of the gate is inverted, and there is an advantage that high withstand voltage can be achieved.
- the concentration of the base region 9 is thin and the resistance is high, the pn junction is likely to be conducted, and there is a problem that latch-up tends to cause destruction of the semiconductor device.
- the thickness of the gate insulating film 46 between the emitter region 11 and the base region 9 instead of the upper portion of the drift layer 3 is thinner than the other portions. Because it becomes difficult to latch up.
- the other effects of the semiconductor device 1D according to the fourth embodiment are similar to those of the semiconductor device according to the first embodiment.
- FIGS. 49 to 59 are main-portion cross-sectional views at positions corresponding to the line IIa-IIa of FIG.
- the manufacturing method of the semiconductor device 1A according to the first embodiment described above is substantially the same as that of the first embodiment except for the steps of forming the resistance lowering layer 41, the gate insulating film 46, and the gate electrode 48. It is the same. Therefore, the process for forming each of the resistance lowering layer 41, the gate insulating film 46, and the gate electrode 48 is specifically described, and the detailed description of the other processes is omitted.
- the n -- type semiconductor substrate 3 SUB is prepared.
- an insulating film 45 is formed on the upper surface of the semiconductor substrate 3SUB by a thermal oxidation method or the like.
- the insulating film 45 also functions as an etching stopper that can withstand a plurality of insulating film formation processes described later.
- the insulating film 45 illustrated in FIG. 49 is formed much thicker than the gate insulating film described later.
- B2 Next, the same steps as those in the first embodiment described above are performed to form trenches 4 on the main surface of the semiconductor substrate 3 SUB using the insulating film 45 as an etching mask as shown in FIG. In the X direction, the mesa region 5 partitioned by the trenches 4 adjacent to each other is formed.
- a first gate insulating film 46a made of a SiO 2 film is formed on the inner side of the trench 4 to a predetermined film thickness by, eg, thermal oxidation.
- the thickness of the side wall of the insulating film 45 on the semiconductor substrate 3SUB is also grown by thermal oxidation.
- the thickness of the thermal oxide film newly formed on the side wall of insulating film 45 and the thickness of the thermal oxide film formed on the side wall of trench 4 are represented by the same thickness, but this is a schematic expression .
- the thickness of the thermal oxide film grown on the side wall of the insulating film 45 is thinner than the thickness of the thermal oxide film grown on the side wall of the trench 4.
- a low specific resistance doped polysilicon film which functions as the first gate electrode 48a is deposited inside the first gate insulating film 46a to bury the trench 4.
- the doped polysilicon film is etched back by RIE or the like, and the upper surface of the doped polysilicon film is the position of the lower surface of resistance lowering layer 41 to be formed in the process described later. Adjust the amount of etch back so that The doped polysilicon film left by the etch back becomes the first gate electrode 48a.
- the second gate insulating film 46b is formed over the upper surface and the side surface of the insulating film 45, the inner wall surface of the upper portion of the trench 4, the upper end surface of the first gate insulating film 46a and the upper surface of the first gate electrode 48a. .
- the second gate insulating film 46b illustrated in FIG. 54 is formed thinner than the first gate insulating film 46a.
- a gate material which is to function as the second gate electrode 48b is It is deposited by the CVD method to backfill the trench 4.
- the gate material in addition to doped polysilicon, high melting point metals such as tungsten (W), molybdenum (Mo), titanium (Ti) and the like can be used.
- the upper portion of the gate material is etched back to form a second gate electrode 48b, and as shown in FIG. 56, the thickness of the second gate electrode 48b is controlled to have a predetermined dimension. That is, the thickness of the second gate electrode 48b is set by etching back so that the upper surface thereof is aligned with the upper surface of the low resistance layer 41 to be formed in the process described later.
- a third gate insulating film 46c such as an SiO 2 film or a silicon nitride film (Si 3 N 4 film) is formed in the trench 4 exposed to the etched back space. Is formed with a constant film thickness by, for example, a CVD method.
- the third gate insulating film 46c is formed over the surface of the second gate insulating film 46c and the upper surface of the second gate electrode 48b.
- the third gate insulating film 46 c may be substantially equal to the thickness of the first gate insulating film 46 a in combination with the thickness t of the second gate insulating film 46 b as illustrated in FIG. Or even thicker.
- the portion of the upper surface of the second gate electrode 48b has a high directivity such as RIE. It is selectively removed by dry etching to expose the upper surface of the second gate electrode 48b.
- the portion of the third gate insulating film 46c which has been selectively removed and the first gate insulating film 46a and the second gate insulating film 46b are integrated to form the gate insulating film 46 as shown in FIG. Become.
- the gate material to function as the third gate electrode 48c is made continuous with the second gate electrode 48b by, for example, the CVD method. Deposit and backfill the space at the top of the trench 4.
- this gate material for example, doped polysilicon, refractory metal, silicide of refractory metal or polycide can be used.
- the upper surface of the gate material is etched back to a level shown in FIG. 59 to form a third gate electrode 48c.
- the third gate electrode 48c of the remaining portion after the etch back, the first gate electrode 48a and the second gate electrode 48b are integrated to form a gate electrode 48 as shown in FIG.
- the first impurity ions exhibiting p-type are selectively implanted along the Y direction so that the contact region 12 is formed as described in FIGS. Do.
- first impurity ions exhibiting p-type conductivity are selectively implanted between the regions into which the plurality of first impurity ions are implanted so that the resistance lowering layer 41 is formed.
- a second impurity ion exhibiting n-type is selectively implanted so that the emitter region 11 is formed.
- the resistance reduction layer 41 is formed under the emitter region 11 by selecting the diffusion constant and the projection distance of the first impurity ion and the second impurity ion, respectively.
- the respective steps are performed in the same manner as described with reference to FIGS.
- the low resistance layer 41 is subjected to an activation process so as to be positioned at the same height as the second gate electrode 48 b and the second gate insulating film 46 b.
- the semiconductor device 1D according to the fourth embodiment as shown in FIGS. 46 to 48 can be manufactured.
- the thickness of the gate insulating film 56 at the position in contact with the resistance reducing layer 41 is selectively thinned to facilitate the formation of the inversion layer.
- the thickness of the membrane 56 may also be thin.
- 60 is a cross-sectional view of essential parts at a position corresponding to the line IIa-IIa of FIG.
- the region in contact with resistance lowering layer 41 and emitter region 11 is provided to have a thickness thinner than the thickness of gate insulating film 56 in the region in contact with base region 9 and extend in the vertical direction with a constant thickness. The illustrated state is illustrated.
- the gate insulating film 56 in the case of a structure in which the thickness of the gate insulating film 56 is reduced not only in the region in contact with the resistance reducing layer 41 but also in the region in contact with the resistance reducing layer 41 and the emitter region 11, the gate insulating film 56. And the manufacturing process for forming the gate electrode 58 is simplified. Specifically, the need to form the third gate insulating film 46c as shown in FIG. 57 can be eliminated. Further, the third gate electrode 48c can be integrally formed in a single manufacturing step without performing the manufacturing step of the third gate electrode 48c separately from the manufacturing step of the second gate electrode 48b as shown in FIG. Therefore, the method of manufacturing the semiconductor device according to the fourth embodiment can be simplified, and the productivity can be improved.
- the gate electrode 48 is formed to such a depth that the highest position of the upper surface of the gate electrode 48 is at the same position as the upper surface of the emitter region 11.
- the gate electrode may be formed lower than in the case shown in FIG. 47 so that the upper surface of the gate electrode is aligned with the upper surface of the resistance reducing layer 41.
- the third gate insulating film 46 c shown in FIG. 57 is formed thick enough to back the inside of the trench 4.
- the second gate electrode 48b functions as the top layer of the gate electrode. Thereafter, by filling the via plug in the contact hole (via hole), electrical connection between the second gate electrode 48b and the surface wiring can be made.
- the other steps are the same as in the method of manufacturing the semiconductor device 1D according to the fourth embodiment described above.
- the second modification of the fourth embodiment in which the upper surface of the gate electrode is lower than the lower surface of the emitter region 11 in this manner, the parasitic capacitance between the emitter and the gate can be reduced. Formation can be facilitated.
- the present invention is not limited to this, and after the surface structure such as the emitter region 11 and the low resistance layer 41 is formed, the gate electrode can be formed by changing the process order to form the trench 4 as shown in FIG. The freedom of choice of materials is improved.
- the present invention has been specifically described based on the above-described first to fourth embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. Of course, it can be changed.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
またトレンチ構造のIGBTとして、互いに隣り合うトレンチで挟まれた島領域に、この島領域の長手方向に沿ってn型エミッタ領域及びp型コンタクト領域を交互に配置したIGBTがある。このIGBTにおいては、n型エミッタ領域とp型ベース領域とのpn接合界面の島領域長手方向に測ったエミッタ注入幅を狭くしてゲート幅を狭くすることで、寄生サイリスタに対するラッチアップ耐量を向上させることができる。
特に、トレンチ構造のIGBTでは、高電流密度化を図るために、島領域の幅を狭くして島領域の数を多くする傾向にある。そのため、島領域の幅を狭くすることでn型エミッタ領域の表面積が縮小し、エミッタ電極とのコンタクト抵抗が増加するので、島領域の微細化を図る上でもエミッタ領域の表面積はできるだけ確保する必要がある。
また図2、図3、図7乃至図11、図13、図16乃至図19、図21乃至図27、図30、図31、図33乃至図36、図38乃至図44、図47乃至図60では、水平方向をX方向と定義している。図4乃至図6、図14、図17、図20、図46では、水平方向をY方向と定義している。
なお、図5及び図6においては、図面を見易くするため、断面を表すハッチングを省略している。
<第1の実施形態に係る半導体装置の構造>
本発明の第1の実施形態に係る半導体装置1Aとしては、図1乃至図4に示すように、半導体基板の一部をドリフト層3として構成したトレンチ構造のIGBTを例示的に説明する。
図1に示すように、ドリフト層3を内部に含む半導体基板の主面内には互いに直交するX方向及びY方向が定義され、図2に示すように、X方向に互いに隣り合うトレンチ4でメサ領域5がそれぞれ区画される。図1から分かるように、トレンチ4及びメサ領域5の各々は、X方向に沿って複数個周期的に配置され、かつY方向に沿ってストライプ状に平行に延伸する平面パターンを構成している。
トレンチ構造のバイポーラトランジスタは、微細パターンのトランジスタセル2を電気的に複数個並列に接続している。これにより、大電流を得るマルチセル構造になっている。図1乃至図3は、これに限定されないが、第1の実施形態に係る半導体装置1Aの一部としてトランジスタセル2及びメサ領域5がそれぞれ3つ配列された部分を例示的に示している。
このゲート絶縁膜6を介して、ゲート電極8がトレンチ4の内部のそれぞれに設けられている。また、図1乃至図3から分かるように、トランジスタセル2のそれぞれには、メサ領域5の表層部に設けられた第2導電型(p型)のベース領域9を備える。
また、このベース領域9の表層部には、Y方向に沿って周期的に複数個配置された第1導電型(n+型)のエミッタ領域11を備える。また、エミッタ領域11のそれぞれを挟むように、第2導電型(n+型)のコンタクト領域12を備えている。
また、複数のトランジスタセル2は、共通領域として、半導体基板からなる共通のドリフト層3と、ドリフト層3の裏面に設けられた第1導電型(n型)のバッファ層21及び第2導電型(p+型)のコレクタ領域22とを備えている。
ドリフト層3は、例えば単結晶シリコンで形成されている。トレンチ4及びメサ領域5の各々は、メサ領域5の表面から深さ方向に伸びている。トレンチ4は、例えば幅1μm程度、深さ5μm~10μm程度で形成されているが、これに限定されない。また、メサ領域5は、X方向における幅が例えば0.1μm~1.0μmで、例えば0.5μmであってもよい。
特に高耐圧が要求されるパワーデバイス(電力用半導体装置)においては緻密性に有利な熱酸化法によるSiO2膜を用いることが好ましい。
ゲート電極8には、例えば不純物が添加された多結晶シリコン膜(ドープドポリシリコン膜)が低比抵抗な導電膜として採用可能である。ベース領域9はトレンチ4の底部の深さよりも浅く形成されている。ゲート電極8に閾値以上の電圧が印加されると、エミッタ領域11の直下であってトレンチ4の側壁に接するベース領域9には、反転層のチャネルが形成される。
ベース領域9は、ドリフト層3よりも高不純物濃度で形成されている。エミッタ領域11は、ベース領域9及びコンタクト領域12よりも高不純物濃度で形成されている。コンタクト領域12は、後述するエミッタ電極20とベース領域9とのコンタクト抵抗を低減する目的でベース領域9よりも高不純物濃度で形成されている。
バッファ層21は、ドリフト層3とコレクタ領域22との間の位置に設けられている。バッファ層21及びコレクタ領域22は、ドリフト層3よりも高不純物濃度で形成されている。
また、n型のバッファ層21は例えば1×1016/cm3程度、p+型のコレクタ領域22は例えば1×1018/cm3程度の不純物濃度で形成することが好ましい。
コンタクト孔16は、図1に点線で示すように、メサ領域5上をY方向(メサ領域5の長手方向)に沿って延在する。コンタクト孔16は、マスクレベルでは例えばX方向の幅が0.5μm程度のストライプ状又は矩形のパターンとなるように設けられている。
バリアメタル膜17は、例えば下側からチタン(Ti)膜/チタンナイトライド(TiN)膜を含む複合膜で形成されている。コンタクトプラグ19は例えば高融点金属であるタングステン(W)膜で形成されている。バリアメタル膜17は、コンタクトプラグ19の金属原子がメサ領域5の半導体中に拡散するのを防止する目的で設けられている。
これは、コンタクトプラグ19の金属原子がメサ領域5の半導体中に拡散するとメサ領域5にダメージを与え、コンタクト抵抗が増加するためである。バリアメタル膜17は、層間絶縁膜15の表面上には設けられておらず、コンタクト孔16の内部に選択的に設けられている。
エミッタ電極20は、例えばアルミニウム(Al)膜、又はアルミニウム・シリコン(Al-Si),アルミニウム・銅(Al-Cu),アルミニウム・銅・シリコン(Al-Cu-Si)などのアルミ合金膜で形成されている。
コレクタ領域22にはコレクタ電極24が電気的に低い接触抵抗をなすように、かつ金属学的に接続されている。コレクタ電極24は、例えば金(Au)膜を最表層とする複数の金属(Al、Ni等)を含む複合層で形成されている。
次に、第1の実施形態に係る半導体装置の動作について、図2及び図3を用いて説明する。
エミッタ電極20に第1の基準電位(例えば0V)を印加し、コレクタ電極24に第1の基準電位よりも高い第2の基準電位(例えば650V)を印加した状態で、ゲート電極8の電圧が閾値よりも低い電圧ではIGBTはオフ状態である。
次に、IGBTのエミッタ電極20とコレクタ電極24の電位差を0Vとする。図示しないゲート駆動回路よりゲート抵抗を介して閾値より高い電圧をゲート電極8に印加すると、p型のベース領域9のうち、ゲート絶縁膜6を介してゲート電極8と対向している部分にn型の反転層が形成される。この反転層がチャネルとなる。
さらにコレクタ領域22からバッファ層21を介してドリフト層3に正孔が注入される。これにより、IGBTはオン状態となる。このオン状態において、エミッタ電極20とコレクタ電極24との間の電圧降下がIGBTのオン電圧である。
IGBTをオン状態からオフ状態にするには、エミッタ電極20とゲート電極8との間の電圧を閾値以下にすることによって、ゲート電極8に蓄積されていた電荷はゲート抵抗を介してゲート駆動回路へ放電される。
その際、n型に反転していたチャネルがp型に戻り、チャネルが無くなることにより電子の供給がなされなくなり、IGBTがオフ状態になる。
次に、エミッタ領域11及びコンタクト領域12について説明する。
図5に示すように、n+型のエミッタ領域11とp+型のコンタクト領域12はトレンチ4の長手方向に沿って複数個が配列され、エミッタ領域11を挟んで互いに隣り合うコンタクト領域12は、エミッタ領域11よりも深く形成されている。
そして、コンタクト領域12は、エミッタ領域11の直下に廻り込んで互いに離間している。コンタクト領域12の深さdbcは例えば1.5μm程度、エミッタ領域11の深さdeは例えば0.5μm程度になっている。
また、p+型のコンタクト領域12とp型のベース領域9とが接するコンタクト・ベース間界面12pのY方向に測った、コンタクト・ベース間界面12pのY方向の両端を結ぶ直線上の距離を「実効コンタクト領域幅Weff」と定義する。また、n+型のエミッタ領域11とp型のベース領域9とが接するエミッタ・ベース間pn接合界面11n1のY方向に測った、エミッタ・ベース間pn接合界面11n1のY方向の両端を結ぶ直線上の距離を「エミッタ注入幅Winj」と定義する。
実効コンタクト領域幅Weffは、エミッタ注入幅Winjよりも広くなっている。第1の実施形態では、以下の値に限定されないが、例えば、コンタクト領域接触幅Wbcは2μm程度、エミッタ領域接触幅Weは3μm程度になっている。
コンタクト領域接触幅Wbcはコンタクト領域12の表面の長さであり、エミッタ領域接触幅Weはエミッタ領域11の表面の長さである。また、実効コンタクト領域幅Weffは4μm程度、エミッタ注入幅Winjは1μm程度になっている。
第1の実施形態に係る半導体装置1Aは、図1乃至図4に示すように、n+型のエミッタ領域11とp+型のコンタクト領域12とがY方向に沿って交互に配置された構造になっている。このような構造では、図5を参照すれば、エミッタ注入幅Winjを狭くしてエミッタ領域11直下のゲート幅を狭くすることで、寄生サイリスタに対するラッチアップ耐量を向上させることができる。
また、エミッタ領域接触幅Weを広くしてエミッタ領域11の表面積を大きくすることで、低オン抵抗化を図ることができる。
その結果、コンタクトプラグ19及びバリアメタル膜17を介してエミッタ電極20に接触するエミッタ領域接触幅Weを狭くすることなく、エミッタ注入幅Winjを狭くすることができる。逆に言えば、エミッタ注入幅Winjを広くすることなく、エミッタ領域接触幅Weを広くすることができる。
したがって、第1の実施形態に係る半導体装置1Aは、エミッタ領域11の表面におけるエミッタ領域接触幅Weを狭くすることなく、エミッタ注入幅Winjを狭くしてエミッタ領域11直下の総チャネル長を短く(チャネル密度を低く)することができる。
また、エミッタ注入幅Winjを広くすることなく、エミッタ領域接触幅Weを広くする。これにより、トレンチ構造のIGBTのラッチアップ耐量の向上及び低オン電圧化を図ることができる。
図5に示すように、n+型のエミッタ領域11及びp+型のコンタクト領域12をY方向(トレンチ4又はメサ領域5の長手方向)に沿って交互に配置する構造では、エミッタ領域11直下のp型のベース領域9がチャネルの実質的な形成領域となる。そのため、エミッタ領域接触幅We及びエミッタ注入幅Winjが同じ長さのエミッタ領域11を周期的に形成すると、エミッタ領域11をY方向に沿ってストライプ状に連続的に形成する従来構造と比較してチャネル密度が低くなる傾向が生じる。そしてチャネル密度の低下に伴ってオン電圧が高くなることがある。
すなわち、エミッタ領域11は図2に示したように隣り合うトレンチ4を繋ぐようにして設けられているので、正孔は図5のY方向に進んでp+型のコンタクト領域12に流れなければならない。
このため、エミッタ・ベース間pn接合界面11n1の長さであるエミッタ注入幅Winjの長さ分だけ電圧降下が増加し、ラッチアップし易くなる。したがって、エミッタ領域11及びコンタクト領域12をY方向に沿って交互に配置する構造では、どうしてもエミッタ・ベース間pn接合界面11n1の長さであるエミッタ注入幅Winjを所定の長さ(数μm)を超えて広くすることは難しい。
このエミッタ領域11の底面の直下でコンタクト領域12が挟み込む間隔(エミッタ注入幅Winj)の長さが、例えば0.1μm~2.0μmで、より好ましくは0.1μm~2.0μmであってもよい。
ラッチアップは、正孔の通る箇所の抵抗成分だけでなく、正孔の電流密度でも決まる。そのため、コンタクト領域12自体のY方向の長さを相対的に短くしてエミッタ領域11の割合(個数)を増やすだけでは、チャネル密度は増やせても、やはりラッチアップし易くなる。
このような構成とすることにより、コンタクト領域接触幅Wbcよりも実効コンタクト領域幅Weffを広くすることができる。このため、チャネル中の電子に引き寄せられて流れてくる正孔がポテンシャルに沿ってp+型のコンタクト領域12にも流れる割合を高くすることができる。
その結果、n+型のエミッタ領域11直下の正孔電流密度は小さくなる。これにより、コンタクト領域12の表面におけるコンタクト領域接触幅Wbcを相対的に狭くし、エミッタ領域接触幅Weの割合を増やしてチャネル密度を増やしても、エミッタ領域11のラッチアップ耐量を高めることができる。さらに、チャネル密度を増やすことができるので、オン電圧を低くすることができる。
また、コンタクト領域12がエミッタ領域11よりも深く、かつエミッタ領域11の底面直下に廻りこむように形成されているので、正孔電流Iholeをコンタクト領域12側に分散することができる。これにより、エミッタ領域11直下に溜まった正孔をコンタクト領域12を介してエミッタ電極20に素早く引き抜くことができる。
なお、ラッチアップ耐量は、コンタクト領域12をエミッタ領域11よりも深くして飽和電流値を低くすることで高めることができるが、深すぎると低下する。したがって、コンタクト領域の深さdbcはエミッタ領域11の深さdeから0.5μm以上、2μm以下が好ましい。
そのため、エミッタ領域11及びコンタクト領域12とエミッタ電極20とのコンタクト抵抗を低くすることができる。この結果、微細化に伴ってコンタクト孔16の幅が縮小されても、IGBTの低オン電圧化を図ることができる。
次に、第1の実施形態に係る半導体装置の製造方法について、図8乃至図28を用いて説明する。以下の説明では、エミッタ領域11を形成するための不純物イオンとコンタクト領域12を形成するための不純物イオンとをベース領域9の表層部に注入した後、これらの不純物イオンを活性化させる熱処理を一括して施す場合について説明する。しかし本発明は、このような手順に限定されるものではない。
トレンチ4は、フォトリソグラフィ技術を用いて半導体基板3SUBの主面を例えばRIEなどのドライエッチングで選択的にエッチングすることにより形成される。この結果、メサ領域5は、X方向(トレンチ4又はメサ領域5の幅方向)に沿って複数配置される。
次に、図9に示すように、半導体基板3SUBの主面にトレンチ4の内部を埋め尽くすように、ゲート材7として例えば低比抵抗のドープドポリシリコン膜を形成する。ゲート材7は、例えば1μmのトレンチ幅に対して、1μm程度の膜厚で形成する。
また、この工程において、ゲート絶縁膜6に対して選択性を有するエッチングレートでゲート材7をエッチバックすることでメサ領域5上のゲート絶縁膜6はエッチングストッパとして機能し、メサ領域5の上部表面のエッチングを防止することができる。
このベース領域9は、トレンチ4よりも浅く形成する。例えば、ベース領域9は、トレンチ4の深さ5~10μmに対して、2~8μm程度の深さで形成する。なお、この第1の実施形態では、トレンチ4の内部にゲート電極8を形成した後にベース領域9を形成しているが、ベース領域9は、半導体基板3SUBの主面にトレンチ4を形成する前に、半導体基板3SUBの主面の表層部全面に形成してもよい。この場合、トレンチ4は、ベース領域9を突き抜けるようにして半導体基板3SUBの主面に形成される。
第1マスクRM1は、半導体基板3SUBの主面上の全面に感光性レジスト膜を形成し、その後、この感光性レジスト膜に感光及び現像処理などを施して所定のパターンに加工することによって形成される。第1マスクRM1は、互いに隣り合うメサ領域5の間のトレンチ4を横切るようにしてX方向に連続的に延在するストライプ状の平行パターンで形成される。第1マスクRM1は、例えば4μm程度の幅a1で形成し、Y方向に沿って2μm程度の間隔b1、6μm程度の配列ピッチで配列する。
具体的には、まず、図15乃至図17に示すように、第2マスクRM2を第1マスクRM1と同一の配列ピッチMP2で形成する。この第2マスクRM2は、第1不純物イオン注入領域12A上に、隣り合う第1マスクRM1の間の間隔b1よりも同一方向の間隔b2が広く、第1マスクRM1の幅a1よりも同一方向の幅a2が狭い。
また、第2マスクRM2は、上述の第1マスクRM1と同様に、互いに隣り合うメサ領域5の間のトレンチ4を横切るようにしてX方向に連続的に延在するストライプ状の平行パターンで形成される。第2マスクRM2は、例えば3μm程度の幅a2で形成し、Y方向に沿って3μm程度の間隔b2、第1マスクRM1と同様の配列ピッチで配列する。
ここで、図16は、図15のIVa-IVa線に沿った断面構造を示す要部断面図である。図17は、図15のIVb-IVb線に沿った断面構造を示す要部断面図である。砒素イオン(75As+)の注入は、例えばドーズ量が1×1015/cm2~1×1016/cm2程度、加速エネルギが120keV程度の条件で行う。
また、互いに隣り合う第1マスクRM1の間の間隔b1よりも第2マスクRM2のY方向の幅a2の方が広い。一方、第1マスクRM1のY方向の幅a1よりも互いに隣り合う第2マスクRM2の間の間隔b2の方が狭い。そのため、図17に示すように、第1不純物イオン注入領域12Aの一部に第2不純物イオン注入領域11Aの一部が畳重する。
具体的には、注入されたボロンイオン(11B+)及びヒ素イオン(75As+)を活性化させる熱処理を一括して施す。これにより、図18乃至図20に示すように、第2不純物イオンとしてヒ素イオン(75As+)が添加されたn+型のエミッタ領域11と、第1不純物イオンとしてボロンイオン(11B+)が添加されたp+型のコンタクト領域12が形成される。
この工程において、砒素イオン(75As+)はボロンイオン(11B+)のドーズ量よりも高いドーズ量で注入されている。そのため、図20に示すように、ボロンイオン(11B+)が注入された領域の一部と砒素イオン(75As+)が注入された領域の一部とが重複する領域はn+型のエミッタ領域11となる。
また、第2不純物イオン注入領域11Aは、複数の第1不純物イオン注入領域12Aの間のベース領域9の表層部にY方向に沿って注入される。このため、図20に示すように、エミッタ領域11を挟んで互いに隣り合うコンタクト領域12が、エミッタ領域11よりも深く形成され、かつエミッタ領域11直下に廻り込んで互いに離間する構造とすることができる。
そのため、コンタクト領域12を形成するための第1マスクRM1とエミッタ領域11を形成するための第2マスクRM2との合わせズレに起因する、エミッタ注入幅Winjのバラツキを抑制することができる。また、図5に示すように、コレクタ領域接触幅Wbcがエミッタ領域接触幅Weよりも狭く、実効コンタクト領域幅Weffが、エミッタ注入幅Winjよりも広い構造とすることができる。
なお、配置によっては、第1不純物イオン注入領域12Aの一部に第2不純物イオン注入領域11Aの一部が、最大0.3μm程度は畳重しなくてもよい。前述の熱処理による拡散で、図4に示すように、エミッタ領域11の両側に接するコンタクト領域12が、エミッタ領域11よりも深く、かつエミッタ領域11の底面の直下に廻りこんでエミッタ領域11を挟みこむ構造が達成できる。
このコンタクト孔16は、図1に点線で示すように、メサ領域5上にY方向(トレンチ4又メサ領域5の長手方向)に沿ってストライプ状の平行平面パターンで形成される。またコンタクト孔16は、メサ領域5の表層部に設けられたエミッタ領域11及びコンタクト領域12に亘って形成される。
次に、図22に示すように、例えばPVD法でコンタクト孔16の内壁、メサ領域5の表面及び層間絶縁膜15の表面に沿ってバリアメタル膜17を形成する。バリアメタル膜17は、下側からチタン(Ti)膜/チタンナイトライド(TiN)膜を含む複合膜で形成される。チタン膜は例えば40nm程度の膜厚で形成する。チタンナイトライド膜は例えば100nm程度の膜厚で形成する。
そのため、メサ領域5のX方向の幅が微細化により縮小されてコンタクト孔16のアスペクト比が高くなっても、このコンタクト孔16の内部にタングステン膜を良好なステップカバレージで埋め尽くすことができる。また、コンタクト孔16のX方向の幅と深さとのアスペクト比(幅/深さ)が、0.8~1.5程度であってもよい。
さらに、コンタクト孔16の内部に選択的に残存するバリアメタル膜17を形成する。この工程において、コンタクト孔16の内部にバリアメタル膜17を介してコンタクトプラグ19が選択的に埋め込まれ、層間絶縁膜15の表面側は略平坦になる。
また、この工程においては、図4に示したように、コンタクトプラグ19は、バリアメタル膜17を介してベース領域9の表層部に設けられたn+型のエミッタ領域11及びp+型のコンタクト領域12と電気的に接続されることになる。
また、図24に示すように、コンタクト孔16の内部に残存するバリアメタル膜17の上縁部17dは、コンタクト孔16の上縁部16dよりも一段低くなる。また、コンタクトプラグ19の表面19aは、中央部が窪む凹面形状で形成される。
その後、この金属膜をエッチングによりパターンニングして、図25に示すように、層間絶縁膜15上にコンタクト孔16内のバリアメタル膜17及びコンタクトプラグ19と接触して電気的に接続されるエミッタ電極20を形成する。
この工程において、エミッタ電極20は、図4に示したように、p型のベース領域9の表層部に設けられたn+型のエミッタ領域11及びp+型のコンタクト領域12とコンタクトプラグ19及びバリアメタル膜17を介して電気的に接続されることになる。エミッタ電極20と接触するコンタクトプラグ19の表面19aは中央部が窪む凹面形状になっている。
そのため、コンタクトプラグ19の表面が平坦な場合と比較して、エミッタ電極20とコンタクトプラグ19との接触面積が増加し、エミッタ領域11及びコンタクト領域12とエミッタ電極20との間のコンタクト抵抗を低くすることができる。
次に、図28のバッファ層及びコレクタ領域形成工程S12により、図26に示すように、半導体基板3SUBの裏面の表層部にn型のバッファ層21及びp+型のコレクタ領域22を形成する。
バッファ層21及びコレクタ領域22の形成方法としては、まず、半導体基板3SUBの裏面に、n型を呈する不純物イオンとして例えばリンイオン(31P+)を注入すると共に、p型を呈する不純物イオンとして例えばボロンイオン(11B+)を注入する。その後、注入された不純物イオンを活性化させる熱処理を施すことによってバッファ層21及びコレクタ領域22が形成される。
バッファ層21は、半導体基板3SUBの裏面から深さ方向にコレクタ領域22よりも深い位置に形成され、残余の半導体基板3SUBがドリフト層3となる。n型のバッファ層21を形成するための不純物イオンは、加速エネルギがp型のコレクタ領域22を形成するための不純物イオンよりも高い条件で注入される。この工程により、トレンチ構造のIGBTを構成するトランジスタセル2が複数個並列に形成される。
この工程において、水素(H2)は、チタン膜を含むバリアメタル膜17を通過することができない。しかし、図27に示すように、バリアメタル膜17はコンタクト孔16の内部に選択的に形成され、層間絶縁膜15の表面には設けられていない。そのため、水素は、半導体基板3SUBの主面側の上方から保護膜23、エミッタ電極20、層間絶縁膜15などを通過する。
よって半導体基板3SUBの主面に水素を容易に供給することができ、水素アニールによる効果、すなわち荷電粒子の照射により生成された欠陥の回復やIGBTの閾値変動の回復を十分に行うことができる。最後に、図28のコレクタ電極形成工程S16により、コレクタ領域22にコレクタ電極24を形成する。これにより、図1乃至図7に示した本発明の第1の実施形態に係る半導体装置1Aのウエハプロセスがほぼ完成する。
このため、少数キャリアのライフタイムを低減させる必要が特段無い場合は、前述のライフタイム制御工程S14及び水素アニール工程S15については、行わなくてもよい。
また、第1マスクRM1の配列ピッチMP1と同一の配列ピッチMP2で配置された第2マスクRM2を用いて、第1不純物イオン注入領域12Aの間のベース領域9の表層部に、砒素イオン(75As+)が注入される。砒素イオン(75As+)の注入は、第1不純物イオンよりも射影飛程が浅くなるような加速エネルギを選択して行われる。
また、図12及び図14に示す第1マスクRM1とエミッタ領域11を形成するための図15及び図17に示す第2マスクRM2との合わせズレに起因する、エミッタ注入幅Winjのバラツキを抑制することができる。また、図5に示すように、コレクタ領域接触幅Wbcがエミッタ領域接触幅Weよりも狭く、実効コンタクト領域幅Weffが、エミッタ注入幅Winjよりも広い構造とすることができる。
この場合、水素は、前段のライフタイム制御工程での荷電粒子の照射により生成された欠陥の回復やIGBTの閾値変動の回復を行う際に、チタン膜を通過できない。そしてチタン膜を含むバリアメタル膜17はコンタクト孔16の内部に選択的に形成され、層間絶縁膜15の表面には設けられていない。
このため、半導体基板3SUBの主面側の上方から保護膜23、エミッタ電極20、層間絶縁膜15などを通過して半導体基板3SUBの主面に水素を容易に供給することができる。これにより、水素アニールによる効果、すなわち荷電粒子の照射により生成された欠陥の回復やIGBTの閾値変動の回復を十分に行うことができる。
また、バリアメタル膜17を用いることができるので、コンタクトプラグ19中の原子の拡散に起因するコンタクト抵抗の増加を抑制することができる。この結果、IGBTのスイッチング速度を速くすることができる。
また、本発明の第1の実施形態に係る半導体装置1Aの製造方法では、プラグ材18のエッチバックにより層間絶縁膜15上のバリアメタル膜17を除去する。また、コンタクト孔16の内部に選択的に残存するバリアメタル膜17を形成する。そのため、コンタクト孔16の内部のバリアメタル膜17はコンタクト孔16に対して自己整合で形成される。
したがって、コンタクト孔16の位置に対してバリアメタル膜17のパターンニングの位置ずれを考慮する必要がないので、微細なトランジスタセル2で構成されるIGBTの製造を容易に行うことができる。
例えば、それぞれの熱処理を別工程で行ってもよい。この場合、エミッタ領域11及びコンタクト領域12の何れを先に形成してもよい。しかし、p型を呈する不純物イオンであるボロンイオン(11B+)や二フッ化ボロンイオン(49BF2 +)は、n型を呈する不純物イオンであるヒ素イオン(75As+)やリンイオン(31P+)と比較して拡散係数が大きい。
そのため、p型の不純物イオンであるボロンイオン(11B+)や二フッ化ボロンイオン(49BF2 +)を先に注入し、この不純物イオンを活性化させる熱処理の方を先に実施することが好ましい。
上述した第1の実施形態では、単体のIGBTを有する個別デバイスである半導体装置1Aについて説明した。これに対し、第2の実施形態では、トレンチ構造のIGBTとダイオードを集積化した半導体装置1Bについて説明する。
本発明の第2の実施形態に係る半導体装置1Bは、図29乃至図31に示すように、例えば単結晶シリコンからなるn-型の半導体基板の一部をドリフト層3として構成している。そして、第2の実施形態に係る半導体装置1Bは、半導体基板にトレンチ構造のIGBT及びダイオードを逆並列で接続した逆導通IGBT(Reverse Conducting IGBT,RC-IGBT)である。
トランジスタ用メサ領域5a及びダイオード用メサ領域5bは、例えばX方向に沿って交互にそれぞれ複数個周期的に配置されている。フローティング用メサ領域5cは、例えばトランジスタ用メサ領域5aとダイオード用メサ領域5bとの間に配置され、集積化構造を実現している。トレンチ4、トランジスタ用メサ領域5a、ダイオード用メサ領域5b及びフローティング用メサ領域5cの各々は、Y方向に沿ってストライプ状に平行に延伸する平面パターンを構成している。
図29乃至図31は、トランジスタセル2a、ダイオードセル2b、トランジスタ用メサ領域5a、ダイオード用メサ領域5b及びフローティング用メサ領域5cがそれぞれ1つ配列された部分を第2の実施形態に係る半導体装置1Bの一部として例示する。
しかし、本発明はこれに限定されるものではない。
複数のトレンチ4のそれぞれの内壁に沿ってゲート絶縁膜6が設けられ、このゲート絶縁膜6を介してゲート電極8がトレンチ4の内部のそれぞれに設けられている。
また、トランジスタセル2aは、エミッタ領域11のそれぞれを挟むようにY方向に沿って交互に複数個配置され、エミッタ領域11よりも深く形成され、かつエミッタ領域11の直下に廻り込んで互いに離間したp+型のコンタクト領域12を備えている。
また、トランジスタセル2aは、半導体基板からなる共通のドリフト層3と、ドリフト層3の裏面に設けられたn型のバッファ層21及び第2導電型で高不純物濃度のコレクタ領域22とを共通領域として備えている。
フローティング用メサ領域5cに対向する他方の主面側(裏面)には、トランジスタセル2aに対向する裏面のコレクタ領域22が延在している。
アノード領域29はトレンチ4よりも浅く形成されており、例えばベース領域9と同一工程で形成されている。カソード領域22bは、n+型のコレクタ領域22と共に、ドリフト層3の裏面から深さ方向に向かってバッファ層21よりも浅い位置に配置され、かつドリフト層3の裏面に設けられたコレクタ電極24と電気的にかつ金属学的に接続されている。カソード領域22bは、バッファ層21よりも高不純物濃度で形成されている。
そして層間絶縁膜15には、層間絶縁膜15の表面からトランジスタ用メサ領域5aに到達するように層間絶縁膜15を貫通するコンタクト孔16aが設けられている。また層間絶縁膜15には、層間絶縁膜15の表面からダイオード用メサ領域5bに到達するように層間絶縁膜15を貫通するコンタクト孔16bが設けられている。
コンタクト孔16aは図29に点線で示すように、トランジスタ用メサ領域5a上をY方向(トレンチ4又はトランジスタ用メサ領域5aの長手方向)に沿って延伸し、エミッタ領域11及びコンタクト領域12の配列位置に対応するように設けられている。
コンタクト孔16bは、図29に点線で示すように、ダイオード用メサ領域5b上をY方向(トレンチ4又はダイオード用メサ領域5bの長手方向)に沿って延伸し、アノード領域29と対向するようにして設けられている。コンタクト孔16a及び16bは、前述の第1の実施形態のコンタクト孔16と同様に、例えば幅0.5μmのストライプ状の平行平面パターンで構成されている。
また、コンタクト孔16aの内部には、バリアメタル膜17を介してコンタクトプラグ19が埋設されている。コンタクト孔16bの内部にも、第1の実施形態のコンタクト孔16と同様に、コンタクト孔16aの内壁とコンタクト孔16bの底部に露出したアノード領域29の表面に沿って選択的に形成されたバリアメタル膜17が設けられている。
また、コンタクト孔16bの内部にも、バリアメタル膜17を介してコンタクトプラグ19が埋設されている。バリアメタル膜17は、層間絶縁膜15の表面上には設けられておらず、コンタクト孔16a及び16bの各々の内部に選択的に設けられている。
また、このエミッタ電極20は、コンタクト孔16bの内部に設けられたコンタクトプラグ19及びバリアメタル膜17を介してアノード領域29と電気的に接続されている。エミッタ電極20上には、このエミッタ電極20を覆うようにして保護膜23が設けられている。
第2の実施形態に係るn+型のエミッタ領域11及びp+型のコンタクト領域12は、前述の第1の実施形態に係るn+型のエミッタ領域11及びp+型のコンタクト領域12と同様の構成になっている。すなわち、図5を参照すれば、n+型のエミッタ領域11を挟んで互いに隣り合うp+型のコンタクト領域12は、エミッタ領域11よりも深く形成されている。そして、コンタクト領域12は、エミッタ領域11の直下に廻り込んで互いに離間している。
また、図6を参照すれば、エミッタ・ベース間pn接合界面11n1のY方向に測ったエミッタ注入幅Winjの半分の長さAは、エミッタ・コンタクト間pn接合界面11n2のY方向に沿う断面図上での曲面に沿った沿面距離dcrpよりも短くなっている。
したがって、このように構成された第2の実施形態に係る半導体装置1Bにおいても、上述した第1の実施形態に係る半導体装置1Aと同様の効果を得ることができる。
<第3の実施形態に係る半導体装置の構造>
本発明の第3の実施形態に係る半導体装置1Cは、図32乃至図34に示すように、上述した本発明の第1の実施形態に係る半導体装置1Aとほぼ同様の構成になっているが、ゲート絶縁膜36の構成が異なっている。第3の実施形態に係る半導体装置1Cは、第1の実施形態のゲート絶縁膜6に代えて膜厚が異なるゲート絶縁膜36を備えている。
また、第3の実施形態に係る半導体装置1Cは、メサ領域5の表層部に設けられたp型のベース領域9と、このベース領域9の表層部に、Y方向に沿って周期的に複数個配置されたn+型のエミッタ領域11とを備える。
また、第3の実施形態に係る半導体装置1Cは、このエミッタ領域11のそれぞれを挟むようにY方向に沿って交互に複数個配置され、エミッタ領域11よりも深く形成され、かつエミッタ領域11の直下に廻り込んで互いに離間したp+型のコンタクト領域12を備えている。
第3の実施形態に係る半導体装置1Cは、コンタクト孔16の内部に設けられ、コンタクト孔16の内壁とコンタクト孔16の底部に露出したエミッタ領域11及びコンタクト領域12の表面に沿って選択的に設けられたバリアメタル膜17を備えている。
また、第3の実施形態に係る半導体装置1Cは、コンタクト孔16の内部にバリアメタル膜17を介して設けられたコンタクトプラグ19と、層間絶縁膜15上にコンタクトプラグ19と接続して設けられたエミッタ電極20とを備えている。
換言すれば、ゲート絶縁膜36は、少なくともエミッタ領域11直下のベース領域9を挟む位置のトレンチ4の側壁に設けられた第1の部分36aを有している。また、ゲート絶縁膜36は、第1の部分36aよりも厚い膜厚で形成され、かつ、少なくともコンタクト領域12直下のベース領域9を挟む位置のトレンチ4の側壁に設けられた第2の部分36bを有している。
また、ゲート絶縁膜36は、第1の部分36aよりも厚い膜厚で形成され、かつ、少なくともトレンチ4の底部(ドリフト層3とゲート電極8との間)に設けられた第3の部分36c(図33及び図34参照)を有している。第1の部分36a、第2の部分36b及び第3の部分36cは、それぞれ連続して一体に形成されている。
また、第1の部分36aは、図33に示すように、エミッタ領域11直下のベース領域9とゲート電極8との間からエミッタ領域11とゲート電極8との間に亘って設けられ、一部がエミッタ領域11側に食み出てメサ領域5の上部表面で終端している。
また、第1の部分36aは、エミッタ領域11直下のベース領域9とゲート電極8との間からトレンチ4の底部とゲート電極8との間(ドリフト層3とゲート電極8との間)に亘って設けられている。第1の部分36aは、一部がトレンチ4の底部側(ドリフト層3側)に食み出て第3の部分36cと繋がっている。
また、第2の部分36bも、コンタクト領域12直下のベース領域9とゲート電極8との間からトレンチ4の底部とゲート電極8との間(ドリフト層3とゲート電極8との間)に亘って設けられている。第2の部分36bは、一部がトレンチ4の底部側(ドリフト層3側)に食み出て第3の部分36cと繋がっている。
第1の部分36aは、例えば100nm程度の膜厚で形成されている。第2の部分36bは、例えば150nm程度の膜厚で形成されている。第3の部分36cは、例えば200nm程度の膜厚で形成されている。
一方、コンタクト領域12直下のベース領域9とゲート電極8との間の第2の部分36bや、トレンチ4の底部に設けられた第3の部分36cは実質的にチャネルの電荷を誘起するゲート膜として機能しない。第3の実施形態に係る半導体装置1Cでは、この第2の部分36b及び第3の部分36cの膜厚が第1の部分36aよりも厚くなっている。
これにより、第1の部分36aの膜厚に合わせて第2の部分36b及び第3の部分36cも同一の膜厚で均一に形成する従来の場合と比較して、ゲート-エミッタ間容量、及びゲート-コレクタ間容量を低減することができる。その結果、トレンチ構造のIGBTのスイッチング時間、スイッチング損失を改善することができる。また、トレンチ構造のIGBTのスイッチング速度の高速化を図ることができる。
次に、第3の実施形態に係る半導体装置1Cの製造方法について、図35乃至図44を用いて説明する。第3の実施形態に係る半導体装置1Cでは、ゲート絶縁膜36の形成工程以外は上述した第1の実施形態に係る半導体装置1Aの製造方法とほぼ同一なので、ゲート絶縁膜36の形成工程に特化して説明し、その他の工程については詳細な説明を省略する。
(b1)次に、図35に示すように、半導体基板3SUBの主面にトレンチ4の内部を埋め尽くすように、例えばCVD法によりSiO2膜からなる堆積膜31を形成する。堆積膜31は、例えば1μmのトレンチ幅に対して、1μm程度の膜厚で形成する。
(c1)次に、堆積膜31をRIEなどのドライエッチングでエッチバックする。このエッチングによって、図36に示すように、半導体基板3SUBの主面上、すなわちトレンチ4上及びメサ領域5上の堆積膜31を選択的に除去して、トレンチ4の内部に埋設された堆積膜31を形成する。
第3マスクRM3は、図37及び図38に示すような第1の部分m3aと、図37及び図39に示すような第2の部分m3bとがY方向に沿って交互に繰り返し配置されたストライプ状平行平面パターンで形成される。
第1の部分m3aは、X方向の幅xaがメサ領域5のX方向の幅5xとほぼ同等であり、第2の部分m3bは、X方向の幅xbがメサ領域5のX方向の幅5xよりも広い。
この第2の部分m3bの側面の位置とメサ領域5の側面の位置との寸法差がゲート絶縁膜36の第2の部分36bの膜厚に相当する。第1の部分m3aの幅xaは例えば0.5μm程度、第2の部分m3bの幅xbは例えば0.7μm程度になっている。
第3マスクRM3は、上述した第1の実施形態での第1マスクRM1や第2マスクRM2と同様に、半導体基板3SUBの主面上の全面に形成された感光性レジスト膜を所定のパターンに加工することによって形成される。
また、図41に示すように、第3マスクRM3の第2の部分m3b直下のメサ領域5の側壁に例えば150nm程度の膜厚で残存する堆積膜31bを形成する。堆積膜31cは、トレンチ4及びメサ領域5の長手方向(Y方向)に沿ってストライプ状で形成される。堆積膜31bは、メサ領域5の上部から下部に向かって伸びており、堆積膜31cと一体的に繋がっている。堆積膜31bは、図40に示すように、第3マスクRM3の第1の部分m3aの直下のメサ領域5の側壁には形成されていない。
すなわち、メサ領域5の側壁にメサ領域5の長手方向(Y方向)に沿って周期的にメサ領域5の側壁が露出するパターンとなるように堆積膜31cを形成する。
すなわち、メサ領域5の長手方向(Y方向)において隣り合う堆積膜31bの間のメサ領域5の側壁の露出した箇所に堆積膜31b及び堆積膜31cよりも膜厚が薄い熱酸化膜32を形成する。この工程において、図42及び図43に示すように、メサ領域5の上部表面にも熱酸化膜32が形成される。
また、この工程において、熱酸化膜32からなる第1の部分36aと、堆積膜31bからなる第2の部分36bと、堆積膜31cからなる第3の部分36cとを有するゲート絶縁膜36が形成される。
この工程において、メサ領域5の上部表面に熱酸化膜32が形成されている。そのため、上述した第1の実施形態と同様に、熱酸化膜32に対して選択性を有するエッチングレートでゲート材7をエッチバックすることでメサ領域5上の熱酸化膜はエッチングストッパとして機能し、メサ領域5の上部表面のエッチングを防止できる。
また第1の実施形態と同様の工程を施して、エミッタ電極20、n型のバッファ層21、p+型のコレクタ領域22、保護膜23、コレクタ電極24などを形成する。
また併せて、ライフタイム制御工程(S14)及び水素アニール工程(S15)を施すことにより、本発明の第3の実施形態に係る半導体装置3Cのウエハプロセスがほぼ完了する。
なお、第3の実施形態に係る半導体装置1Cでは、ゲート絶縁膜36の第1の部分36aが、エミッタ領域11直下のベース領域9とゲート電極8との間からコンタクト領域12直下のベース領域9とゲート電極8との間に亘って設けられていた。そして、図32及び図33に示すように、ゲート絶縁膜36の第1の部分36aの一部がコンタクト領域12直下のベース領域9側に食み出て第2の部分36bと繋がっている場合について説明した。しかしながら、本発明は、これに限定されるものではない。
この場合、図37に示す第3マスクRM3において、第2の部分m3bのY方向の幅を広くし、第1の部分3maのY方向の幅を狭くすることで、容易にゲート絶縁膜36の第2の部分36bのY方向の幅を広くすることができる。また、第1の部分36aのY方向の幅を狭くすることができる。
第4の実施形態に係る半導体装置1Dは、図46に示すように、エミッタ領域の直下に設けられた低抵抗化層41及び、この低抵抗化層41に接する領域に対応する部分の厚みが、他の部分よりも薄いゲート絶縁膜46を備えることを特徴とする。
第4の実施形態に係る半導体装置1Dの低抵抗化層41は、隣り合うコンタクト領域12の間を架け渡すように、ベース領域9の上部に、ベース領域9より高濃度(p++)で設けられている。図46は、図1のIIc-IIc線に対応する位置での要部断面図である。
具体的には、低抵抗化層41と同じ高さに位置するゲート絶縁膜46の領域の厚みを、低抵抗化層41の上側のエミッタ領域11、低抵抗化層41の下側のベース領域9及びベース領域9の下側のドリフト層3と接する領域のゲート絶縁膜46より薄くする。
ゲート絶縁膜46の低抵抗化層41と同じ高さに位置する部分の厚みは、図48に示すように、ゲート電極48との界面側が低抵抗化層41側に引っ込む凹部を設けることで薄肉化されている。薄肉化された領域の厚みtは、ゲート電圧印加時にトレンチ4の側壁側の低抵抗化層41の表面の表面ポテンシャルが変化し、所望の反転層が形成されるように考慮して設定されている。
第4の実施形態に係る半導体装置1Dによれば、高濃度の低抵抗化層41がエミッタ領域11の下側に設けられていることにより、エミッタ領域11の下側の領域の抵抗が低下し、pn接合が導通し難くなる。そしてターンオフ動作時に正孔電流が流れた際の低抵抗化層41の領域における電位上昇を抑制して、第4の実施形態に係る半導体装置1Dをラッチアップし難くすることができる。
またエミッタ領域接触幅Weを大きくして、チャネル密度を上げることが可能になり、オン電圧を低減することができる。
ゲート絶縁膜46の厚みをトレンチ4の側壁に沿って一様とすれば、エミッタ領域11の下に低抵抗化層41の表面に反転層が形成され難くなり、ゲート閾値電圧が上昇し、半導体装置がターンオンし難くなる。
そのため、低抵抗化層41に接する位置のゲート絶縁膜46の厚みを端部の領域より相対的に薄くすることにより、低抵抗化層41の表面ポテンシャルの制御を容易にして、ゲート閾値電圧の上昇を抑制することができる。このように低抵抗化層41の設置及びゲート絶縁膜46の膜厚の制御を組み合わせて構成することにより、ラッチアップし難く、ゲート閾値電圧の上昇を抑制した、第4の実施の形態に係る半導体装置を提供することができる。
この方法の場合、ゲート電極に逆バイアスを印加した時に、ドリフト層3のゲートに近接する部分の導電型が反転し、高耐圧化を図ることができるというメリットがある。しかしベース領域9の濃度が薄く抵抗が高いとpn接合が導通し易くなり、ラッチアップして半導体装置が破壊し易くなるという問題がある。
この点、第4の実施形態に係る半導体装置によれば、ドリフト層3の上部ではなく、エミッタ領域11とベース領域9の間におけるゲート絶縁膜46の厚みを、他の部分よりも薄く構成するのでラッチアップし難くなる。第4の実施形態に係る半導体装置1Dの他の効果については、第1の実施形態に係る半導体装置の場合と同様である。
次に、第4の実施形態に係る半導体装置1Dの製造方法について、図49乃至図59を用いて説明する。図49乃至図59は、図1のIIa-IIa線に対応する位置での要部断面図である。
第4の実施形態に係る半導体装置1Dでは、低抵抗化層41、ゲート絶縁膜46及びゲート電極48のそれぞれの形成工程以外は上述した第1の実施形態に係る半導体装置1Aの製造方法とほぼ同一である。そのため、低抵抗化層41、ゲート絶縁膜46及びゲート電極48のそれぞれの形成工程に特化して説明し、その他の工程については詳細な説明を省略する。
(b2)次に、上述した第1の実施形態と同様の工程を施して、図50に示すように、絶縁膜45をエッチングマスクとして、半導体基板3SUBの主面にトレンチ4を形成すると共に、X方向において互いに隣り合うトレンチ4で挟まれて区画されたメサ領域5を形成する。
図51では、絶縁膜45の側壁部に新たに出来る熱酸化膜の厚さとトレンチ4の側壁に出来る熱酸化膜の厚さを同じ厚さで表現しているが、これは模式的表現である。実際には絶縁膜45の側壁部に成長する熱酸化膜の厚さは、トレンチ4の側壁に成長する熱酸化膜の厚さより薄い。
その後、図52に示すように、ドープドポリシリコン膜をRIE等でエッチバックしてドープドポリシリコン膜の上面が、後述する工程で形成される予定の低抵抗化層41の下面の位置となるように、エッチバックの量を調整する。エッチバックにより残ったドープドポリシリコン膜が第1のゲート電極48aとなる。
(f2)次に、図54に示すように、トレンチ4の内側に、例えばSiO2膜からなる第2のゲート絶縁膜46bを、例えば熱酸化法等により一定の膜厚で形成する。第2のゲート絶縁膜46bは、絶縁膜45の上面及び側面、トレンチ4の上部の内壁面、第1のゲート絶縁膜46aの上端面並びに第1のゲート電極48aの上面に亘って形成される。図54中に例示された第2のゲート絶縁膜46bは、第1のゲート絶縁膜46aに比して薄く形成されている。
すなわち、第1のゲート電極48aの上面が露出し、第2のゲート絶縁膜46bの下端が、第1のゲート絶縁膜46aの上端から連続するように指向性エッチングを施す。指向性エッチングであるので、エッチング後の第2のゲート絶縁膜46bは当初設定された厚みtが維持でき、高濃度の低抵抗化層41中に反転層が形成し易い第2のゲート絶縁膜46bの厚さが維持できる。
その後、ゲート材の上部をエッチバックして第2のゲート電極48bを形成し、図56に示すように、第2のゲート電極48bの厚みが、所定の寸法となるように制御する。すなわちエッチバックにより第2のゲート電極48bの厚みは、上面が、後述する工程で形成される予定の低抵抗化層41の上面の位置に揃うように設定される。
第3のゲート絶縁膜46cは、図57中に例示したように第2のゲート絶縁膜46bの厚みtと併せて、第1のゲート絶縁膜46aの厚みと略等しくなるようにしても良いし、或いは更に厚くても構わない。
選択的に除去され残った部分の第3のゲート絶縁膜46cと、第1のゲート絶縁膜46aと第2のゲート絶縁膜46bとが一体で、図47に示したようなゲート絶縁膜46となる。
その後、ゲート材の上面が図59に示すレベルとなるようにエッチバックして、第3のゲート電極48cを形成する。エッチバックされ残った部分の第3のゲート電極48cと、第1のゲート電極48aと第2のゲート電極48bとが一体で、図47に示したようなゲート電極48となる。
次に、エミッタ領域11が形成されるように、n型を呈する第2不純物イオンを選択的に注入する。これらのイオン注入の際、第1不純物イオン及び第2不純物イオンの拡散定数及び射影距離をそれぞれ選択することにより、エミッタ領域11の下側に低抵抗化層41が形成される。
その後、図15~図27で説明したのと同様にそれぞれの工程を施す。このとき、低抵抗化層41は活性化後に、第2のゲート電極48b及び第2のゲート絶縁膜46bと同じ高さに揃って位置するように、活性化処理が施される。
以上の工程により、図46~図48に示したような第4の実施形態に係る半導体装置1Dを製造することができる。
第4の実施形態に係る半導体装置は、低抵抗化層41に接する位置のゲート絶縁膜56の厚みのみを選択的に薄くして、反転層の形成を容易化した。しかし低抵抗化層41における反転層の形成を容易化できる限り、図60に示した第4の実施形態の第1変形例に係る半導体装置1Eのように、エミッタ領域11に接する領域のゲート絶縁膜56の厚みも薄くしてもよい。
図60は、図1のIIa-IIa線に対応する位置での要部断面図である。図60中には、低抵抗化層41及びエミッタ領域11に接する領域が、ベース領域9に接する領域のゲート絶縁膜56の厚みよりも薄い厚みで、上下方向に一定の厚みで延びるように設けられた状態が例示されている。
具体的には、図57に示したような第3のゲート絶縁膜46cを成膜する必要が省ける。また図59に示したような、第3のゲート電極48cの製造工程を第2のゲート電極48bの製造工程と別に施すことなく、1回の製造工程で一体的に形成できる。よって、第4の実施形態に係る半導体装置の製造方法を簡素化し、生産性を高めることができる。
また、第4の実施形態に係る半導体装置は、ゲート電極48の上面の最も高い位置がエミッタ領域11の上面と同じ位置となるような深さでゲート電極48が形成されていた。しかしゲート電極の上面が低抵抗化層41の上面に揃う位置となるように、図47に示した場合より低くなるように形成してもよい。
第4の実施形態の第2変形例に係る半導体装置の製造方法としては、例えば図57において示した第3のゲート絶縁膜46cを、トレンチ4の内側を埋め戻す程度まで厚く形成する。その後、第3のゲート絶縁膜46cの内部に、第2のゲート電極48bに達するコンタクトホール(ビアホール)を形成すれば、第2のゲート電極48bがゲート電極の一番上の層として機能する。
その後、コンタクトホール(ビアホール)の中にビアプラグを埋めることにより、第2のゲート電極48bと表面配線との電気的な接続が可能になる。その他の工程については、上記した第4の実施形態に係る半導体装置1Dの製造方法の場合と同様である。
このようにゲート電極の上面をエミッタ領域11の下面より低くした第4の実施形態の第2変形例によれば、エミッタ・ゲート間の寄生容量を低減でき、低抵抗化層41における反転層の形成を容易化できる。
また、上記した第4の実施形態に係る半導体装置1Dの製造方法の説明では、トレンチ4を掘り込んだ後に、図60に示したようなエミッタ領域11や低抵抗化層41等の表面構造を形成した。しかしこれに限定されず、エミッタ領域11や低抵抗化層41等の表面構造を形成した後で、図50に示したようなトレンチ4を形成するように工程の順番を変更すれば、ゲート電極の材料の選択の自由度が向上する。
以上、本発明を上述した第1乃至第4の実施形態に基づき具体的に説明したが、本発d明は、上述の実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
2,2a…トランジスタセル
2b…ダイオードセル
3…n-型のドリフト層
3SUB…半導体基板
4…トレンチ
5…メサ領域
5a…トランジスタ用メサ領域
5b…ダイオード用メサ領域
5c…フローティング用メサ領域
6…ゲート絶縁膜
7…ゲート材(ポリシリコン膜)
8…ゲート電極
9…p型のベース領域
9a…フローティング領域
11…n+型のエミッタ領域
11n1…エミッタ・ベース間pn接合界面
11n2…エミッタ・コンタクト間pn接合界面
12…p+型のコンタクト領域
12p…コンタクト・ベース間界面
15…層間絶縁膜
16,16a,16b…コンタクト孔
17…バリアメタル膜
18…プラグ材
19…コンタクトプラグ
20…エミッタ電極
21…n型のバッファ層
22…p+型のコレクタ領域
23…保護膜
24…コレクタ電極
41…低抵抗化層
45…絶縁膜
46…ゲート絶縁膜
46a…第1のゲート絶縁膜
46b…第2のゲート絶縁膜
46c…第3のゲート絶縁膜
48…ゲート電極
48a…第1のゲート電極
48b…第2のゲート電極
48c…第3のゲート電極
56…ゲート絶縁膜
58…ゲート電極
dbc…コレクタ領域の深さ
de…エミッタ領域の深さ
Wbc…コンタクト領域接触幅
We…エミッタ領域接触幅
Weff…実効コンタクト領域幅
Winj…エミッタ注入幅
Claims (25)
- 第1導電型のドリフト層と、
前記ドリフト層上において、互いに隣り合うトレンチで挟まれたメサ領域と、
前記トレンチのそれぞれの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記メサ領域に設けられた第2導電型のベース領域と、
前記ベース領域の表層部に、前記トレンチの長手方向に沿って周期的に複数個配置された第1導電型のエミッタ領域と、
前記エミッタ領域のそれぞれを挟むように前記長手方向に沿って交互に配置され、前記エミッタ領域よりも深く形成され、かつ前記エミッタ領域の直下に廻り込んで互いに離間した第2導電型のコンタクト領域と、
を備えることを特徴とする半導体装置。 - 前記コンタクト領域の表面に定義される前記長手方向に測ったコンタクト領域接触幅は、前記エミッタ領域の表面に定義される前記長手方向に測ったエミッタ領域接触幅よりも狭いことを特徴とする請求項1に記載の半導体装置。
- 前記コンタクト領域の表面に定義される前記長手方向に測ったコンタクト領域接触幅は、前記エミッタ領域の表面に定義される前記長手方向に測ったエミッタ領域接触幅よりも広いことを特徴とする請求項1に記載の半導体装置。
- 前記コンタクト領域と前記ベース領域との界面の前記長手方向に測った実効コンタクト領域幅は、前記エミッタ領域と前記ベース領域とのpn接合界面の前記長手方向に測ったエミッタ注入幅よりも広いことを特徴とする請求項2又は請求項3に記載の半導体装置。
- 前記エミッタ注入幅の半分の長さは、前記エミッタ領域と前記コンタクト領域とのpn接合界面の沿面距離よりも短いことを特徴とする請求項4に記載の半導体装置。
- 前記エミッタ領域及び前記コンタクト領域は、隣り合う前記トレンチを繋ぐようにして設けられていることを特徴とする請求項5に記載の半導体装置。
- 前記エミッタ領域は前記コンタクト領域よりも高不純物濃度であることを特徴とする請求項6に記載の半導体装置。
- 前記エミッタ領域及び前記コンタクト領域を覆うようにして設けられた層間絶縁膜と、
前記層間絶縁膜を貫通するコンタクト孔の内壁と前記コンタクト孔の底部に露出した前記エミッタ領域及び前記コンタクト領域の各々の表面に設けられたバリアメタル膜と、
前記コンタクト孔の内部に前記バリアメタル膜を介して設けられたコンタクトプラグと、
前記層間絶縁膜上に前記コンタクトプラグと接続して設けられたエミッタ電極と、
を更に備えることを特徴とする請求項1に記載の半導体装置。 - 前記コンタクト孔は、前記長手方向に沿ってストライプ状に延伸していることを特徴とする請求項8に記載の半導体装置。
- 前記バリアメタル膜の上縁部は、前記コンタクト孔の上縁部よりも一段低くなっていることを特徴とする請求項8に記載の半導体装置。
- 前記コンタクトプラグの表面は凹形状になっていることを特徴とする請求項8に記載の半導体装置。
- 前記バリアメタル膜は、チタン膜及びチタンナイトライド膜を含む複合膜で形成され、
前記コンタクトプラグは、タングステン膜で形成されていることを特徴とする請求項8に記載の半導体装置。 - 前記ドリフト層上において、互いに隣り合う前記トレンチで挟まれたダイオード用メサ領域と、
前記ダイオード用メサ領域の表層部に設けられた第2導電型のアノード領域と、
前記ドリフト層の表層部とは反対側の裏面に、前記ダイオード用メサ領域と対向して設けられた第1導電型のカソード領域と、
を更に備えることを特徴とする請求項8乃至請求項12の何れか1項に記載の半導体装置。 - 前記ゲート絶縁膜は、少なくとも前記エミッタ領域直下の前記ベース領域を挟む位置の前記トレンチの側壁に設けられた第1の部分と、前記第1の部分よりも厚い膜厚で形成され、かつ少なくとも前記コンタクト領域直下の前記ベース領域を挟む位置の前記トレンチの側壁に設けられた第2の部分とを有することを特徴とする請求項1に記載の半導体装置。
- 前記第1の部分は、前記エミッタ領域直下の前記ベース領域と前記ゲート電極との間から、前記コンタクト領域直下の前記ベース領域と前記ゲート電極との間に亘って設けられていることを特徴とする請求項14に記載の半導体装置。
- 前記第2の部分は、前記コンタクト領域直下の前記ベース領域と前記ゲート電極との間から、前記エミッタ領域直下の前記ベース領域と前記ゲート電極との間に亘って設けられていることを特徴とする請求項14に記載の半導体装置。
- 前記第1の部分は、前記エミッタ領域直下の前記ベース領域と前記ゲート電極との間から、前記エミッタ領域と前記ゲート電極との間に亘って設けられていることを特徴とする請求項15又は請求項16に記載の半導体装置。
- 前記第2の部分は、前記コンタクト領域直下の前記ベース領域と前記ゲート電極との間から、前記コンタクト領域と前記ゲート電極との間に亘って設けられていることを特徴とする請求項15又は請求項16に記載の半導体装置。
- 前記ゲート絶縁膜は、前記第1の部分よりも厚い膜厚で前記トレンチの底部に設けられた第3の部分を更に有することを特徴とする請求項14に記載の半導体装置。
- 前記第1の部分は熱酸化膜で形成され、前記第2及び第3の部分は堆積膜で形成されていることを特徴とする請求項19に記載の半導体装置。
- 第1導電型の半導体基板の表層部に第2導電型のベース領域を形成する工程と、
前記ベース領域の表層部の周期的な複数の領域に、第1導電型を呈する第1不純物イオンを選択的に一方向に沿って注入する工程と、
前記複数の領域の配列パターンの間隔よりも間隔が広く前記複数の領域の配列と同一配列ピッチのパターンで、かつ前記第1不純物イオンよりも低い加速エネルギで、前記第1不純物イオンが注入された前記複数の領域の間の前記ベース領域の表層部に、第1導電型を呈する第2不純物イオンを前記一方向に沿って選択的に注入する工程と、
前記第1不純物イオンが注入された領域で第2導電型のコンタクト領域が形成され、かつ前記第2不純物イオンが注入された領域で第1導電型のエミッタ領域が形成されるように前記第1及び第2不純物イオンを活性化する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記活性化する工程は、前記コンタクト領域が前記エミッタ領域よりも深く、かつ前記エミッタ領域の直下に廻り込むように熱処理を施すことを含むことを特徴とする請求項21に記載の半導体装置の製造方法。
- 前記第2不純物イオンの注入は、前記第1不純物イオンよりも高いドーズ量で行うことを特徴とする請求項21に記載の半導体装置の製造方法。
- 半導体基板の主面にトレンチを形成すると共に、前記トレンチで挟まれたメサ領域を形成する工程と、
前記メサ領域を含む前記半導体基板の主面上に層間絶縁膜を形成する工程と、
前記層間絶縁膜を貫通するようにコンタクト孔を開孔する工程と、
前記コンタクト孔の内部を含む前記層間絶縁膜上にバリアメタル膜を形成する工程と、
前記コンタクト孔の内部を埋め尽くすように前記バリアメタル膜上にプラグ材を形成する工程と、
前記層間絶縁膜上の前記プラグ材及び前記バリアメタル膜を選択的に除去して、前記コンタクト孔の内部に前記プラグ材からなるコンタクトプラグを埋め込む工程と、
前記半導体基板の主面側の上方から前記半導体基板の主面に向って荷電粒子を照射してライフタイム制御を行う工程と、
前記半導体基板に水素アニールを施す工程と、
を含むことを特徴とする半導体装置の製造方法。 - 半導体基板の主面にトレンチを形成すると共に、前記トレンチで挟まれたメサ領域を形成する工程と、
前記メサ領域の側壁に前記メサ領域の長手方向に沿って周期的に前記メサ領域の側壁が露出するパターンとなるように堆積膜を形成する工程と、
前記半導体基板に熱酸化処理を施し、前記メサ領域の長手方向において隣り合う前記堆積膜の間の前記側壁の前記露出した箇所に前記堆積膜よりも膜厚が薄い熱酸化膜を形成することにより、前記堆積膜及び前記熱酸化膜を有するゲート絶縁膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016573227A JP6406361B2 (ja) | 2015-02-03 | 2016-02-03 | 半導体装置及びその製造方法 |
DE112016000071.5T DE112016000071T5 (de) | 2015-02-03 | 2016-02-03 | Halbleitervorrichtung und Verfahren zu ihrer Herstellung |
CN201680002154.1A CN106663692B (zh) | 2015-02-03 | 2016-02-03 | 半导体装置及其制造方法 |
US15/416,453 US11127844B2 (en) | 2015-02-03 | 2017-01-26 | Semiconductor device and method for manufacturing the same |
US17/403,666 US20210376132A1 (en) | 2015-02-03 | 2021-08-16 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015019372 | 2015-02-03 | ||
JP2015-019372 | 2015-02-03 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/416,453 Continuation US11127844B2 (en) | 2015-02-03 | 2017-01-26 | Semiconductor device and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016125490A1 true WO2016125490A1 (ja) | 2016-08-11 |
Family
ID=56563844
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2016/000562 WO2016125490A1 (ja) | 2015-02-03 | 2016-02-03 | 半導体装置及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US11127844B2 (ja) |
JP (2) | JP6406361B2 (ja) |
CN (1) | CN106663692B (ja) |
DE (1) | DE112016000071T5 (ja) |
WO (1) | WO2016125490A1 (ja) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018056233A1 (ja) * | 2016-09-20 | 2018-03-29 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
CN107946361A (zh) * | 2016-10-12 | 2018-04-20 | 富士电机株式会社 | 半导体装置 |
JP2018117016A (ja) * | 2017-01-17 | 2018-07-26 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP2019033208A (ja) * | 2017-08-09 | 2019-02-28 | 富士電機株式会社 | 半導体装置 |
JP2019054091A (ja) * | 2017-09-14 | 2019-04-04 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法、電力変換装置 |
JPWO2018139557A1 (ja) * | 2017-01-25 | 2019-11-14 | ローム株式会社 | 半導体装置 |
JP2020013828A (ja) * | 2018-07-13 | 2020-01-23 | 富士電機株式会社 | 半導体装置および製造方法 |
JP2020047676A (ja) * | 2018-09-14 | 2020-03-26 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP2021122076A (ja) * | 2017-01-17 | 2021-08-26 | 富士電機株式会社 | 半導体装置 |
WO2023157395A1 (ja) * | 2022-02-18 | 2023-08-24 | ローム株式会社 | 半導体装置およびその製造方法 |
CN117423714A (zh) * | 2023-12-18 | 2024-01-19 | 合肥晶合集成电路股份有限公司 | 半导体结构的制备方法及半导体结构 |
US11955540B2 (en) | 2019-04-16 | 2024-04-09 | Fuji Electric Co., Ltd. | Semiconductor device and production method |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016125490A1 (ja) * | 2015-02-03 | 2016-08-11 | 富士電機株式会社 | 半導体装置及びその製造方法 |
WO2017141998A1 (ja) * | 2016-02-15 | 2017-08-24 | 富士電機株式会社 | 半導体装置 |
US9806152B2 (en) * | 2016-03-04 | 2017-10-31 | Pakal Technologies Llc | Vertical insulated gate turn-off thyristor with intermediate p+ layer in p-base |
US10600897B2 (en) * | 2017-11-08 | 2020-03-24 | Fuji Electric Co., Ltd. | Semiconductor device |
JP7200488B2 (ja) * | 2018-03-19 | 2023-01-10 | 富士電機株式会社 | 絶縁ゲート型半導体装置 |
JP7283287B2 (ja) * | 2019-07-23 | 2023-05-30 | 株式会社デンソー | 半導体装置 |
CN112310204B (zh) * | 2019-07-26 | 2022-04-12 | 广东美的白色家电技术创新中心有限公司 | 绝缘栅双极型晶体管及其制作方法 |
JP2021082725A (ja) * | 2019-11-20 | 2021-05-27 | 三菱電機株式会社 | 半導体装置 |
JP7327672B2 (ja) * | 2020-07-03 | 2023-08-16 | 富士電機株式会社 | 半導体装置 |
WO2024024073A1 (ja) * | 2022-07-29 | 2024-02-01 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04258153A (ja) * | 1991-02-12 | 1992-09-14 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2004014763A (ja) * | 2002-06-06 | 2004-01-15 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
JP2004259934A (ja) * | 2003-02-26 | 2004-09-16 | Toyota Motor Corp | 高耐圧電界効果型半導体装置 |
WO2013046578A1 (ja) * | 2011-09-27 | 2013-04-04 | 株式会社デンソー | 半導体装置 |
JP2013084904A (ja) * | 2011-09-29 | 2013-05-09 | Toshiba Corp | 半導体装置 |
JP2013175707A (ja) * | 2012-01-23 | 2013-09-05 | Denso Corp | 半導体装置およびその製造方法 |
JP2014027076A (ja) * | 2012-07-26 | 2014-02-06 | Renesas Electronics Corp | 半導体装置 |
WO2014125584A1 (ja) * | 2013-02-13 | 2014-08-21 | トヨタ自動車株式会社 | 半導体装置 |
JP2014241426A (ja) * | 2008-12-25 | 2014-12-25 | ローム株式会社 | 半導体装置 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2983110B2 (ja) | 1992-06-24 | 1999-11-29 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JPH07122749A (ja) * | 1993-09-01 | 1995-05-12 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3325424B2 (ja) | 1995-03-31 | 2002-09-17 | 株式会社東芝 | 絶縁ゲート型半導体装置 |
JP3660799B2 (ja) * | 1997-09-08 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
JP4857566B2 (ja) | 2005-01-27 | 2012-01-18 | 富士電機株式会社 | 絶縁ゲート型半導体装置とその製造方法 |
JP4991134B2 (ja) * | 2005-09-15 | 2012-08-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5383009B2 (ja) * | 2007-07-17 | 2014-01-08 | 三菱電機株式会社 | 半導体装置の設計方法 |
JP2009111200A (ja) | 2007-10-31 | 2009-05-21 | Panasonic Corp | 半導体装置及びその製造方法 |
US8188484B2 (en) | 2008-12-25 | 2012-05-29 | Rohm Co., Ltd. | Semiconductor device |
JP5672719B2 (ja) | 2010-03-03 | 2015-02-18 | 株式会社デンソー | パワー素子を備えた半導体装置の製造方法 |
JP5246302B2 (ja) * | 2010-09-08 | 2013-07-24 | 株式会社デンソー | 半導体装置 |
JP2012069861A (ja) | 2010-09-27 | 2012-04-05 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP5594276B2 (ja) * | 2010-12-08 | 2014-09-24 | 株式会社デンソー | 絶縁ゲート型半導体装置 |
JP5644793B2 (ja) * | 2012-03-02 | 2014-12-24 | 株式会社デンソー | 半導体装置 |
JP5754397B2 (ja) | 2012-03-09 | 2015-07-29 | 三菱電機株式会社 | 縦型トレンチigbtの製造方法 |
JP2016039170A (ja) * | 2014-08-05 | 2016-03-22 | 株式会社東芝 | 半導体装置 |
WO2016125490A1 (ja) * | 2015-02-03 | 2016-08-11 | 富士電機株式会社 | 半導体装置及びその製造方法 |
-
2016
- 2016-02-03 WO PCT/JP2016/000562 patent/WO2016125490A1/ja active Application Filing
- 2016-02-03 DE DE112016000071.5T patent/DE112016000071T5/de active Pending
- 2016-02-03 JP JP2016573227A patent/JP6406361B2/ja active Active
- 2016-02-03 CN CN201680002154.1A patent/CN106663692B/zh active Active
-
2017
- 2017-01-26 US US15/416,453 patent/US11127844B2/en active Active
-
2018
- 2018-09-05 JP JP2018165600A patent/JP6683228B2/ja active Active
-
2021
- 2021-08-16 US US17/403,666 patent/US20210376132A1/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04258153A (ja) * | 1991-02-12 | 1992-09-14 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2004014763A (ja) * | 2002-06-06 | 2004-01-15 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
JP2004259934A (ja) * | 2003-02-26 | 2004-09-16 | Toyota Motor Corp | 高耐圧電界効果型半導体装置 |
JP2014241426A (ja) * | 2008-12-25 | 2014-12-25 | ローム株式会社 | 半導体装置 |
WO2013046578A1 (ja) * | 2011-09-27 | 2013-04-04 | 株式会社デンソー | 半導体装置 |
JP2013084904A (ja) * | 2011-09-29 | 2013-05-09 | Toshiba Corp | 半導体装置 |
JP2013175707A (ja) * | 2012-01-23 | 2013-09-05 | Denso Corp | 半導体装置およびその製造方法 |
JP2014027076A (ja) * | 2012-07-26 | 2014-02-06 | Renesas Electronics Corp | 半導体装置 |
WO2014125584A1 (ja) * | 2013-02-13 | 2014-08-21 | トヨタ自動車株式会社 | 半導体装置 |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2018056233A1 (ja) * | 2016-09-20 | 2019-06-24 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US11869961B2 (en) | 2016-09-20 | 2024-01-09 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
WO2018056233A1 (ja) * | 2016-09-20 | 2018-03-29 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US11264490B2 (en) | 2016-09-20 | 2022-03-01 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
CN109314139A (zh) * | 2016-09-20 | 2019-02-05 | 富士电机株式会社 | 半导体装置和半导体装置的制造方法 |
CN107946361B (zh) * | 2016-10-12 | 2023-03-03 | 富士电机株式会社 | 半导体装置 |
CN107946361A (zh) * | 2016-10-12 | 2018-04-20 | 富士电机株式会社 | 半导体装置 |
JP2021122076A (ja) * | 2017-01-17 | 2021-08-26 | 富士電機株式会社 | 半導体装置 |
JP2018117016A (ja) * | 2017-01-17 | 2018-07-26 | 株式会社デンソー | 半導体装置およびその製造方法 |
CN110235229A (zh) * | 2017-01-17 | 2019-09-13 | 株式会社电装 | 半导体装置及其制造方法 |
US20190341308A1 (en) * | 2017-01-17 | 2019-11-07 | Denso Corporation | Semiconductor device and manufacturing method of semiconductor device |
JP7295162B2 (ja) | 2017-01-17 | 2023-06-20 | 富士電機株式会社 | 半導体装置 |
CN110235229B (zh) * | 2017-01-17 | 2022-08-12 | 株式会社电装 | 半导体装置及其制造方法 |
WO2018135541A1 (ja) * | 2017-01-17 | 2018-07-26 | 株式会社デンソー | 半導体装置およびその製造方法 |
US10923395B2 (en) * | 2017-01-17 | 2021-02-16 | Denso Corporation | Semiconductor device and manufacturing method of semiconductor device |
JPWO2018139557A1 (ja) * | 2017-01-25 | 2019-11-14 | ローム株式会社 | 半導体装置 |
US12027579B2 (en) | 2017-01-25 | 2024-07-02 | Rohm Co., Ltd. | Semiconductor device having a carrier trapping region including crystal defects |
JP7032331B2 (ja) | 2017-01-25 | 2022-03-08 | ローム株式会社 | 半導体装置 |
US10535761B2 (en) | 2017-08-09 | 2020-01-14 | Fuji Electric Co., Ltd. | Semiconductor device including a mesa portion including an emitter region having a varied width |
JP2019033208A (ja) * | 2017-08-09 | 2019-02-28 | 富士電機株式会社 | 半導体装置 |
US11239350B2 (en) | 2017-09-14 | 2022-02-01 | Mitsubishi Electric Corporation | Semiconductor device, method of manufacturing semiconductor device, power conversion device |
JP2019054091A (ja) * | 2017-09-14 | 2019-04-04 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法、電力変換装置 |
JP2020013828A (ja) * | 2018-07-13 | 2020-01-23 | 富士電機株式会社 | 半導体装置および製造方法 |
JP7283036B2 (ja) | 2018-07-13 | 2023-05-30 | 富士電機株式会社 | 半導体装置および製造方法 |
JP7119814B2 (ja) | 2018-09-14 | 2022-08-17 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP2020047676A (ja) * | 2018-09-14 | 2020-03-26 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
US11955540B2 (en) | 2019-04-16 | 2024-04-09 | Fuji Electric Co., Ltd. | Semiconductor device and production method |
WO2023157395A1 (ja) * | 2022-02-18 | 2023-08-24 | ローム株式会社 | 半導体装置およびその製造方法 |
CN117423714A (zh) * | 2023-12-18 | 2024-01-19 | 合肥晶合集成电路股份有限公司 | 半导体结构的制备方法及半导体结构 |
CN117423714B (zh) * | 2023-12-18 | 2024-04-05 | 合肥晶合集成电路股份有限公司 | 半导体结构的制备方法及半导体结构 |
Also Published As
Publication number | Publication date |
---|---|
JP6683228B2 (ja) | 2020-04-15 |
JPWO2016125490A1 (ja) | 2017-10-26 |
JP6406361B2 (ja) | 2018-10-17 |
CN106663692A (zh) | 2017-05-10 |
DE112016000071T5 (de) | 2017-03-23 |
US20210376132A1 (en) | 2021-12-02 |
CN106663692B (zh) | 2020-03-06 |
US20170141216A1 (en) | 2017-05-18 |
US11127844B2 (en) | 2021-09-21 |
JP2019016802A (ja) | 2019-01-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6683228B2 (ja) | 半導体装置 | |
US9536875B2 (en) | Semiconductor device | |
JP6369173B2 (ja) | 縦型半導体装置およびその製造方法 | |
US20210013310A1 (en) | Silicon Carbide Device with Compensation Layer and Method of Manufacturing | |
JP6728953B2 (ja) | 半導体装置及びその製造方法 | |
JP2009004668A (ja) | 半導体装置 | |
JP2009043966A (ja) | 半導体装置及びその製造方法 | |
JP2006210392A (ja) | 半導体装置およびその製造方法 | |
US10651270B2 (en) | Semiconductor device having a trench structure | |
JP6345378B1 (ja) | 半導体装置 | |
CN108550618B (zh) | 半导体装置 | |
JP2009088005A (ja) | 半導体装置およびその製造方法 | |
JP2015177010A (ja) | 半導体装置およびその製造方法 | |
JP2019102761A (ja) | 半導体装置および半導体装置の製造方法 | |
CN108574000B (zh) | 半导体装置和半导体装置的制造方法 | |
JP2005203565A (ja) | 半導体装置およびその製造方法 | |
JP2009043782A (ja) | 半導体装置及びその製造方法 | |
CN115132833A (zh) | 半导体装置及半导体装置的制造方法 | |
JP4997715B2 (ja) | 半導体装置およびその製造方法 | |
JP2020136416A (ja) | 半導体装置および半導体装置の製造方法 | |
JP7528687B2 (ja) | 半導体装置 | |
KR102400895B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP6649197B2 (ja) | 半導体装置の製造方法 | |
CN114388612A (zh) | 半导体装置及半导体装置的制造方法 | |
JP2013251467A (ja) | 半導体装置および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16746322 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2016573227 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112016000071 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16746322 Country of ref document: EP Kind code of ref document: A1 |