WO2017141998A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2017141998A1 WO2017141998A1 PCT/JP2017/005601 JP2017005601W WO2017141998A1 WO 2017141998 A1 WO2017141998 A1 WO 2017141998A1 JP 2017005601 W JP2017005601 W JP 2017005601W WO 2017141998 A1 WO2017141998 A1 WO 2017141998A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 178
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 238000003860 storage Methods 0.000 claims abstract description 80
- 238000009825 accumulation Methods 0.000 claims description 80
- 239000012535 impurity Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 description 131
- 238000005468 ion implantation Methods 0.000 description 17
- 238000000034 method Methods 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Definitions
- the present invention relates to a semiconductor device.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2012-43890
- the accumulation layer may be formed shallow and the gate threshold may be lowered.
- a semiconductor substrate In a first aspect of the present invention, a semiconductor substrate, a drift layer of a first conductivity type formed on the semiconductor substrate, and a base region of a second conductivity type formed above the drift layer in the semiconductor substrate, A storage layer of the first conductivity type provided between the drift layer and the base region and having a higher concentration than the drift layer, the storage layer comprising a first storage region and a region different from the storage layer in plan view And a second storage region formed shallower than the first storage region.
- the semiconductor device may include a transistor portion formed on a semiconductor substrate.
- the transistor portion is formed on the front surface of the semiconductor substrate, and is formed between a plurality of trench portions arranged in a predetermined direction and a plurality of trench portions on the front surface of the semiconductor substrate.
- an emitter region of the first conductivity type that is higher in concentration than the layer.
- the first storage region and the second storage region may be formed between the plurality of trench portions.
- the transistor portion may have a boundary region in which the emitter region is not formed between the plurality of trench portions at one end in the arrangement direction of the transistor portions.
- the transistor portion may have a boundary region in which an emitter region is not formed between the plurality of trench portions at both ends of one end in the arrangement direction of the transistor portion and the other end opposite to the one end.
- the width of the second storage region in the boundary region may be equal to the width of the mesa surrounded by the plurality of trench portions.
- the semiconductor substrate has a contact region of the second conductivity type higher in concentration than the base region on the front surface of the semiconductor substrate in the boundary region.
- the drift layer may be connected to the base region at the boundary region.
- the depth of the second accumulation region may gradually change in the direction parallel to the front surface of the semiconductor substrate.
- the semiconductor device may further include a diode unit formed on the semiconductor substrate.
- the boundary region may be formed on the boundary side of the transistor portion with the diode portion.
- the second accumulation region may include a region formed at least at the same depth as the center position in the depth direction of the base region.
- the impurity concentration of the lower end of the second accumulation region may be lower than the impurity concentration of the lower end of the first accumulation region.
- the semiconductor device may further include a well region of the second conductivity type on the front surface of the semiconductor substrate on the side in the extension direction in which the transistor portion extends in plan view.
- the second accumulation region may be formed on the boundary side of the accumulation layer with the well region in plan view.
- a semiconductor substrate a drift layer of a first conductivity type formed on the semiconductor substrate, and a base region of the second conductivity type formed above the drift layer in the semiconductor substrate;
- An accumulation layer of the first conductivity type provided between the drift layer and the base region and having a concentration higher than that of the drift layer, formed on the front surface of the semiconductor substrate, and arranged in a predetermined arrangement direction
- the storage layer is shallower than the first storage region on the side of the boundary between the first storage region and the region different from the storage layer in plan view at one end of the arrangement direction of the plurality of trenches.
- a semiconductor device having a formed second storage region.
- FIG. 1 is a plan view showing an example of a semiconductor device 100 according to a first embodiment.
- FIG. 2 is a view showing an example of the cross section aa ′ of the semiconductor device 100 according to the first embodiment;
- FIG. 18 is a plan view showing an example of a semiconductor device 500 according to Comparative Example 1; An example of the bb 'cross section of the semiconductor device 500 which concerns on the comparative example 1 is shown.
- FIG. 7 is a plan view showing an example of a semiconductor device 100 according to a second embodiment.
- FIG. 6 is a view showing an example of a cross section taken along line cc 'of the semiconductor device 100 according to the second embodiment;
- One example of a plan view of the semiconductor device 100 is shown.
- FIG. 10 shows an example of a structure in which the vicinity of the trench portion is enlarged.
- FIG. 10 shows an example of a plan view of a semiconductor device 100 according to a third embodiment.
- FIG. 18 is a view showing an example of a dd ′ cross section of the semiconductor device 100 according to the third embodiment;
- FIG. 1 is a plan view showing an example of a semiconductor device 100 according to a first embodiment.
- the semiconductor device 100 of this example is a semiconductor chip having a transistor unit 70 including a transistor such as an IGBT (Insulated Gate Bipolar Transistor) and a diode unit 80 including a diode such as a FWD (Free Wheel Diode). Further, the transistor unit 70 has a boundary region 75 on the boundary side between the transistor unit 70 and the diode unit 80 in plan view. In FIG. 1, the front surface of the chip around the chip end is shown, and other regions are omitted.
- IGBT Insulated Gate Bipolar Transistor
- the X direction and the Y direction are directions perpendicular to each other, and the Z direction is a direction perpendicular to the XY plane.
- the X direction, the Y direction and the Z direction form a so-called right hand system.
- the semiconductor substrate of this example has a top surface in the + Z direction and a back surface in the ⁇ Z direction. Note that “upper” and “upper” mean the + Z direction. On the other hand, "below” and “below” mean the -Z direction.
- FIG. 1 shows the active region of the semiconductor substrate in the semiconductor device 100
- the semiconductor device 100 may have an edge termination region surrounding the active region.
- the active region indicates a region through which current flows when the semiconductor device 100 is controlled to be in an on state.
- the edge termination region relieves the concentration of electric field on the front side of the semiconductor substrate.
- the edge termination region has, for example, a guard ring, a field plate, a resurf and a structure combining them.
- the gate electrode 50, the emitter electrode 52, the gate trench portion 40, the dummy trench portion 30, the emitter trench portion 60, the well region 17, the emitter region 12 and the base region are provided on the front surface side of the chip. And 14, contact regions 15 and contact holes 54, 55, and 56.
- a gate trench portion 40, a dummy trench portion 30, an emitter trench portion 60, a well region 17, an emitter region 12, a base region 14 and a contact region 15 are formed in the inside of the front surface side of the semiconductor substrate.
- An emitter electrode 52 and a gate electrode 50 are provided above the front surface of the semiconductor substrate.
- An interlayer insulating film is formed between the emitter electrode 52 and the gate electrode 50 and the front surface of the semiconductor substrate, but is omitted in FIG.
- the contact holes 54, 55, 56 are formed through the interlayer insulating film formed above the semiconductor substrate.
- the positions at which the contact holes 54, 55, 56 are formed are not particularly limited to this example.
- Emitter electrode 52 is formed above gate trench portion 40, dummy trench portion 30, emitter trench portion 60, well region 17, emitter region 12, base region 14 and contact region 15. Emitter electrode 52 is in contact with the semiconductor substrate through contact holes 54 and 56. Emitter electrode 52 is formed of a material containing a metal. In one example, at least a partial region of the emitter electrode 52 is formed of aluminum. Emitter electrode 52 may have a region formed of a material containing tungsten. The emitter electrode 52 in this example is provided corresponding to the transistor unit 70 and the diode unit 80, respectively.
- Gate electrode 50 contacts the semiconductor substrate through contact hole 55. However, the gate electrode 50 is not formed above the dummy trench portion 30 and the emitter trench portion 60.
- the gate electrode 50 is formed of a material containing a metal. In one example, at least a partial region of the gate electrode 50 is formed of aluminum.
- the gate electrode 50 may have a region formed of a material containing tungsten.
- the gate electrode 50 of this example is provided corresponding to the transistor unit 70 and the diode unit 80, respectively.
- the gate electrode 50 of this example is formed of the same material as the emitter electrode 52. However, the gate electrode 50 may be formed of a material different from that of the emitter electrode 52.
- the dummy trench portion 30 is formed extending in a predetermined extending direction on the front surface of the semiconductor substrate.
- One or more dummy trench portions 30 are arranged at predetermined intervals in the region of the transistor portion 70 along the predetermined arrangement direction with the gate trench portion 40.
- the dummy trench portion 30 in this example has a linear shape, and is formed extending in a direction perpendicular to the arrangement direction.
- the arrangement direction of the trench portions refers to the X axis direction
- the extension direction of the trench portions refers to the Y axis direction.
- the gate trench portion 40 has an opposing portion 41 and a projecting portion 43.
- the facing portion 41 is formed so as to extend in the above-described extending direction in a range facing the dummy trench portion 30. That is, the facing portion 41 is formed in parallel to the dummy trench portion 30.
- the protruding portion 43 is further extended from the facing portion 41 and is formed in a range not facing the dummy trench portion 30.
- two opposing portions 41 provided on both sides of the dummy trench portion 30 are connected by one projecting portion 43. At least a portion of the protrusion 43 may have a curvilinear shape.
- the gate trench portions 40 and the dummy trench portions 30 of this example are alternately arranged in a predetermined arrangement direction. Also, the trench portions may be arranged at regular intervals. However, the arrangement of each trench is not limited to the above example. A plurality of gate trench portions 40 may be disposed between the two dummy trench portions 30. Also, the number of gate trench portions 40 provided between the respective dummy trench portions 30 may not be constant.
- the contact hole 55 is formed in the insulating layer covering the protrusion 43.
- the contact hole 55 may be formed corresponding to the region farthest from the facing portion 41 in the protrusion 43.
- the projecting portion 43 in this example has a portion that extends in a direction orthogonal to the facing portion 41 in a region farthest from the facing portion 41.
- the contact hole 55 may be formed corresponding to the corresponding portion of the protrusion 43.
- Emitter trench portion 60 is provided in the region of diode portion 80.
- Emitter trench portion 60 may have the same shape as gate trench portion 40. However, the length in the extension direction of the emitter trench 60 may be shorter than that of the gate trench 40. The length of the emitter trench portion 60 in this example is the same as that of the dummy trench portion 30.
- the well region 17 is formed in a predetermined range from the side where the gate electrode 50 is provided. A portion of the dummy trench portion 30, the emitter trench portion 60 and the facing portion 41 on the gate electrode 50 side is formed in the well region 17.
- the protrusion 43 may be entirely formed in the well region 17.
- the semiconductor substrate has a first conductivity type, and the well region 17 has a second conductivity type different from the semiconductor substrate.
- the semiconductor substrate of this example is N ⁇ type, and the well region 17 is P + type.
- the first conductivity type is described as N-type
- the second conductivity type is described as P-type.
- the first conductivity type may be P-type
- the second conductivity type may be N-type.
- the base region 14 is formed in a region sandwiched by the respective trench portions.
- Base region 14 is a second conductivity type having a lower impurity concentration than well region 17.
- the base region 14 in this example is P-type.
- the contact region 15 is a region of the second conductivity type in which the impurity concentration is higher than that of the base region 14 on the front surface of the base region 14.
- the contact region 15 in this example is P + type.
- Emitter region 12 is selectively formed in part of the front surface of contact region 15 in transistor portion 70 as a region of a first conductivity type having a higher impurity concentration than the semiconductor substrate.
- the emitter region 12 in this example is N + type.
- Each of contact region 15 and emitter region 12 is formed from one adjacent trench portion to the other trench portion.
- the one or more contact regions 15 and the one or more emitter regions 12 of the transistor portion 70 are formed so as to be alternately exposed along the extending direction of the trench portion in the region sandwiched by the respective trench portions.
- the contact hole 54 is formed above the contact region 15, the emitter region 12 and the dummy trench portion 30 in the transistor portion 70.
- the contact hole 54 in this example is formed across the emitter region 12 and the contact region 15.
- the contact hole 54 may be formed to expose the entire area of the front surface of the emitter region 12.
- the contact hole 54 may be formed to expose the entire area of the front surface of the contact region 15.
- contact hole 54 is not formed in the region corresponding to base region 14 and well region 17.
- Contact hole 54 is formed above each of contact region 15, base region 14 and emitter trench portion 60 in diode portion 80.
- the contact holes 54 of the transistor section 70 and the contact holes 54 of the diode section 80 have the same length in the extending direction of the respective trench sections.
- the boundary region 75 is formed in the transistor portion 70 near the boundary between the transistor portion 70 and the region other than the transistor portion 70 in plan view. Boundary region 75 may be provided in the vicinity of any boundary between the transistor portion 70 in the X-axis direction with another region and the transistor portion 70 with the other region in the Y-axis direction. The boundary region 75 in this example is formed on the positive side in the X-axis direction of the transistor unit 70 and on the boundary side with the diode unit 80 side. Boundary region 75 includes dummy trench portion 30 and gate trench portion 40. Boundary region 75 does not have emitter region 12 on the front surface of the semiconductor substrate. For example, the boundary region 75 has a contact region 15 on the front surface of the semiconductor substrate. The boundary region 75 may also have a base region 14 on the front surface of the semiconductor substrate.
- FIG. 2 is a view showing an example of an aa ′ cross section of the semiconductor device 100 according to the first embodiment.
- the semiconductor device 100 of this example has the semiconductor substrate 10, the emitter electrode 52, and the collector electrode 24 in the cross section.
- Emitter electrode 52 is formed on the front surface of semiconductor substrate 10.
- Emitter electrode 52 is electrically connected to emitter terminal 53.
- the collector electrode 24 is formed on the back surface of the semiconductor substrate 10.
- the collector electrode 24 is electrically connected to the collector terminal.
- Emitter electrode 52 and collector electrode 24 are formed of a conductive material such as metal.
- the surface on the side of the emitter electrode 52 of each member such as the substrate, the layer, and the region is referred to as the front surface, and the surface on the side of the collector electrode 24 is referred to as the back surface or the bottom.
- a direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.
- the semiconductor substrate 10 may be a silicon substrate, or may be a compound semiconductor substrate such as a silicon carbide substrate or a nitride semiconductor substrate.
- a P-type base region 14 is formed on the front surface side of the semiconductor substrate 10.
- the N + -type emitter region 12 is selectively formed in a partial region on the front surface side of the base region 14.
- the semiconductor substrate 10 further includes an N + -type storage layer 16, an N ⁇ -type drift region 18, an N ⁇ -type buffer region 20, a P + -type collector region 22, and an N + -type cathode region 82.
- the accumulation layer 16 is formed on the back side of the base region 14.
- the accumulation layer 16 is formed to have a concentration higher than the impurity concentration of the drift region 18.
- the storage layer 16 is formed by implanting an N-type impurity such as phosphorus from the front surface side of the semiconductor substrate 10.
- the accumulation layer 16 is formed in the mesa portion of the semiconductor substrate 10.
- the mesa portion of the semiconductor substrate 10 refers to a plateau portion sandwiched by the trench portion.
- the mesa portion in this example shows a portion sandwiched between the dummy trench portion 30 and the gate trench portion 40, the present invention is not limited to this example as long as it is a region sandwiched by the trench portions.
- the accumulation layer 16 is formed in the mesa portion between the dummy trench portion 30 and the gate trench portion 40.
- the accumulation layer 16 may be provided to cover the respective regions between the dummy trench portion 30 and the gate trench portion 40.
- Providing the storage layer 16 suppresses the flow of holes injected from the collector region 22 to the drift region 18 into the base region 14 in the on state, thereby promoting the injection of electrons from the emitter region 12 to the base region 14. The effect is enhanced. This reduces the on voltage.
- the accumulation layer 16 includes an accumulation layer 16a and an accumulation layer 16b.
- the accumulation layer 16 a is formed between the plurality of trench portions in the transistor portion 70.
- a part of storage layer 16 a may be formed in boundary region 75.
- the accumulation layer 16 a is an example of a first accumulation region of the accumulation layer 16.
- the accumulation layer 16 b is formed between the plurality of trench portions in the boundary region 75.
- the accumulation layer 16 b is disposed on the boundary side between the accumulation layer 16 and a different area in plan view. That is, the accumulation layer 16b is disposed on the outer peripheral side of the accumulation layer 16a. A part of the accumulation layer 16 b may be formed in the boundary region 75.
- the accumulation layer 16 b is formed shallower than the accumulation layer 16 a in the semiconductor substrate 10. By forming the storage layer 16 b shallow, the field plate effect in the boundary region 75 is easily obtained, and the withstand voltage is improved.
- the accumulation layer 16 b is an example of a second accumulation region of the accumulation layer 16.
- the width of the storage layer 16b in this example is equal to the mesa width surrounded by the plurality of trench portions.
- the width of the storage layer 16 b in this example is equal to the width between the dummy trench portion 30 and the gate trench portion 40.
- the mesa width indicates the width of the mesa portion in the arrangement direction of the trench portions. That is, the mesa width indicates the width of the semiconductor substrate 10 between adjacent trench portions.
- Drift region 18 is formed on the back surface side of storage layer 16.
- Buffer region 20 is formed on the back side of drift region 18.
- the impurity concentration of the buffer region 20 is higher than the impurity concentration of the drift region 18.
- Buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the back side of base region 14 from reaching collector region 22 and cathode region 82.
- the collector region 22 is formed on the back surface side of the buffer region 20 in the region of the transistor unit 70.
- the cathode region 82 is formed on the back surface side of the buffer region 20 in the region of the diode section 80. Further, a collector electrode 24 is provided on the back surface of the collector region 22 and the cathode region 82.
- Collector region 22 may be formed on the back side of boundary region 75, and cathode region 82 may be formed. In the present embodiment, the collector region 22 is formed.
- One or more gate trench portions 40, one or more dummy trench portions 30, and one or more emitter trench portions 60 are formed on the front surface side of the semiconductor substrate 10. Each trench portion penetrates base region 14 from the front surface of semiconductor substrate 10 to reach drift region 18.
- the gate trench portion 40 and the dummy trench portion 30 penetrate the emitter region 12, the base region 14 and the storage layer 16 from the front surface of the semiconductor substrate 10 to reach the drift region 18.
- the emitter trench portion 60 penetrates the base region 14 and the accumulation layer 16 from the front surface of the semiconductor substrate 10 to reach the drift region 18.
- the gate trench portion 40 has an insulating film 42 and a gate conductive portion 44 formed on the front surface side of the semiconductor substrate 10.
- the gate conductive portion 44 is formed on the front surface side of the semiconductor substrate 10 in the gate trench portion 40. Gate conductive portion 44 includes a region facing at least adjacent base region 14. Each gate conductive portion 44 is electrically connected to the gate terminal 51. In the present embodiment, as shown in FIG. 1, the gate conductive portion 44 is electrically connected to the gate electrode 50 in the projecting portion 43. Also, the gate electrode 50 is electrically connected to the gate terminal 51. When a predetermined voltage is applied to the gate conductive portion 44 through the gate terminal 51, a channel is formed in the surface layer of the interface in the base region 14 in contact with the gate trench.
- the gate conductive portion 44 in this example is formed of a conductive material such as polysilicon.
- the gate conductive portion 44 is an example of a first conductive portion in the gate trench portion 40.
- the insulating film 42 is formed to cover the periphery of the gate conductive portion 44. That is, the insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10.
- the insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
- the dummy trench portion 30 has an insulating film 32 and a dummy conductive portion 34 formed on the front surface side of the semiconductor substrate 10.
- the dummy conductive portion 34 is formed on the front surface side of the semiconductor substrate 10 in the dummy trench portion 30.
- the dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.
- the dummy conductive portion 34 is formed of a conductive material such as polysilicon.
- the dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.
- the dummy conductive portion 34 is an example of a first conductive portion in the dummy trench portion 30.
- the insulating film 32 is formed to cover the side surface and the bottom surface of the dummy conductive portion 34. That is, the insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10.
- the insulating film 32 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the dummy trench.
- the diode unit 80 is provided in a region near the transistor unit 70.
- the diode unit 80 has a base region 14, an accumulation layer 16, a drift region 18 and a buffer region 20 in the same layer as the transistor unit 70.
- a cathode region 82 is provided on the back side of the buffer region 20 of the diode unit 80.
- the diode unit 80 has one or more emitter trench units 60. Further, the emitter region 12 is not formed in the diode section 80.
- Emitter trench portion 60 penetrates base region 14 and storage layer 16 from the front surface side of base region 14 to reach drift region 18.
- Each emitter trench portion 60 includes an insulating film 62 and an emitter conductive portion 64.
- Emitter conductive portion 64 is formed on the front surface side of semiconductor substrate 10 in emitter trench portion 60. Emitter conductive portion 64 is electrically connected to emitter terminal 53.
- the insulating film 62 is formed to cover the side surface and the bottom surface of the emitter conductive portion 64. In addition, the insulating film 62 is formed to cover the inner wall of the emitter trench.
- the boundary region 75 refers to a region in which the emitter region 12 is not formed on the boundary side between the transistor portion 70 and the other region in plan view.
- the emitter region 12 is not formed between the plurality of trench portions at one end in the arrangement direction of the transistor portions 70.
- one end in the arrangement direction of the transistor units 70 indicates a region on the X axis direction positive side of the transistor units 70 at the boundary with the diode unit 80.
- the boundary region 75 in this example has a contact region 15 on the front surface of the semiconductor substrate 10 in the boundary region 75.
- FIG. 3 is a plan view showing an example of a semiconductor device 500 according to Comparative Example 1.
- FIG. 4 shows an example of the bb ′ cross section of the semiconductor device 500 according to the first comparative example.
- the semiconductor device 500 of this example differs from the semiconductor device 100 according to the first embodiment in that the emitter region 512 is also formed in the region 575.
- the semiconductor device 500 of this example includes a transistor portion 570 and a diode portion 580.
- the semiconductor device 500 includes an emitter region 512, a base region 514, a contact region 515, an accumulation layer 516, a well region 517, an interlayer insulating film 526, a dummy trench portion 530, and a gate trench portion 540 on the front surface of the semiconductor substrate 510.
- Emitter trench portion 560, gate electrode 550 and emitter electrode 552 are provided.
- the dummy trench portion 530 has an insulating film 532 and a dummy conductive portion 534
- the gate trench portion 540 has an insulating film 542 and a gate conductive portion 544.
- Emitter trench portion 560 has insulating film 562 and emitter conductive portion 564.
- the accumulation layer 516 includes an accumulation layer 516a and an accumulation layer 516b.
- the semiconductor device 500 of this example includes the drift region 518, the buffer region 520, the collector region 522, and the cathode region 582 formed in the semiconductor substrate 510.
- a collector electrode 524 is formed on the back surface side of the semiconductor substrate 510.
- the gate electrode 550 is connected to the gate terminal 551 and connected to the semiconductor substrate 510 through the contact hole 555.
- the emitter electrode 552 is connected to the emitter terminal 553 and connected to the semiconductor substrate 510 through the contact hole 554 or the contact hole 556.
- the region 575 is formed on the boundary side with the other region of the transistor portion 570 in plan view.
- the region 575 has a storage layer 516 b which is a shallow storage layer 516.
- the region 575 has an emitter region 512 on the front surface of the semiconductor substrate 510. Therefore, in the region 575, the distance between the emitter region 512 and the accumulation layer 516b is shortened. As a result, the gate threshold of the semiconductor device 500 is lowered.
- FIG. 5 is a plan view showing an example of the semiconductor device 100 according to the second embodiment.
- FIG. 6 is a view showing an example of a cross section taken along the line cc 'of the semiconductor device 100 according to the second embodiment.
- the semiconductor device 100 of this example has a boundary region 75 in which the emitter region 12 is not formed on the boundary side with the other region in the transistor portion 70.
- the boundary region 75 in this example corresponds to a region from the region where the emitter region 12 is not formed to the region on the transistor portion 70 side of the emitter trench portion 60 in the cc 'cross section of the semiconductor device 100.
- the semiconductor device 100 according to this embodiment is different from the semiconductor device 100 according to the first embodiment in that the base region 14 is provided on the front surface of the semiconductor substrate 10 in the boundary region 75.
- the contact region 15 may not be formed on the front surface of the semiconductor substrate 10 in the boundary region 75.
- the semiconductor device 100 according to the present embodiment does not have the emitter region 12 in the boundary region 75. Therefore, in the boundary region 75, even when the storage layer 16b is formed shallow, the distance between the emitter region 12 and the storage layer 16b is not shortened. Therefore, the semiconductor device 100 of this example can suppress the decrease of the gate threshold in the boundary region 75.
- FIG. 7 shows an example of a plan view of the semiconductor device 100.
- the semiconductor device 100 of this example is a semiconductor chip having a semiconductor substrate 10 in which an active region 102 and an outer region 105 are formed.
- the active region 102 is a region through which current flows when the semiconductor device 100 is driven.
- a plurality of transistor portions 70 and a diode portion 80 are provided in the active region 102.
- the transistor portions 70 and the diode portions 80 are alternately arranged in the X-axis direction in the active region 102. Further, the transistor unit 70 and the diode unit 80 are formed in three rows in the Y-axis direction.
- the outer region 105 is provided outside the active region 102.
- the outside of the active region 102 refers to a region which is not surrounded by the active region 102 and closer to the end of the semiconductor substrate 10 than the center of the active region 102.
- Outer region 105 may surround the perimeter of active region 102.
- the outer region 105 includes a gate pad, a sense unit, and a temperature detection unit. Further, an edge termination area 109 or the like may be provided further outside the outer area 105.
- Region A indicates a region in which the boundary on the + X side of the transistor unit 70 and the boundary on the ⁇ X side of the diode unit 80 face each other.
- the boundary region 75 is formed in the region of the transistor portion 70 in the region A.
- Region B indicates a region in which the boundary on the ⁇ X side of transistor portion 70 and the boundary on the + X side of diode portion 80 face each other.
- the boundary region 75 is formed in the region of the transistor portion 70 in the region B.
- the boundary region 75 may be formed in the region of the transistor portion 70 in both the region A and the region B.
- Regions A and B both include the boundary between the transistor portion 70 and the diode portion 80.
- the accumulation layer 16 is formed only in the transistor unit 70 and is not formed in the diode unit 80. Therefore, at the time of the ion implantation of the accumulation layer 16, the end portions of the resist for ion implantation are disposed in the region A and the region B. Therefore, the storage layer 16 b formed shallow in the regions A and B is formed.
- the arrangement of the transistor unit 70 and the diode unit 80 in this example is merely an example.
- the arrangement of the transistor unit 70 and the diode unit 80 may be appropriately changed according to the specifications of the semiconductor device 100. That is, the area in which the boundary area 75 is created may also be changed depending on the arrangement of the transistor unit 70.
- FIG. 8 shows an outline of a method of forming the accumulation layer 16 in the region A of FIG.
- FIG. 9 shows an outline of a method of forming the accumulation layer 16 in the region B of FIG.
- the ion implantation may be performed at high acceleration. Also, when performing ion implantation with high acceleration, channeling is performed at a predetermined angle to prevent ions from being implanted at a position deeper than a targeted position. When ion implantation is performed at a predetermined angle, ions may be decelerated by the resist 95 in the vicinity of the end of the resist 95 as in the region A and the region B of FIG. 7. Therefore, the region A or the region B may be driven at a position shallower than the target.
- the storage layer 16 b is formed in the region A.
- the storage layer 16 b is formed in the region B.
- the boundary region 75 in this example has three mesas of different structures.
- Boundary region 75 includes three regions of boundary region 75a, boundary region 75b, and boundary region 75c, depending on the structure of the mesa.
- the boundary region 75 a, the boundary region 75 b, and the boundary region 75 c are all common in that they do not have the emitter region 12.
- Boundary region 75a is provided on the side opposite to the side on which diode portion 80 is provided, with respect to boundary region 75b and boundary region 75c.
- Boundary region 75 a is a region in which base region 14 and storage layer 16 a are formed between dummy trench portion 30 and gate trench portion 40.
- Boundary region 75 b is a region in which base region 14 and storage layer 16 b are formed between dummy trench portion 30 and gate trench portion 40.
- Boundary region 75 c is provided on the side of diode portion 80 in boundary region 75 with respect to boundary region 75 a and boundary region 75 b.
- Boundary region 75 c is a region in which only base region 14 is formed between gate trench portion 40 and emitter trench portion 60. Further, in the boundary region 75 c, the base region 14 is connected to the drift region 18 between the gate trench portion 40 and the emitter trench portion 60.
- the storage layer 16 is not formed between the gate trench portion 40 and the emitter trench portion 60. Thereby, the semiconductor device 100 can improve the withstand voltage in the boundary region 75 where the electric field is concentrated. In addition, in the region where the accumulation layer 16 is not formed, the holes can be easily extracted. In the boundary region 75, it is preferable to have at least one boundary region 75c where the storage layer 16 is not formed.
- the boundary region 75 in the present example is formed adjacent to the diode unit 80 at one end in the arrangement direction of the transistor unit 70. However, as shown in FIG. 8 and FIG. 9, the boundary region 75 may be formed at both ends of one end of the transistor section 70 and the other end on the opposite side.
- the semiconductor device 100 rotates the implantation direction by 180 degrees and then performs the ion implantation again. For example, the semiconductor device 100 is ion-implanted from the + X direction to the ⁇ X direction, and then ion-implanted from the ⁇ X direction to the + X direction.
- the semiconductor device 100 can form the accumulation layer 16 b on both the + X side of the transistor unit 70 and the ⁇ X side of the transistor unit 70.
- FIG. 10 shows an example of a structure in which the vicinity of the trench portion is enlarged.
- the drawing in order to explain the dimensions in the vicinity of the dummy trench portion 30 and the gate trench portion 40, only a part of the structure is extracted and shown.
- the accumulation layer 16 b may include a region formed at least at the same depth as the center position in the depth direction of the base region 14. That is, the accumulation layer 16 b is formed shallow enough to include the same depth as the center position of the base region 14 in the depth direction.
- D C is the depth at the center position of the base region 14
- D T is the depth from the front surface of the semiconductor substrate 10 at the upper end of the accumulation layer 16 b
- D B is the semiconductor substrate 10 at the lower end of the accumulation layer 16 b. Assuming that the depth from the front surface of the lens, D T ⁇ D C ⁇ D B holds.
- the impurity concentration at the lower end of the accumulation layer 16 b may be lower than the impurity concentration at the lower end of the first accumulation region. That is, the fact that the accumulation layer 16b is formed shallow in the depth direction of the semiconductor substrate 10 means that in addition to the accumulation layer 16b being formed above the accumulation layer 16a, the impurity concentration distribution of the accumulation layer 16b is equal to the accumulation layer 16a. It is shifted to the front surface side of the semiconductor substrate 10 than the impurity concentration distribution of The impurity concentration of the accumulation layer 16 may have the same or higher impurity concentration than that of the base region 14.
- the impurity concentration of the accumulation layer 16 is 1E16 cm ⁇ 3 or more and 1E18 m ⁇ 3 or less.
- E is meant a power of 10, for example, 1E16 cm -3 means 1 ⁇ 10 16 cm -3.
- the accumulation layer 16b may be shallower than the accumulation layer 16a in a range of 0.1 ⁇ m to 1.0 ⁇ m, and more preferably shallow in a range of 0.3 ⁇ m to 0.7 ⁇ m.
- the accumulation layer 16b is formed 0.5 ⁇ m shallower than the accumulation layer 16a.
- the depth of the storage layer 16 b is adjusted by changing the tilt angle of the semiconductor substrate 10 at the time of ion implantation of the storage layer 16.
- the depth of the accumulation layer 16 b is also changed by the thickness and the material of the resist 95. Note that how shallow the storage layer 16 b is to be made may be determined according to the depth of the emitter region 12 and the base region 14, the depth of the trench portion, and the like.
- the emitter region 12, the base region 14 and the storage layer 16 in this example have thicknesses of 0.5 ⁇ m, 1.5 ⁇ m and 2.5 ⁇ m, respectively.
- FIG. 11 shows an example of a plan view of the semiconductor device 100 according to the third embodiment.
- FIG. 12 is a view showing an example of a dd ′ cross section of the semiconductor device 100 according to the third embodiment.
- the well region 17 is provided on the front surface of the semiconductor substrate 10 on the side in the extension direction in which the transistor unit 70 extends in plan view.
- the well region 17 in this example is formed on the side of the transistor portion 70 in the ⁇ Y axis direction, but may be formed on the side of the transistor portion 70 in the + Y axis direction.
- the accumulation layer 16 b is formed on the boundary side of the accumulation layer 16 with the well region 17 in a plan view.
- the storage layer 16 in this example is formed by ion implantation from the ⁇ Y direction to the + Y direction. Therefore, storage layer 16 has storage layer 16 b in a region adjacent to well region 17 positioned on the ⁇ Y-axis direction side of transistor portion 70.
- the storage layer 16 b may be separated by sandwiching the base region 14 without contacting the well region 17.
- the depth of the accumulation layer 16 b gradually changes in the direction parallel to the front surface of the semiconductor substrate 10.
- the depth of the storage layer 16 b is gradually reduced in the direction parallel to the front surface of the semiconductor substrate 10.
- the storage layer 16b is gradually shallowed in the negative side direction of the Y-axis direction in the dd ′ cross section of the semiconductor substrate 10.
- the region on the -Y axis side of the accumulation layer 16b is shallower than the accumulation layer 16a in the range of 0.1 ⁇ m to 1.0 ⁇ m, and more preferably in the range of 0.3 ⁇ m to 0.7 ⁇ m. It may be formed shallow.
- the region on the ⁇ Y axis side of the accumulation layer 16b is formed 0.5 ⁇ m shallower than the accumulation layer 16a.
- the breakdown voltage Vb2 in the region in which the storage layer 16b is formed becomes larger than the breakdown voltage Vb1 in the region in which the storage layer 16a is formed. Therefore, in the semiconductor device 100 of this example, the withstand voltage can be increased in the region on the well region 17 side where the withstand voltage is required.
- the breakdown voltage Vb3 in the region where the well region 17 is formed is larger than the breakdown voltage Vb1 and the breakdown voltage Vb2. Further, by sandwiching the base region 14 having a lower impurity concentration than the well region 17 between the storage layer 16b and the well region 17 as described above, the electric field strength can be relaxed and the breakdown voltage Vb2 can be further improved.
- the semiconductor device 100 may be used in combination with the ion implantation method according to the first embodiment and the second embodiment.
- the semiconductor device 100 stores the storage layer 16 using both the method according to the first embodiment in which the semiconductor device 100 is ion-implanted with inclination in the X-axis direction and the method according to the third embodiment with the ion-implantation in the Y-axis direction.
- the method of inclining in the X-axis direction and the method of inclining in the Y-axis direction are separately performed such that the impurity concentration of the storage layer 16 becomes a predetermined value.
- the semiconductor device 100 it is possible to shallowly form the accumulation layer 16 on all the boundary sides in the + X axis direction side, the ⁇ X axis direction side, the + Y axis direction side, and the ⁇ Y axis direction side of the transistor portion 70. In this case, the semiconductor device 100 can improve the withstand voltage in the vicinity of all the boundaries around the transistor unit 70.
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Abstract
Description
特許文献1 特開2012-43890号公報
図1は、実施例1に係る半導体装置100の一例を示す平面図である。本例の半導体装置100は、IGBT(Insulated Gate Bipolar Transistor)等のトランジスタを含むトランジスタ部70、および、FWD(Free Wheel Diode)等のダイオードを含むダイオード部80を有する半導体チップである。また、トランジスタ部70は、平面視において、トランジスタ部70とダイオード部80との境界側に、境界領域75を有する。図1においてはチップ端部周辺のチップのおもて面を示しており、他の領域を省略している。
図3は、比較例1に係る半導体装置500の一例を示す平面図である。図4は、比較例1に係る半導体装置500のb-b'断面の一例を示す。本例の半導体装置500は、領域575においてもエミッタ領域512が形成されている点で、実施例1に係る半導体装置100と異なる。
図5は、実施例2に係る半導体装置100の一例を示す平面図である。図6は、実施例2に係る半導体装置100のc-c'断面の一例を示す図である。本例の半導体装置100は、トランジスタ部70における他の領域との境界側において、エミッタ領域12が形成されていない境界領域75を有する。本例の境界領域75は、半導体装置100のc-c'断面において、エミッタ領域12が形成されていない領域から、エミッタトレンチ部60のトランジスタ部70側の領域までに対応する。本例の半導体装置100は、境界領域75において、半導体基板10のおもて面にベース領域14を有する点で、実施例1に係る半導体装置100と相違する。このように、半導体装置100は、境界領域75における半導体基板10のおもて面において、コンタクト領域15を形成しなくてもよい。
図11は、実施例3に係る半導体装置100の平面図の一例を示す。図12は、実施例3に係る半導体装置100のd-d'断面の一例を示す図である。
Claims (13)
- 半導体基板と、
前記半導体基板に形成された第1導電型のドリフト層と、
前記半導体基板において、前記ドリフト層の上方に形成された第2導電型のベース領域と、
前記ドリフト層と前記ベース領域との間に設けられ、前記ドリフト層よりも高濃度である第1導電型の蓄積層と
を備え、
前記蓄積層は、第1蓄積領域と、平面視における前記蓄積層と異なる領域との境界側において、前記第1蓄積領域よりも浅く形成された第2蓄積領域とを有する
半導体装置。 - 前記半導体基板に形成されたトランジスタ部を備え、
前記トランジスタ部は、
前記半導体基板のおもて面に形成され、予め定められた方向に配列された複数のトレンチ部と、
前記半導体基板のおもて面において、前記複数のトレンチ部の間に形成された前記ドリフト層よりも高濃度である第1導電型のエミッタ領域と
を有し、
前記第1蓄積領域および前記第2蓄積領域は、前記複数のトレンチ部の間に形成される
請求項1に記載の半導体装置。 - 前記トランジスタ部は、前記トランジスタ部の配列方向の一端において、前記複数のトレンチ部の間に前記エミッタ領域が形成されていない境界領域を有する
請求項2に記載の半導体装置。 - 前記トランジスタ部は、前記トランジスタ部の配列方向の一端と、前記一端と反対側の他端との両端において、前記複数のトレンチ部の間に前記エミッタ領域が形成されていない境界領域を有する
請求項2に記載の半導体装置。 - 前記境界領域における前記第2蓄積領域の幅は、前記複数のトレンチ部により囲まれたメサの幅と等しい
請求項3又は4に記載の半導体装置。 - 前記半導体基板は、前記境界領域における前記半導体基板のおもて面に、前記ベース領域よりも高濃度である第2導電型のコンタクト領域を有する
請求項3から5のいずれか一項に記載の半導体装置。 - 前記ドリフト層は、前記境界領域において、前記ベース領域と接続されている
請求項3から6のいずれか一項に記載の半導体装置。 - 前記半導体基板のおもて面と平行な方向において、前記第2蓄積領域の深さが徐々に変化する
請求項3から7のいずれか一項に記載の半導体装置。 - 前記半導体基板に形成されたダイオード部を更に備え、
前記境界領域は、前記トランジスタ部における前記ダイオード部との境界側に形成されている
請求項3から8のいずれか一項に記載の半導体装置。 - 前記第2蓄積領域は、前記ベース領域の深さ方向の中心位置と同一の深さに少なくとも形成された領域を含む
請求項2から9のいずれか一項に記載の半導体装置。 - 前記第2蓄積領域の下端の不純物濃度は、前記第1蓄積領域の下端の不純物濃度よりも低い
請求項2から10のいずれか一項に記載の半導体装置。 - 平面視で前記トランジスタ部が延伸する延伸方向側における前記半導体基板のおもて面に、第2導電型のウェル領域を更に備え、
前記第2蓄積領域は、平面視で、前記蓄積層における前記ウェル領域との境界側に形成される
請求項2から11のいずれか一項に記載の半導体装置。 - 半導体基板と、
前記半導体基板に形成された第1導電型のドリフト層と、
前記半導体基板において、前記ドリフト層の上方に形成された第2導電型のベース領域と、
前記ドリフト層と前記ベース領域との間に設けられ、前記ドリフト層よりも高濃度である第1導電型の蓄積層と、
前記半導体基板のおもて面に形成され、予め定められた配列方向に配列された複数のトレンチ部と
を備え、
前記蓄積層は、前記複数のトレンチ部の配列方向の一端において、第1蓄積領域と、平面視における前記蓄積層と異なる領域との境界側において、前記第1蓄積領域よりも浅く形成された第2蓄積領域とを有する
半導体装置。
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Also Published As
Publication number | Publication date |
---|---|
CN107851666B (zh) | 2021-11-23 |
US11676960B2 (en) | 2023-06-13 |
DE112017000063T5 (de) | 2018-03-22 |
JPWO2017141998A1 (ja) | 2018-06-07 |
CN107851666A (zh) | 2018-03-27 |
US20180158815A1 (en) | 2018-06-07 |
US20230268341A1 (en) | 2023-08-24 |
US20200388611A1 (en) | 2020-12-10 |
JP6614326B2 (ja) | 2019-12-04 |
JP7010275B2 (ja) | 2022-01-26 |
US10770453B2 (en) | 2020-09-08 |
JP2020074396A (ja) | 2020-05-14 |
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