JP2021192447A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2021192447A JP2021192447A JP2021142776A JP2021142776A JP2021192447A JP 2021192447 A JP2021192447 A JP 2021192447A JP 2021142776 A JP2021142776 A JP 2021142776A JP 2021142776 A JP2021142776 A JP 2021142776A JP 2021192447 A JP2021192447 A JP 2021192447A
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Abstract
Description
特許文献1 国際公開第2015/068203号
特許文献2 特開2015−179705号公報
特許文献3 特開平10−107282号公報
0.01<D/(D+G)<0.2
(項目1)
トランジスタ部とダイオード部とを有する半導体装置であって、
前記トランジスタ部と前記ダイオード部とが隣接する領域に形成され、前記トランジスタ部と前記ダイオード部との干渉を防止する境界領域を有し、
前記トランジスタ部および前記ダイオード部は、予め定められた配列方向に配列された複数のトレンチ部を備え、
前記ダイオード部は、半導体基板のおもて面側とは反対側の面に第1導電型のカソード領域を備え、
前記ダイオード部の前記配列方向における幅は、前記トランジスタ部の前記配列方向における幅よりも大きく、
前記カソード領域は、前記配列方向において前記境界領域まで延伸して設けられている
半導体装置。
(項目2)
前記配列方向において、前記ダイオード部の幅が、1500μm以上である
項目1に記載の半導体装置。
(項目3)
複数のトランジスタ部および複数のダイオード部を備え、
前記複数のダイオード部の総面積は、前記複数のトランジスタ部の総面積より大きい
項目1または2に記載の半導体装置。
(項目4)
前記半導体基板の上面の上方に設けられたゲート金属層と、
前記半導体基板の上面の上方に設けられたエミッタ電極と、
前記トランジスタ部において前記半導体基板の上面側に設けられた第1導電型のエミッタ領域と、
前記トランジスタ部において前記半導体基板の上面側に設けられ、前記ゲート金属層と電気的に接続され、前記エミッタ領域と接するゲートトレンチ部と、
前記ダイオード部において前記半導体基板の上面側に設けられ、前記エミッタ電極と電気的に接続されたエミッタトレンチ部とを更に備え、
前記エミッタトレンチ部は、前記トランジスタ部においても、前記ゲートトレンチ部の間に一定の周期で配置されている
項目1から3のいずれか一項に記載の半導体装置。
(項目5)
前記半導体基板の上面側に設けられ、前記ゲート金属層と電気的に接続され、前記エミッタ領域と接していないダミートレンチ部を更に備える
項目4に記載の半導体装置。
(項目6)
前記境界領域は、前記トランジスタ部のデバイス構造とも、前記ダイオード部のデバイス構造とも異なるデバイス構造を有する領域である
項目1から5のいずれか一項に記載の半導体装置。
(項目7)
前記半導体基板の上面側の上方に設けられる層間絶縁膜と、
前記トランジスタ部および前記ダイオード部において、トレンチ部間の前記層間絶縁膜に設けられエミッタ電極が埋め込まれるコンタクトホールとを更に備え、
前記境界領域のトレンチ部間の前記層間絶縁膜には、前記コンタクトホールが設けられていない
項目1から6のいずれか一項に記載の半導体装置。
(項目8)
前記ダイオード部は、前記境界領域と非境界領域とを有し、
前記ダイオード部の前記境界領域における前記カソード領域の濃度は、前記ダイオード部の前記非境界領域における前記カソード領域の濃度よりも高い
項目1から7のいずれか一項に記載の半導体装置。
(項目9)
前記半導体基板の上面側とは反対側に設けられた下面ライフタイムキラーを更に備え、
前記ダイオード部は、前記境界領域と非境界領域とを有し、
前記ダイオード部の前記境界領域における前記下面ライフタイムキラーの濃度は、前記ダイオード部の前記非境界領域における前記下面ライフタイムキラーの濃度よりも低い
項目1から8のいずれか一項に記載の半導体装置。
(項目10)
前記半導体基板の上面側において、少なくとも前記ダイオード部の非境界領域に導入される上面ライフタイムキラーを更に備え、
前記カソード領域は、前記上面ライフタイムキラーよりもトランジスタ部側に延伸して設けられる
項目1から9のいずれか一項に記載の半導体装置。
Claims (11)
- 半導体基板の上面側に設けられ第1方向に延伸する複数のトレンチ部と、複数の前記トレンチ部の間に設けられる複数のメサ部と、少なくとも1つの前記メサ部に設けられた第1導電型のエミッタ領域と、前記半導体基板の上面の上方に設けられたゲート金属層と、前記半導体基板の上面の上方に設けられたエミッタ電極と、前記半導体基板の上面と前記ゲート金属層および前記エミッタ電極との間に介在する層間絶縁膜と、を備える半導体装置であって、
複数の前記メサ部は、
前記第1方向と垂直な第2方向の前記エミッタ領域を通過する断面において、前記層間絶縁膜に設けられたコンタクトホールを介し前記エミッタ電極と接続する第1メサ部と、
前記第1方向と垂直な第2方向の前記エミッタ領域を通過する断面において、前記層間絶縁膜に上面を覆われる第2メサ部と、を含み、
複数の前記トレンチ部は、
前記ゲート金属層と電気的に接続され、前記エミッタ領域に接するゲートトレンチ部と、
前記エミッタ電極と電気的に接続されるエミッタトレンチ部と、
前記ゲート金属層と電気的に接続され、前記エミッタ領域に接しないダミートレンチ部と、を含み、
前記ダミートレンチ部と前記第2メサ部とが隣接して配置されている
半導体装置。 - 前記エミッタ領域は、少なくとも1つの前記第1メサ部に設けられている
請求項1に記載の半導体装置。 - 1以上の第1メサ部と前記第1メサ部に接する前記トレンチ部とを含む第1領域と、
1以上の第2メサ部と前記第2メサ部の間の前記トレンチ部とを含む第2領域と、を備え、
前記第2方向において、前記第1領域の両隣に前記第2領域が配置されている
請求項1または2に記載の半導体装置。 - 前記ダミートレンチ部は、前記第2領域に複数配置されている
請求項3に記載の半導体装置。 - 前記第2領域は、4個以上10個以下の前記第2メサ部を含む
請求項3または4に記載の半導体装置。 - 少なくとも1つの第2メサ部は、前記ダミートレンチ部に挟まれている
請求項5に記載の半導体装置。 - 前記第2領域の前記トレンチ部の半分以上が、前記ダミートレンチ部である
請求項3から6のいずれか1項に記載の半導体装置。 - 前記第2領域は、前記エミッタトレンチ部を含む
請求項3から7のいずれか1項に記載の半導体装置。 - 前記第1領域は、前記ゲートトレンチ部と前記エミッタトレンチ部とを含む
請求項3から8のいずれか1項に記載の半導体装置。 - 前記第1領域の複数の前記トレンチ部は、前記第2方向において、前記ゲートトレンチ部の両隣に前記エミッタトレンチ部が位置するように配置されている
請求項9に記載の半導体装置。 - 前記第1メサ部および前記第2メサ部に設けられた第2導電型のベース領域と、
前記第1メサ部および前記第2メサ部に設けられた、前記半導体基板のドーピング濃度よりも高濃度の第1導電型の蓄積領域と、
を備える請求項1から10のいずれか1項に記載の半導体装置。
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