JP6320808B2 - トレンチmos型半導体装置 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
1a n+フィールドストップ層
2 p型コレクタ層
3a p型チャネル領域
4 n+型エミッタ領域
5 並列トレンチ
6 ゲート絶縁膜
7 ゲート電極
8 層間絶縁膜
9、9a、9b エミッタ電極
10 コレクタ電極
11 等電位面
12 p+コンタクト領域
13 等電位面
14 開口部
15 ユニットセル
20 IGBT
21 メインIGBT
22 センスIGBT
23 センス抵抗
24 ツェナーダイオード
25 MOSFET
30 過電流保護回路
31、32 pウェル領域
50 IGBT
60 プレーナー状のゲート電極
61 絶縁膜
62 分離構造
100 IGBT
102−2 フローティング領域
110 トレンチMOSゲート領域
200 トレンチゲート型IGBT
300 IEGT
Im メイン電流
Is センス電流
Igs 変位電流
Claims (7)
- 第1導電型の半導体基板と、
該半導体基板に形成されたメイン半導体素子部と、
該メイン半導体素子部に並列接続され、相対的に面積比の小さい電流検出用のセンス半導体素子部と、を備え、
前記メイン半導体素子部は、
前記半導体基板の一面側に形成された第2導電型のチャネル領域と、
該チャネル領域の表層に設けられる第1導電型のエミッタ領域と、
前記半導体基板の一面側に並列ストライプ状の平面パターンを有し、前記半導体基板の一面から該エミッタ領域に接して前記チャネル領域の下層の前記半導体基板に達する深さのトレンチと、
該トレンチの内面に絶縁膜を介して充填される導電体と、
該導電体上を覆う層間絶縁膜と、
該層間絶縁膜と前記エミッタ領域の表面に共通に接触するエミッタ電極と、
を備え、
前記センス半導体素子部は、
前記半導体基板の一面側に形成された第2導電型の第2のチャネル領域と、
該チャネル領域の表層に設けられる第1導電型のエミッタ領域と、
前記半導体基板の一面側に並列ストライプ状の平面パターンを有し、前記半導体基板の一面から該エミッタ領域に接して前記チャネル領域の下層の前記半導体基板に達する深さのトレンチと、
該トレンチの内面に絶縁膜を介して充填される導電体と、
該導電体上を覆う層間絶縁膜と、
該層間絶縁膜と前記エミッタ領域の表面に共通に接触するエミッタ電極と、
を備え、
前記メイン半導体素子部では、前記並列ストライプ状のトレンチ間の前記半導体基板の表面に、複数の前記エミッタ領域が、前記トレンチの長手方向に所定の間隔で繰り返す構造を有しており、
前記電流検出用のセンス半導体素子部では、前記並列ストライプ状のトレンチ間の前記半導体基板に前記第2のチャネル領域を有し、該第2のチャネル領域を挟んで複数の前記エミッタ領域が前記トレンチの長手方向に所定の間隔で繰り返す構造を有しており、
前記メイン半導体素子部と前記センス半導体素子部とは、前記エミッタ領域の前記トレンチの長手方向に繰り返す前記間隔および該エミッタ領域の平面形状が同じであって、且つ、
前記メイン半導体素子部と前記センス半導体素子部とは、前記トレンチの長手方向における前記並列ストライプ状のトレンチ間の表面パターンに差異を有し、該表面パターンの差異として、前記メイン半導体素子部の表面パターンでは第1導電型の領域が配置されるところに、前記センス半導体素子部では、該第1導電型の領域が配置されるよりもオン電圧が高くなる前記第2のチャネル領域が配置されていて、
前記センス半導体素子部では、前記第2のチャネル領域が前記トレンチの長手方向における前記並列ストライプ状のトレンチ間にわたって設けられていて、
前記センス半導体素子部の帰還容量が前記メイン半導体素子部の帰還容量よりも小さいことを特徴とするトレンチMOS型半導体装置。 - 前記メイン半導体素子部と前記センス半導体素子部の活性領域面積比が100〜10000であることを特徴とする請求項1に記載のトレンチMOS型半導体装置。
- 前記メイン半導体素子部と前記センス半導体素子部とは、前記トレンチの幅方向では、該トレンチを挟んで前記エミッタ領域が該トレンチの長手方向にずれて分散配置されていることを特徴とする請求項1または2に記載のトレンチMOS型半導体装置。
- 前記センス半導体素子部領域を取り囲むように、
前記メイン半導体素子部のエミッタ電極に接続される第2導電型ウェル領域と、
前記センス半導体素子部のエミッタ電極に接続される第2導電型第2のウェル領域と、を備えることを特徴とする請求項1〜3のいずれか一項に記載のトレンチMOS型半導体装置。 - 前記メイン半導体素子部と前記センス半導体素子部が離間する離間部を有し、
該離間部の前記半導体基板の一面側は前記半導体基板が露出することを特徴とする請求項1〜4のいずれか一項に記載のトレンチMOS型半導体装置。 - 前記離間部の長さが25μm以上30μm以下であることを特徴とする請求項5に記載の半導体装置。
- トレンチMOS型半導体装置が絶縁ゲートバイポーラトランジスタまたは電界効果型トランジスタであることを特徴とする請求項1〜6のいずれか一項に記載のトレンチMOS型半導体装置。
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JP2014055728A JP6320808B2 (ja) | 2014-03-19 | 2014-03-19 | トレンチmos型半導体装置 |
US14/622,822 US9748370B2 (en) | 2014-03-19 | 2015-02-13 | Trench MOS semiconductor device |
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WO2016098409A1 (ja) * | 2014-12-19 | 2016-06-23 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6597090B2 (ja) | 2015-09-11 | 2019-10-30 | 株式会社デンソー | 内燃機関用のスパークプラグ及びその製造方法 |
JP6588363B2 (ja) * | 2016-03-09 | 2019-10-09 | トヨタ自動車株式会社 | スイッチング素子 |
JP2018022776A (ja) * | 2016-08-03 | 2018-02-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6805620B2 (ja) * | 2016-08-10 | 2020-12-23 | 富士電機株式会社 | 半導体装置 |
US10103140B2 (en) * | 2016-10-14 | 2018-10-16 | Alpha And Omega Semiconductor Incorporated | Switch circuit with controllable phase node ringing |
JP6930858B2 (ja) * | 2017-05-24 | 2021-09-01 | 株式会社東芝 | 半導体装置 |
DE112018006404T5 (de) | 2017-12-14 | 2020-09-03 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
CN107942615B (zh) * | 2017-12-22 | 2024-03-22 | 江苏宏微科技股份有限公司 | 一种电动汽车用igbt或mosfet版图结构 |
CN108899319B (zh) * | 2018-08-30 | 2024-01-26 | 赵少峰 | 一种增加vdmos沟道密度的布图结构和布图方法 |
JP7101593B2 (ja) * | 2018-10-30 | 2022-07-15 | 三菱電機株式会社 | 半導体装置 |
JP7099546B2 (ja) | 2018-12-19 | 2022-07-12 | 富士電機株式会社 | 半導体装置 |
DE112019007210T5 (de) * | 2019-04-10 | 2021-12-30 | Mitsubishi Electric Corporation | Halbleitervorrichtung |
KR102153550B1 (ko) * | 2019-05-08 | 2020-09-08 | 현대오트론 주식회사 | 전력 반도체 소자 |
JP2021034726A (ja) * | 2019-08-13 | 2021-03-01 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP2021136241A (ja) * | 2020-02-21 | 2021-09-13 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP7508906B2 (ja) | 2020-07-09 | 2024-07-02 | 富士電機株式会社 | 電子回路及び半導体モジュール |
JP7459703B2 (ja) * | 2020-07-15 | 2024-04-02 | 富士電機株式会社 | 半導体装置 |
CN113257902B (zh) * | 2021-06-10 | 2021-09-21 | 南京晟芯半导体有限公司 | 一种具有抑制振荡效果的igbt器件及其制造方法 |
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JP3361874B2 (ja) | 1994-02-28 | 2003-01-07 | 三菱電機株式会社 | 電界効果型半導体装置 |
JP3156487B2 (ja) * | 1994-03-04 | 2001-04-16 | 富士電機株式会社 | 絶縁ゲート型バイポーラトランジスタ |
JP3226075B2 (ja) | 1994-06-22 | 2001-11-05 | 富士電機株式会社 | たて型mos半導体装置 |
JP3349029B2 (ja) * | 1996-01-16 | 2002-11-20 | 株式会社東芝 | 半導体装置 |
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JP4581179B2 (ja) | 2000-04-26 | 2010-11-17 | 富士電機システムズ株式会社 | 絶縁ゲート型半導体装置 |
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WO2011111500A1 (ja) | 2010-03-09 | 2011-09-15 | 富士電機システムズ株式会社 | 半導体装置 |
JP5779025B2 (ja) | 2010-11-08 | 2015-09-16 | 株式会社東芝 | 半導体装置 |
JP2015176927A (ja) * | 2014-03-13 | 2015-10-05 | 株式会社東芝 | 半導体装置および絶縁ゲート型バイポーラトランジスタ |
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