WO2016098409A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- WO2016098409A1 WO2016098409A1 PCT/JP2015/076122 JP2015076122W WO2016098409A1 WO 2016098409 A1 WO2016098409 A1 WO 2016098409A1 JP 2015076122 W JP2015076122 W JP 2015076122W WO 2016098409 A1 WO2016098409 A1 WO 2016098409A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
- Patent Document 1 Japanese Patent Laid-Open No. 2007-324539 Patent Document 2 Japanese Patent Laid-Open No. 2011-243946
- the wiring part can be reliably connected to the gate electrode. Moreover, it is preferable that it is a shape which other structures, such as a channel layer, are easy to form.
- the semiconductor device includes at least one of a mesa portion, a floating portion, a trench, an electrode, and an outer wiring portion.
- the mesa portion may be formed on the surface side of the semiconductor substrate.
- the floating part may be formed on the surface side of the semiconductor substrate.
- the trench may be formed surrounding the floating part.
- the trench may separate the mesa portion and the floating portion.
- the electrode may be formed in the trench.
- the outer wiring portion may be formed along the arrangement direction of the mesa portion and the floating portion outside the region surrounded by the trench.
- the mesa part of the outer wiring part and the end side on the floating part side may have a protruding part and a concave part.
- the protruding portion may be formed in at least a part of the region facing the floating portion.
- the protruding portion may protrude toward the floating portion beyond the trench.
- the concave portion may be formed in at least a part of a region facing the mesa portion.
- the recessed portion may be recessed on the outer wiring portion side than the protruding portion.
- the semiconductor device may further include a well region.
- the well region may be of the second conductivity type.
- the well region may be formed between the end portion of the semiconductor substrate and the mesa portion and the floating portion.
- the mesa portion may have a second conductivity type base region.
- the base region and the well region may be connected.
- the base region may be formed using the outer wiring portion as a mask after the well region is formed.
- the concave portion may be recessed toward the outer wiring portion to a position where the base region can be connected to the well region.
- the tip of the concave portion may be arranged on the outer wiring portion side from the position protruding from the end of the well region toward the inside of the mesa portion by 0.75 times the depth of the base region.
- the tip of the recess may be arranged on the outer wiring part side than the trench.
- the floating portion has the second conductivity type, and the second conductivity type region in the floating portion covered by the protruding portion may be connected to the trench.
- the floating portion may be formed using the outer wiring portion as a mask after the trench is formed.
- the protruding portion may have a length that allows the second conductivity type region of the floating portion to be connected to the trench below the protruding portion.
- the length of the region of the protruding portion that overlaps the floating portion may be 0.75 times or less the depth of the floating portion.
- the width of the protruding portion may be smaller than the width of the floating portion.
- the width of the recess may be larger than the width of the mesa portion.
- a trench surrounding a predetermined region on the surface side of the semiconductor substrate may be formed.
- a floating part surrounded by the trench and a mesa part separated from the floating part may be formed.
- an electrode may be formed in the trench, and an outer wiring portion along the arrangement direction of the mesa portion and the floating portion may be formed outside the region surrounded by the trench.
- impurities of a predetermined conductivity type may be doped and diffused in the mesa portion and the floating portion using the outer wiring portion as a mask.
- the protruding portion and the concave portion may be formed on the edge of the outer wiring portion on the mesa portion and the floating portion side.
- the protruding portion may be disposed in at least a part of the region facing the floating portion.
- the protruding portion may protrude toward the floating portion beyond the trench.
- the concave portion may be disposed in at least a part of a region facing the mesa portion.
- the recessed portion may be recessed on the outer wiring portion side than the protruding portion.
- the semiconductor substrate may have the first conductivity type.
- the well region of the second conductivity type may be formed between the end portion of the semiconductor substrate, the mesa portion, and the floating portion before the step of forming the trench.
- the base region connected to the well region may be formed in the mesa portion by doping and diffusing the impurity of the second conductivity type.
- the second conductivity type region in the floating portion covered with the protruding portion may be connected to the trench by doping and diffusing the impurity of the second conductivity type.
- FIG. 1 is a plan view showing an example of a semiconductor device 100.
- FIG. FIG. 2 shows a cross section AA ′ in FIG.
- the BB 'cross section in FIG. 1 is shown.
- the CC 'cross section in FIG. 1 is shown.
- 6 is a diagram illustrating another configuration example of the semiconductor device 100.
- FIG. FIG. 6 shows a cross section taken along the line AA ′ in FIG. 6 is a diagram illustrating an example in which the position of the tip of the recess 54 in the y direction matches the position of the end of the trench 20 on the outer wiring portion 50 side.
- FIG. 2 is a diagram showing an outline of a manufacturing process of the semiconductor device 100.
- FIG. The cross section of the semiconductor device 100 in each process of a manufacturing process is shown.
- FIG. It is a figure which shows the protrusion part 52 and the recessed part 54.
- FIG. It is a figure which shows the semiconductor device 300 as a comparative example. 4 shows a cross section taken along the line AA ′ of the semiconductor device 300.
- FIG. It is a figure which shows the semiconductor device 400 as a comparative example. 6 shows a cross section taken along the line AA ′ of the semiconductor device 400.
- FIG. It is the figure which compared the turn-off current characteristic of the semiconductor device 100 shown in FIG. 1, and the semiconductor device 400 shown in FIG. It is a figure which shows the relationship between the ON voltage Von of the semiconductor device 100, and the turn-off loss Eoff. 6 is a plan view illustrating another example of the semiconductor device 100.
- FIG. 18 shows a DD ′ cross section in FIG.
- FIG. 1 is a plan view showing an example of the semiconductor device 100.
- the semiconductor device 100 of this example is a semiconductor chip. In FIG. 1, the chip surface around the chip end is shown, and other regions are omitted.
- the semiconductor device 100 includes a semiconductor substrate 110, a plurality of floating parts 10, a plurality of trenches 20, a plurality of mesa parts 30, and an outer wiring part 50.
- the plurality of floating portions 10, the plurality of trenches 20, the plurality of mesa portions 30, and the outer wiring portion 50 are formed on the surface side of the semiconductor substrate 110.
- the plurality of mesa units 30 and the plurality of floating units 10 are arranged along a predetermined arrangement direction.
- the mesa portions 30 and the floating portions 10 are alternately arranged along the x direction parallel to a predetermined side of the semiconductor substrate 110.
- the mesa unit 30 and the floating unit 10 have a longitudinal direction in the y direction perpendicular to the x direction.
- the shape of the floating part 10 on the surface of the semiconductor substrate 110 is, for example, an ellipse whose longitudinal direction is the y direction, or a rectangle whose apex is rounded into an arc.
- the mesa unit 30 is formed between the plurality of floating units 10 that are spaced apart in the x direction.
- the trench 20 is provided for each floating part 10.
- Each trench 20 is formed to surround the corresponding floating portion 10 on the surface of the semiconductor substrate 110. Thereby, the mesa part 30 and the floating part 10 isolate
- An electrode is formed inside the trench 20.
- An insulating film is formed between the inner wall of the trench 20 and the electrode.
- the electrode of this example functions as a gate electrode in a power semiconductor element having a trench gate structure, for example.
- a base region 34, an emitter region 36 and a buried region 32 are formed.
- the emitter region 36 is formed on the surface of the mesa unit 30.
- the emitter region 36 has a first conductivity type and is connected to an emitter electrode formed on the surface side of the semiconductor substrate 110.
- Base region 34 has a second conductivity type different from the first conductivity type, and is formed between emitter region 36 and a drift region formed on the back side of emitter region 36.
- the first conductivity type will be described as N-type
- the second conductivity type will be described as P-type.
- the first and second conductivity types may be opposite conductivity types.
- the semiconductor substrate 110 is N-type.
- the drift region has the same conductivity type as that of the semiconductor substrate 110.
- the emitter region 36 is N + type and the base region 34 is P ⁇ type.
- a channel is formed along the depth direction in accordance with the voltage applied to the gate electrode formed inside the trench 20.
- the buried region 32 is P + type and is formed between the base region 34 and the emitter region 36. A part of the buried region 32 may be exposed to the surface of the mesa portion 30 through an opening formed in the emitter region 36 and connected to the emitter electrode. With such a configuration, an active portion of a power semiconductor element such as an IGBT is formed in the mesa portion 30.
- an N + type emitter region is not formed, but a P ⁇ type region is formed.
- the area of the emitter region 36 connected to the emitter electrode can be reduced, the carriers flowing through the emitter electrode can be restricted, and the carriers can be accumulated on the surface side of the drift layer. Thereby, the ON voltage can be lowered.
- an interlayer insulating film is formed on the surface of the floating portion 10.
- the floating portion 10 may be formed with a contact portion 12 that penetrates the interlayer insulating film.
- the contact portion 12 is, for example, a P + type semiconductor region, and connects the P ⁇ type region of the floating portion 10 and the emitter electrode.
- the sheet resistance of the floating portion 10 can be controlled.
- the di / dt characteristic that is, the slope of the current change
- the outer wiring portion 50 is formed along the arrangement direction of the mesa portion 30 and the floating portion 10 (x direction in this example) outside the region surrounded by the trench 20.
- the outer wiring part 50 may not be formed strictly in parallel with the arrangement direction. “Formed along the arrangement direction” means that the outer wiring portion 50 has a portion facing the at least one mesa portion 30 and a portion facing the at least one floating portion 10.
- the outer wiring part 50 is electrically connected to a gate electrode formed inside the trench 20.
- the outer wiring portion 50 and the gate electrode are made of, for example, polysilicon.
- the outer wiring part 50 may be formed in an annular shape along the outer periphery of the semiconductor substrate 110.
- the end of the outer wiring part 50 on the side of the mesa part 30 and the floating part 10 has a protrusion 52 and a recess 54.
- the protruding portion 52 is formed in at least a part of the region facing the floating portion 10 on the end side of the outer wiring portion 50, and protrudes beyond the trench 20 to the floating portion 10 side.
- a portion of the protrusion 52 that overlaps the trench 20 is connected to a gate electrode formed inside the trench 20. Thereby, a gate voltage for driving the semiconductor element can be applied to the gate electrode.
- the protruding portion 52 protrudes toward the floating portion 10, the outer wiring portion 50 and the gate electrode can be reliably connected even if the length of the protruding portion 52 varies from the design value due to manufacturing variations or the like. .
- the concave portion 54 is formed in at least a part of a region facing the mesa portion 30 on the end side of the outer wiring portion 50, and is formed so as to be recessed inside the outer wiring portion 50 relative to the protruding portion 52.
- the concave portion 54 is formed over the entire region facing the mesa portion 30 at least at the edge of the outer wiring portion 50.
- the recess 54 of this example is formed in the entire region facing the mesa unit 30 and in a part of the region facing the floating unit 10 adjacent to the mesa unit 30. Thereby, the base region 34 or the like that functions as a channel can be easily formed during manufacturing.
- a P + type well region 56 is formed between the end of the semiconductor substrate 110 and the mesa unit 30 and the floating unit 10.
- the well region 56 may be formed in an annular shape along the outer periphery of the semiconductor substrate 110.
- the well region 56 functions as a breakdown voltage structure that relaxes electric field concentration at the end of the semiconductor substrate 110 and improves breakdown voltage.
- the well region 56 is formed by doping impurities on the surface of the semiconductor substrate 110 using a predetermined mask.
- the end of the mask is indicated by a broken line 58.
- a region inside the semiconductor substrate 110 with respect to the broken line 58 is covered with a mask to dope impurities.
- the well region 56 is formed to the inside of the broken line 58 by thermal diffusion or the like.
- FIG. 2 to 4 are diagrams showing an example of a cross section of the semiconductor device 100.
- FIG. FIG. 2 shows an AA ′ cross section in FIG.
- FIG. 3 shows a BB ′ cross section in FIG.
- FIG. 4 shows a CC ′ cross section in FIG. 2 to 4, the interlayer insulating film and the emitter electrode formed on the surface side of the semiconductor substrate 110 are omitted.
- the semiconductor substrate 110 includes, in order from the surface side, a P ⁇ type base region 34, an N ⁇ type drift region 112, an N + type buffer region 114, and a P + type collector region. 116 is formed.
- the buffer area 114 may function as a field stop layer.
- a collector electrode 120 is formed on the back side of the collector region 116.
- a P + type well region 56 is formed at the end of the semiconductor substrate 110.
- an emitter region 36 doped with N-type impurities is formed on the surface side of the base region 34.
- a buried region 32 may be formed between the emitter region 36 and the base region 34.
- the base region 34 in which the N-type impurity remains without being diffused is formed between the drift region 112 and the emitter region 36.
- a voltage is applied to the gate electrode 22
- a channel is formed in a portion of the base region 34 along the trench 20.
- the trench 20 is formed deeper than the base region 34.
- the base region 34 is formed using the outer wiring portion 50 as a mask.
- the thermal history of the base region 34 functioning as a channel can be reduced. For this reason, it is possible to prevent the base region 34 from being excessively diffused in the depth direction. Therefore, the channel depth can be controlled with high accuracy.
- the outer wiring portion 50 has a protruding portion 52 that protrudes to the floating portion 10 side across the trench 20. For this reason, the outer wiring part 50 can be reliably connected to the gate electrode 22.
- the base region 34 formed in the mesa unit 30 is preferably connected to the well region 56. If the base region 34 does not reach the well region 56, the N ⁇ type region of the semiconductor substrate 110 is exposed on the surface. In this case, the electric field concentrates on the portion, and the withstand voltage decreases.
- the outer wiring portion 50 of this example has a recess 54 in a region facing the mesa portion 30 as shown in FIG. Therefore, even if the base region 34 is formed using the outer wiring portion 50 as a mask, the base region 34 and the well region 56 in the mesa portion 30 can be connected as shown in FIG.
- the concave portion 54 of the outer wiring portion 50 is recessed outside the semiconductor substrate 110 to a position where the base region 34 in the mesa portion 30 can be connected to the well region 56 when the base region 34 is formed using the outer wiring portion 50 as a mask. Preferably it is. According to the semiconductor device 100 of the present example, it is possible to ensure the breakdown voltage by connecting the base region 34 and the well region 56 of the mesa unit 30 while securely connecting the outer wiring unit 50 and the gate electrode 22.
- the base region 34 on the surface side of the floating part 10 is also preferably connected to the trench 20.
- a part of the floating part 10 is covered with the protruding part 52.
- the length L1 in this example, the length protruding in the y direction
- the length it is preferable that the length be such that P-type impurities can diffuse up to the trench 20 below the protrusion 52.
- the distance in which an impurity region having a predetermined depth D is diffused in the horizontal direction is 0.75 ⁇ D.
- the length L1 at which the protruding portion 52 protrudes inside the floating portion 10 is D1 ⁇ 0.75 or less, where the depth of the base region 34 is D1.
- the width of the protrusion 52 (in this example, the width in the x direction) is preferably smaller than the width of the floating portion 10. Accordingly, when the base region 34 is formed using the outer wiring portion 50 as a mask, impurities implanted from both sides of the protruding portion 52 can also be diffused to the lower side of the protruding portion 52, so that the region covered by the protruding portion 52 is formed. Impurities are easily diffused. Further, the width of the recess 54 is preferably larger than the width of the mesa portion 30.
- FIG. 5 is a diagram illustrating another configuration example of the semiconductor device 100.
- the semiconductor device 100 of this example is different in the shape of the outer wiring portion 50 from the semiconductor device 100 shown in FIG.
- Other structures may be the same as those of the semiconductor device 100 shown in FIG.
- the cross section at the position BB ′ shown in FIG. 5 has the structure shown in FIG.
- the tip of the concave portion 54 in the y direction is provided on the inner side of the semiconductor substrate 110 than the concave portion 54 shown in FIG.
- FIG. 6 shows an AA ′ cross section in FIG.
- the base region 34 in the mesa unit 30 is preferably connected to the well region 56. Therefore, the recess 54 of the outer wiring portion 50 used as a mask for forming the base region 34 is preferably formed at a position where the P-type impurity in the base region 34 can diffuse to the end of the well region 56.
- the tip of the recess 54 in the y direction is located on the outer side of the position protruding from the end of the well region 56 in the y direction toward the inside of the mesa 30 by 0.75 times the depth of the base region 34.
- the length L2 of the recess 54 that protrudes in the y direction from the end of the well region 56 is preferably equal to or less than D2 ⁇ 0.75, where the depth of the base region 34 is D2.
- the tip of the recess 54 may be closer to the outer wiring part 50 than the end of the well region 56. That is, the well region 56 may be exposed on the y direction side with respect to the tip of the recess 54. Further, the tip of the recess 54 may be disposed on the outer wiring part 50 side with respect to the trench 20. Since the well region 56 is formed in a range that can be connected to at least the trench 20, the base region 34 can be connected to the well region 56 if the recess 54 is disposed on the outer wiring portion 50 side of the trench 20.
- the outer wiring portion 50 is made smaller, and the distance from the mesa portion 30 and the floating portion 10 to the end portion of the semiconductor substrate 110 is made smaller. be able to. Thereby, the semiconductor device 100 can be reduced in size.
- the tip of the concave portion 54 is disposed inside the semiconductor substrate 110 as much as possible.
- the position of the tip of the recess 54 in the y direction is between the position of the end of the trench 20 on the outer wiring part 50 side and the position protruding by D2 ⁇ 0.75 from the end of the well region 56 in the y direction. It may be. Further, the position of the tip of the recess 54 in the y direction protrudes from the position of the end of the mask forming the base region 34 (ie, the broken line 58) by D2 ⁇ 0.75 from the end of the well region 56 in the y direction. It may be between up to the position. The position of the tip of the recess 54 in the y direction may be between the end of the well region 56 and a position protruding by D2 ⁇ 0.75 from the end of the well region 56 in the y direction.
- FIG. 7 is a diagram illustrating an example in which the position of the tip of the recess 54 in the y direction matches the position of the end of the trench 20 on the outer wiring portion 50 side. As described above, the tip of the recess 54 extends from the position shown in FIG. 7 to a position protruding by D2 ⁇ 0.75 from the end of the well region 56 shown in FIGS. 5 and 6 in the y direction. It may be.
- FIG. 8 and 9 are diagrams showing an example of the manufacturing process of the semiconductor device 100.
- FIG. FIG. 8 shows an outline of the manufacturing process
- FIG. 9 shows a cross section of the semiconductor device 100 in each process.
- a P + type well region 56 is formed on the outer peripheral portion of the surface of the N ⁇ type semiconductor substrate 110 (S200).
- the semiconductor substrate 110 is, for example, a silicon substrate.
- the position of the end of the well region 56 in the y direction is matched with the position where the trench 20 is to be formed.
- the trench 20 surrounding the region corresponding to the floating portion 10 is formed (S202). 9, in S200, the trench 20 is formed so that the end region on the outer wiring portion 50 side of the trench 20 overlaps the end portion of the well region 56 in the y direction. .
- the trench 20 is formed with a depth that does not reach the buffer region 114 formed on the back side of the semiconductor substrate 110.
- the trench 20 may be formed shallower than the well region 56.
- the gate electrode 22 and the outer wiring part 50 (including the protruding part 52 and the recessed part 54) in the trench 20 are formed (S204).
- the outer wiring portion 50 is formed along the arrangement direction of the mesa portion 30 and the floating portion 10 outside the region surrounded by the trench 20. Further, the protruding portion 52 protrudes closer to the floating portion 10 than the trench 20.
- P-type impurities are doped and diffused in the mesa portion 30 and the floating portion 10 using the outer wiring portion 50 as a mask (S206).
- S206 using the outer wiring portion 50 as a mask, P-type impurities are ion-implanted and thermally diffused over the entire surface side of the semiconductor substrate 110.
- the base region 34 is formed.
- the base region 34 is formed shallower than the trench 20.
- the thermal history of the base region 34 is reduced to reduce the base region 34. Depth can be controlled accurately. Further, by providing the protrusions 52, the connection between the outer wiring part 50 and the gate electrode 22 can be ensured, while the recesses 54 are provided to connect the base region 34 and the well region 56.
- N-type impurities are ion-implanted from the surface side of the semiconductor substrate 110 using a mask having a predetermined shape to form an emitter region 36 in the base region 34 of the mesa portion 30. Further, a structure on the surface side of the semiconductor substrate 110 such as an interlayer insulating film and an emitter electrode is formed. An opening of the contact portion 12 may be formed in the interlayer insulating film.
- selenium is ion-implanted from the back surface side of the semiconductor substrate 110 at a rate of, for example, about 1 ⁇ 10 14 / cm 2 .
- the buffer region 114 is formed by performing a heat treatment at a temperature of about 900 ° C. for about 2 hours. Further, the N ⁇ type region remaining without the buffer region 114 being formed becomes the drift region 112.
- selenium having a large diffusion coefficient a deep buffer region 114 can be formed as compared with, for example, phosphorus.
- the buffer region 114 may be formed by ion implantation of protons (H +) multiple times with different doses instead of selenium ion implantation.
- the impurity concentration of the buffer region 114 has a distribution that gradually increases from the drift region 112 side to the collector region 116 side.
- P-type impurities are ion-implanted from the back surface side of the semiconductor substrate 110 at a dose of 1.0 ⁇ 10 13 / cm 2 to 4.0 ⁇ 10 13 / cm 2 , for example.
- a collector region 116 thinner than the buffer region 114 is formed.
- a collector electrode is formed on the back side of the semiconductor substrate 110.
- the semiconductor substrate 110 is grind
- FIG. 10 is a diagram showing the protrusion 52 and the recess 54.
- the length L1 of the region overlapping the floating portion 10 is preferably 0.75 times or less the depth D1 of the base region 34 of the floating portion 10 as described above.
- the length L1 is 1.5 ⁇ m to 2.5 ⁇ m.
- the width W of the protruding portion 52 is smaller than the width of the floating portion 10.
- the protrusion 52 has a width that can be stably connected to the gate electrode 22.
- the width W is 4 ⁇ m to 8 ⁇ m.
- the distance Lb between the end of the mask for forming the well region 56 and the end of the trench 20 is, for example, 5.5 ⁇ m to 7.5 ⁇ m. This distance corresponds to the distance that the well region 56 diffuses in the horizontal direction. Thereby, the well region 56 and the floating part 10 can be separated by the trench 20.
- the contact portion 12 shown in FIG. 1 may have a rectangular shape with one side ranging from 3.5 ⁇ m to 5.5 ⁇ m. Further, the plurality of contact portions 12 provided in the same floating portion 10 may be arranged at a pitch of 500 ⁇ m to 700 ⁇ m.
- the width ratio of the mesa unit 30 and the floating unit 10 may be 1: 3 to 1: 5.
- the difference between the depth of the trench 20 and the depth of the base region 34 may be 0.5 ⁇ m to 2 ⁇ m.
- FIG. 11 is a diagram showing a semiconductor device 300 as a comparative example.
- the semiconductor device 300 of this example includes an outer wiring portion 350 having a constant width in the y direction. Other configurations may be the same as those of the semiconductor device 100 shown in FIG.
- the outer wiring portion 350 is provided so as to cover a part of the floating portion 10 beyond the trench 20, similarly to the protruding portion 52. However, since the outer wiring portion 350 does not have a recess, the mesa portion 30 is also covered to the same extent as the floating portion 10.
- FIG. 12 shows an AA ′ cross section of the semiconductor device 300.
- the base region 34 is formed using the outer wiring portion 350 shown in FIG. 11 as a mask, the base region 34 of the mesa portion 30 cannot diffuse to the end of the well region 56 as shown in FIG. For this reason, an N ⁇ type region is exposed on the surface of the semiconductor substrate 110, and the breakdown voltage is reduced.
- the semiconductor device 100 since the semiconductor device 100 has the recess 54, the base region 34 of the mesa portion 30 can be diffused to the end of the well region 56, and the breakdown voltage can be maintained.
- FIG. 13 is a diagram showing a semiconductor device 400 as a comparative example.
- the semiconductor device 400 of this example has a so-called full trench structure and does not have a floating portion.
- the trench 420 separates the plurality of mesa portions 430.
- Each mesa portion 430 has a P ⁇ type base region 434, a P + type buried region 432, and an N ⁇ type emitter region 436.
- FIG. 14 shows an AA ′ cross section of the semiconductor device 400.
- the well region 456 and the base region 434 are formed before the trench 420 is formed. Then, the trench 420, the gate electrode 422, and the outer wiring portion 450 are formed. Therefore, although the well region 456 and the base region 434 can be connected, the base region 434 functioning as a channel diffuses in the depth direction in the process of forming the trench 20 and the outer wiring portion 450, and the channel The depth of the can not be accurately controlled.
- the semiconductor device 100 can connect the well region 56 and the base region 34 even if the base region 34 is formed after the outer wiring portion 50 is formed. For this reason, it is possible to prevent the base region 34 from diffusing in the depth direction.
- FIG. 15 is a diagram comparing the turn-off current characteristics of the semiconductor device 100 shown in FIG. 1 and the semiconductor device 400 shown in FIG.
- the horizontal axis represents time
- the vertical axis represents the current flowing through the semiconductor device 400.
- the semiconductor device 100 has a short tail current flowing period and can be switched at high speed.
- the semiconductor device 400 does not have a floating portion, the gate capacitance is large and the period during which the tail current flows is long.
- FIG. 16 is a diagram illustrating a relationship between the on-voltage Von of the semiconductor device 100 and the turn-off loss Eoff. Further, the relationship between the ON voltage Von of the semiconductor device 400 and the turn-off loss Eoff is shown as a comparison. Since the semiconductor device 100 has a width ratio of the mesa portion 30 and the floating portion 10 in a range of 1: 3 to 1: 5, and a depth difference between the trench 20 and the base region 34 is in a range of 0.5 ⁇ m to 2 ⁇ m. In addition, the turn-off loss can be reduced by reducing the gate capacitance, and the ON voltage can be reduced by the electron injection promoting effect.
- FIG. 17 is a plan view showing another example of the semiconductor device 100.
- the semiconductor device 100 of this example is different in structure between two trenches 20 from any one of the semiconductor devices 100 shown in FIGS.
- the other structure may be the same as that of any one of the semiconductor devices 100 shown in FIGS.
- FIG. 17 the case where the outer side wiring part 50 has the shape of FIG. 1 is shown.
- a mesa portion 30, a dummy trench 60, and a mesa portion 30 are provided in order between two trenches 20.
- Each mesa unit 30 may have the same structure as the mesa unit 30 of the semiconductor device 100 shown in FIG. However, the dummy trench 60 is disposed between the two mesa portions 30.
- the dummy trench 60 may be arranged at the center of the two trenches 20 on both sides.
- the dummy trench 60 may be arranged in parallel with the two trenches 20 on both sides.
- the dummy trench 60 of this example has a longitudinal direction in the y direction.
- An electrode is formed inside the dummy trench 60.
- An insulating film is formed between the inner wall of the dummy trench 60 and the electrode.
- the electrode in the dummy trench 60 of this example is electrically connected to, for example, an emitter electrode in a power semiconductor element having a trench gate structure.
- the semiconductor device 100 includes a connection portion 80 that electrically connects the emitter electrode and the internal electrode of the dummy trench 60.
- the connection part 80 is provided, for example, at the end of the dummy trench 60 on the outer wiring part 50 side.
- Connection portion 80 may have a dummy trench wiring portion that is electrically connected to the internal electrode of dummy trench 60 and a contact hole that electrically connects the dummy trench wiring portion and the emitter electrode.
- the connection part 80 may be provided in the area of the recess 54.
- the dummy trench wiring portion may be formed in a region not in contact with the outer wiring portion 50 in the same layer as the outer wiring portion 50. Further, the dummy trench wiring part may be formed of the same material as that of the outer wiring part 50. The dummy trench wiring part is formed of, for example, polysilicon.
- the contact hole described above is provided through the interlayer insulating film on the surface of the semiconductor device 100.
- the end portion of the dummy trench 60 may be provided at the same position as the end portion of the trench 20 in the y direction. Further, the end portion of the dummy trench 60 may reach the well region 56 on the surface of the semiconductor device 100 and may be formed inside the base region 34.
- the end portion of the dummy trench 60 may protrude toward the concave portion 54 of the outer wiring portion 50 from the end portion of the trench 20 in the y direction. However, the dummy trench 60 does not contact the outer wiring part 50. In the example shown in FIG. 5 or 7, the end of the dummy trench 60 is provided closer to the emitter region 36 than the end of the trench 20.
- FIG. 18 shows a DD ′ cross section in FIG. In FIG. 18, the interlayer insulating film and the emitter electrode formed on the surface side of the semiconductor substrate 110 are omitted.
- the semiconductor device 100 of this example is provided with the mesa portion 30, the dummy trench 60, and the mesa portion 30 between the two trenches 20.
- the dummy trench 60 is provided between the two trenches 20 so as to separate the two mesa portions 30.
- the dummy trench 60 is provided so as to penetrate the base region 34 and reach the drift region 112.
- An electrode 62 is formed inside the dummy trench 60 via an insulating film. The electrode 62 is electrically connected to the emitter electrode described above.
- the dummy trench 60 may be formed by the same process as the trench 20.
- the dummy trench 60 may have a width in the x direction larger than that of the trench 20. In this case, the IE effect can be further enhanced.
- the relatively large dummy trench 60 is formed by the same process as the trench 20, the dummy trench 60 is formed to a position deeper than the trench 20.
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Abstract
Description
[先行技術文献]
[特許文献]
特許文献1 特開2007-324539号公報
特許文献2 特開2011-243946号公報
Claims (15)
- 半導体基板の表面側に形成されたメサ部と、
前記半導体基板の表面側に形成されたフローティング部と、
前記フローティング部を囲んで形成され、前記メサ部と前記フローティング部とを分離するトレンチと、
前記トレンチ内に形成された電極と、
前記トレンチが囲む領域の外側において、前記メサ部と前記フローティング部の配列方向に沿って形成された外側配線部と
を備え、
前記外側配線部の前記メサ部および前記フローティング部側の端辺は、
前記フローティング部に対向する領域の少なくとも一部に形成され、前記トレンチを越えて前記フローティング部側に突出する突出部と、
前記メサ部に対向する領域の少なくとも一部に形成され、前記突出部よりも前記外側配線部側に凹んでいる凹部と
を有する半導体装置。 - 前記半導体基板は第1の導電型を有し、
前記半導体装置は、前記半導体基板の端部と、前記メサ部および前記フローティング部との間に形成された第2の導電型のウェル領域を更に備える
請求項1に記載の半導体装置。 - 前記メサ部は、第2の導電型のベース領域を有し、
前記ベース領域および前記ウェル領域が接続されている
請求項2に記載の半導体装置。 - 前記凹部は、前記ベース領域が前記ウェル領域に接続できる位置まで、前記外側配線部側に凹んでいる
請求項3に記載の半導体装置。 - 前記凹部の先端は、前記ウェル領域の端部から前記メサ部の内部に向かって、前記ベース領域の深さの0.75倍だけ突出した位置よりも、前記外側配線部側に配置される
請求項3または4に記載の半導体装置。 - 前記凹部の先端は、前記トレンチよりも前記外側配線部側に配置される
請求項2から4のいずれか一項に記載の半導体装置。 - 前記フローティング部は、第2の導電型を有し、
前記突出部に覆われた前記フローティング部における前記第2の導電型の領域は、前記トレンチと接続されている
請求項2から4のいずれか一項に記載の半導体装置。 - 前記突出部は、前記フローティング部の前記第2の導電型の領域が、前記突出部の下側において前記トレンチと接続できる長さを有する
請求項7に記載の半導体装置。 - 前記突出部のうち、前記フローティング部と重なる領域の長さは、前記フローティング部の深さの0.75倍以下である
請求項8に記載の半導体装置。 - 前記突出部の幅は、前記フローティング部の幅よりも小さい
請求項1から4のいずれか一項に記載の半導体装置。 - 前記凹部の幅は、前記メサ部の幅よりも大きい
請求項1から4のいずれか一項に記載の半導体装置。 - 半導体装置の製造方法であって、
半導体基板の表面側において予め定められた領域を囲むトレンチを形成して、前記トレンチに囲まれたフローティング部と、前記フローティング部から分離されたメサ部とを形成する段階と、
前記トレンチ内に電極を形成し、且つ、前記トレンチが囲む領域の外側において、前記メサ部と前記フローティング部の配列方向に沿った外側配線部を形成する段階と、
前記外側配線部をマスクとして前記メサ部および前記フローティング部に予め定められた導電型の不純物をドープして拡散させる段階と
を備え、
前記外側配線部を形成する段階において、前記外側配線部の前記メサ部および前記フローティング部側の端辺に、
前記フローティング部に対向する領域の少なくとも一部に配置され、前記トレンチを越えて前記フローティング部側に突出する突出部を形成し、
前記メサ部に対向する領域の少なくとも一部に配置され、前記突出部よりも前記外側配線部側に凹んでいる凹部を形成する
半導体装置の製造方法。 - 前記半導体基板は第1の導電型を有し、
前記トレンチを形成する段階の前に、前記半導体基板の端部と、前記メサ部および前記フローティング部との間に第2の導電型のウェル領域を形成する段階を更に備える
請求項12に記載の半導体装置の製造方法。 - 前記不純物をドープして拡散させる段階において、第2の導電型の不純物をドープして拡散させて、前記メサ部に、前記ウェル領域と接続されたベース領域を形成する
請求項13に記載の半導体装置の製造方法。 - 前記不純物をドープして拡散させる段階において、第2の導電型の不純物をドープして拡散させて、前記突出部に覆われた前記フローティング部における第2の導電型の領域を、前記トレンチと接続させる
請求項13または14に記載の半導体装置の製造方法。
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DE112015002120.5T DE112015002120B4 (de) | 2014-12-19 | 2015-09-15 | Halbleitervorrichtung und Halbleitervorrichtungsherstellungsverfahren |
CN201580028447.2A CN106463524B (zh) | 2014-12-19 | 2015-09-15 | 半导体装置及半导体装置的制造方法 |
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JP2018157200A (ja) * | 2017-03-15 | 2018-10-04 | 富士電機株式会社 | 半導体装置 |
CN109786464A (zh) * | 2017-11-15 | 2019-05-21 | 英飞凌科技德累斯顿公司 | 具有缓冲区的半导体器件 |
JP7507756B2 (ja) | 2019-06-04 | 2024-06-28 | ローム株式会社 | 半導体装置 |
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US11784206B2 (en) * | 2020-10-26 | 2023-10-10 | Omnivision Technologies, Inc. | Pixel-array substrate and associated method |
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US20170084727A1 (en) | 2017-03-23 |
CN106463524B (zh) | 2019-10-18 |
JPWO2016098409A1 (ja) | 2017-04-27 |
US10109726B2 (en) | 2018-10-23 |
DE112015002120B4 (de) | 2024-02-22 |
JP6197966B2 (ja) | 2017-09-20 |
CN106463524A (zh) | 2017-02-22 |
DE112015002120T5 (de) | 2017-02-23 |
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