JP6277814B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6277814B2 JP6277814B2 JP2014061813A JP2014061813A JP6277814B2 JP 6277814 B2 JP6277814 B2 JP 6277814B2 JP 2014061813 A JP2014061813 A JP 2014061813A JP 2014061813 A JP2014061813 A JP 2014061813A JP 6277814 B2 JP6277814 B2 JP 6277814B2
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- 239000004065 semiconductor Substances 0.000 title claims description 85
- 239000010410 layer Substances 0.000 claims description 171
- 239000000758 substrate Substances 0.000 claims description 52
- 230000002093 peripheral effect Effects 0.000 claims description 34
- 239000002344 surface layer Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 7
- 238000011084 recovery Methods 0.000 description 25
- 210000000746 body region Anatomy 0.000 description 17
- 238000010586 diagram Methods 0.000 description 7
- 239000000969 carrier Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Description
本発明の第1実施形態について説明する。なお、本実施形態の半導体装置は、例えば、インバータ、DC/DCコンバータ等の電源回路に使用されるパワースイッチング素子として利用されると好適である。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対して外周領域2にもダメージ領域24を形成したものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
本発明の第3実施形態について説明する。本実施形態は、第2実施形態に対してダメージ領域24の形状を変更したものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
1b ダイオード領域
10 半導体基板
11 ドリフト層
12 ベース層
21 コレクタ層
22 カソード層
Claims (4)
- 第1導電型のドリフト層(11)と、
前記ドリフト層の表層部に形成された第2導電型のベース層(12)と、
前記ドリフト層のうちの前記ベース層側と反対側に形成された第2導電型のコレクタ層(21)および第1導電型のカソード層(22)と、を有する半導体基板(10)を備え、
前記半導体基板のうちのIGBT素子として動作する領域をIGBT領域(1a)とすると共にダイオード素子として動作する領域をダイオード領域(1b)としたとき、前記IGBT領域と前記ダイオード領域とが交互に繰り返し形成され、前記半導体基板の前記ダイオード領域における前記ドリフト層の表層部にダメージ領域(24)が形成されている半導体装置において、
前記IGBT領域と前記ダイオード領域とは、前記コレクタ層と前記カソード層との境界によって区画され、
前記IGBT領域における前記ドリフト層の表層部には、前記ダイオード領域との境界側の部分に、前記半導体基板の面方向に沿って前記半導体基板の厚さ以上となる前記ダメージ領域が形成され、前記境界側の部分より内縁側の部分に前記ダメージ領域が形成されていない領域を有しており、
前記IGBT領域は、前記IGBT領域と前記ダイオード領域との配列方向に沿った方向の長さを幅とすると、前記ダメージ領域が形成されていない部分の幅の前記IGBT領域における全体の幅に対する割合が1/2以上とされていることを特徴とする半導体装置。 - 前記半導体基板は、前記IGBT領域および前記ダイオード領域を囲む外周領域(2)を有し、
前記外周領域は、前記カソード層と隣接して形成される第2導電型のコレクタ層(21)を有し、前記ダイオード領域とは当該コレクタ層と前記カソード層との境界によって区画され、前記ドリフト層の表層部において、前記ダイオード領域との境界側の部分に、前記半導体基板の面方向に沿って前記半導体基板の厚さの2倍以上となる前記ダメージ領域が形成されていることを特徴とする請求項1に記載の半導体装置。 - 前記IGBT領域に形成されたダメージ領域は、前記ダイオード領域と前記IGBT領域との境界のうちの両端部側に形成された部分が、当該両端部の間の中央部分に形成された部分よりも前記半導体基板の面方向の長さが長くされていることを特徴とする請求項1または2に記載の半導体装置。
- 前記IGBT領域において、
前記ベース層は、一部がチャネル領域(12a)とされていると共に、残部がフロート領域(12b)とされ、
前記チャネル領域の表層部には、第1導電型のエミッタ領域(14)が形成され、
前記フロート領域には、当該フロート領域を前記半導体基板の厚さ方向に分割する第1導電型のホールストッパー層(29)が形成され、
前記チャネル領域と前記ドリフト層との間には、前記ドリフト層よりも不純物濃度が高くされた第1導電型のキャリアストレージ層(30)が形成されていることを特徴とする請求項1ないし3のいずれか1つに記載の半導体装置。
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