CN112750899B - 一种半导体器件及其制备方法、电器设备 - Google Patents

一种半导体器件及其制备方法、电器设备 Download PDF

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CN112750899B
CN112750899B CN201911054305.XA CN201911054305A CN112750899B CN 112750899 B CN112750899 B CN 112750899B CN 201911054305 A CN201911054305 A CN 201911054305A CN 112750899 B CN112750899 B CN 112750899B
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CN112750899A (zh
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兰昊
冯宇翔
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Abstract

本申请公开一种半导体器件及其制备方法、电器设备。该半导体器件包括硅基片、自举电极和绝缘层。硅基片上形成有发射极、栅极和集电极。自举电极形成在硅基片上。绝缘层形成于所述硅基片上；位于所述发射极和所述自举电极之间，使得所述发射极和所述自举电极之间构成自举电容。本申请的半导体器件集成有自举电容，无需在电路中另外连接自举电容，简化电路结构。

Description

一种半导体器件及其制备方法、电器设备
技术领域
本申请涉及半导体技术领域，特别是涉及一种半导体器件及其制备方法、电器设备。
背景技术
现在的大多数电路结构中都会用到半导体器件，甚至于可以用一块硅基片集成电路结构中的多个半导体器件。但是，目前通过一块硅基片制成的多个半导体器件无法构成完整的电路，还需与外部的电元件连接才能构成完整的电路，电路结构复杂，例如图1中的IPM模块100外围还需要连接自举电容131-133，配合集成的自举二极管才能实现完整的自举功能。
发明内容
本申请主要的目的是提供一种半导体器件及其制备方法、电器设备，本申请的半导体器件集成有自举电容，无需在电路中另外连接自举电容，简化电路结构。
为达到上述目的，本申请采用的一个技术方案是：提供一种半导体器件，该半导体器件包括硅基片、自举电极和绝缘层。硅基片上形成有发射极、栅极和集电极。自举电极形成在硅基片上。绝缘层形成于硅基片上；位于发射极和自举电极之间，使得发射极和自举电极之间构成自举电容。
为达到上述目的，本申请采用的另一个技术方案是：提供一种电器设备，该电器设备包括上述的半导体器件。
为达到上述目的，本申请采用的又一个技术方案为：提供一种半导体器件的制备方法，该方法包括：
提供硅基片；
在硅基片上形成绝缘层、自举电极和发射极；
其中，绝缘层位于发射极和自举电极之间，使得发射极和自举电极之间构成自举电容。
本申请在硅基片上形成自举电极，将发射极和自举电极构成自举电容的两极，并将硅基片上形成的绝缘层作为发射极和自举电极之间的绝缘介质，从而发射极、自举电极和绝缘层可构成自举电容，从而将自举电容集成于半导体器件中，无需在电路中另外连接自举电容，简化电路结构。
附图说明
图1是现有技术中的IPM模块外接自举电容的结构示意图；
图2是本申请一实施方式半导体器件的结构示意图；
图3是图2所示的半导体器件的A-A’剖面示意图；
图4是本申请半导体器件一实施方式中硅基片的结构示意图；
图5是本申请半导体器件的制备方法一实施方式的流程示意图；
图6是本申请电器设备一实施方式的结构示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅是本申请的一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
需要说明，若本申请实施方式中有涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施方式中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施方式之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
请参阅图2和图3，图2是本申请半导体器件200一实施方式的结构示意图；图3是图2所示的半导体器件200的A-A’剖面示意图。如图2和图3所示，半导体器件200包括硅基片210、自举电极230和绝缘层240。硅基片210上形成有发射极222、栅极221和集电极223。自举电极230形成在所述硅基片210上。绝缘层240形成于所述硅基片210上。绝缘层240位于发射极222和自举电极230之间，使得发射极222和自举电极230之间构成自举电容。
在本实施方式中，在硅基片210上形成自举电极230，将发射极222和自举电极230构成自举电容的两极，并将硅基片210上形成的绝缘层240作为发射极222和自举电极230之间的绝缘介质，从而发射极222、自举电极230和绝缘层240可构成自举电容，从而本实施方式将自举电容集成于半导体器件200中，半导体器件200无需在电路中另外连接自举电容，简化电路结构。
在本实施方式中，将发射极222作为自举电容的一端电极，在发射极222的电位发生变化时，因为自举电容两端电压不能突变的原因，自举电极230电位随发射极222电位变化而变化，自举电极230与发射极222之间维持接近一定的电压，自举电极230可以实现给栅极221驱动供电，从而可以实现自举功能。
其中，绝缘层240可以是二氧化硅层、氮化硅层及其他绝缘层。可选地，绝缘层240可以是在氧气或氮气氛围下，对硅基片210的部分区域进行高温氧化处理或高温氮化处理形成的。
可选地，自举电极230可以由导电的多晶硅或金属构成。
可以理解的是，可以在硅基片210上形成晶体管结构。晶体管结构包括发射极222、栅极221和集电极223。其中，晶体管结构和自举电极230的连接处可以形成绝缘层240，从而绝缘层240可以将晶体管结构和自举电极230完成隔离开来，防止自举电极230的存在影响晶体管结构本身性能的实现，可以使半导体器件200同时具有自举电容和晶体管结构的功能，提高集成度。
晶体管结构可以为绝缘栅双极晶体管。在其他实施方式中，晶体管结构可为半导体三极管结构、电力晶体管结构、光晶体管结构、双极晶体管结构或其他晶体管结构。晶体管结构为绝缘栅双极晶体管时，绝缘栅双极晶体管的结构可为阳极短路结构、分段阳极结构、超结结构。
在一实施方式中，可以在发射极222表面上形成绝缘层240，然后在绝缘层240上形成自举电极230，从而通过在发射极222上增设绝缘层240和自举电极230即可形成自举电容，简单方便，而且无需调整在硅基片210上形成的晶体管结构的结构，容易制作。
在另一实施方式中，可以在硅基片210上形成凹槽，凹槽内壁形成绝缘层240，自举电极230设置于凹槽内，从而通过在硅基片210上开设凹槽的方式将绝缘层240和自举电极230设置在硅基片210中，可以减小半导体器件200的尺寸，提高集成度。
进一步地，凹槽的数量为至少两个，每一凹槽中设置一自举电极230。至少两个凹槽中的至少两个自举电极230串联连接，从而通过在硅基片210上开设至少两个内部设有自举电极230和绝缘层240的凹槽可以增加自举电极230的电荷空间体积，从而可以增加自举电容的容量。
在又一实施方式中，凹槽可以穿设形成于发射极222，发射极222可被凹槽分隔为第一子发射极和第二子发射极。第一子发射极和第二子发射极串联。凹槽穿设形成于发射极222，并且将被凹槽分隔开的第一子发射极和第二子发射极串联，可以增加凹槽内的自举电极230的电荷空间体积，从而增加自举电容的容量。
可选地，硅基片210上还形成有第一子掺杂区和第二子掺杂区，第一子掺杂区和第二子掺杂区由凹槽分隔，第一子掺杂区连接于第一子发射极，第二子掺杂区连接第二子发射极。通过设置分别与第一子发射极和第二子发射极连接的第一子掺杂区和第二子掺杂区，将第一子掺杂区和第二子掺杂区作为电荷空间，可以增加自举电容一端的电极的电荷空间体积，从而可以增加自举电容的容量。其中，晶体管结构可以包括第一子掺杂区和第二子掺杂区，这样只需要在硅基片210开设出凹槽，并在凹槽内设置绝缘层240和自举电极230，就可将自举电容集成到半导体器件200中。当然，晶体管结构的第一子掺杂区和第二子掺杂区的面积可以适当增加，以增加电荷空间体积，从而增加自举电容的容量。
可选地，集电极223可以位于硅基片210的中间位置。栅极221可以围绕集电极223设置。并且发射极222和自举电极230均围绕栅极221设置，这样通过发射极222和自举电极230将集电极223和栅极221围绕起来，从而自举电极230的存在对硅基片210上晶体管结构的性能没有影响或影响很小。
进一步地，自举电极230和绝缘层240可以设置在晶体管结构的外围，从而自举电极230和绝缘层240不会影响晶体管结构中载流子(空穴和电流)的流动，进而不会影响晶体管结构中导电沟道的形成，对晶体管结构本身性能的实现不会产生影响。
在本实施方式中，硅基片210上还形成有N型漂移区224、P型体区225、P型源区226、N型源区227、N型缓冲区228、P型漏区229和介质层2211。半导体掺杂区(N型漂移区224、P型体区225、P型源区226、N型源区227、N型缓冲区228和P型漏区229可称为半导体掺杂区)中的至少部分可由硅基片210制备而成。具体的，在硅基片210为SOI基片时，半导体掺杂区的至少部分有顶层硅211制备而成。并且，N型漂移区224、P型体区225、P型源区226、N型源区227、N型缓冲区228、P型漏区229、介质层2211、集电极223、发射极222和栅极221可共同构成晶体管结构，以实现晶体管结构的性能。其中，与发射极222连接的第一子掺杂区和第二子掺杂区均可为P型源区226。
在一实施例中，P型源区226围绕N型漂移区224设置；P型体区225和N型缓冲区228设置在N型漂移区224上；N型源区227设置在P型体区225内；P型漏区229设置在N型缓冲区228内；介质层2211设置在N型漂移区224、P型体区225、N型缓冲区228、N型源区227和P型漏区229上；发射极222围绕介质层2211设置；栅极221和集电极223设置在介质层2211内。
在另一实施例中，在硅基片210为SOI基片时，P型体区225和N型缓冲区228设置在N型漂移区224远离绝缘层240的一侧表面上。P型源区226可围绕N型漂移区224设置。N型源区227设置在P型体区225远离绝缘层240的一侧表面上。P型漏区229设置在N型缓冲区228远离绝缘层240的一侧表面上。介质层2211设置在N型漂移区224、P型源区226、N型源区227、P型体区225、N型缓冲区228和P型漏区229远离绝缘层240的一侧上。其中，集电极223、发射极222和栅极221均可位于介质层2211内。
P型源区226和N型源区227均可与发射极222相连。集电极223可与P型漏区229相连。介质层2211将栅极221与晶体管结构的其它部分隔离。另外，栅极221在绝缘层240所在平面上的正投影可与P型体区225在绝缘层240所在平面上的正投影彼此重叠。
在实际晶体管结构的制备过程中，可以采用离子注入的方法在各个区掺杂对应类型的物质，且控制相应的掺杂浓度。P型掺杂区(例如P型体区225、P型源区226和P型漏区229)对应的掺杂物质可以含硼，N型掺杂区(例如N型漂移区224、N型源区227、N型漏区和N型缓冲区228)对应的掺杂物质可以含砷或磷。在其他实施方式中，P型源区226可设置在P型体区225远离绝缘层240的一侧表面上，晶体管结构的其他部件的设置方式可不发生变动。
在本实施方式中，半导体器件200可采用跑道形式的版图结构，这样不会产生中心区域芯片面积浪费的现象。此时，凹槽也可呈跑道状。并且凹槽可以环绕半导体器件中心设置。
当然在其他实施方式中，半导体器件200还可以采用正多边形或环形等形式的版图结构。此时，凹槽也可呈正多边形状或环状。并且凹槽可以环绕半导体器件中心设置。
在本实施方式中，自举电容的容量与栅极221电容的容量的比例可以大于10倍。从而可以通过该容量比例关系确定自举电容两端电极的尺寸、掺杂浓度等。
在本实施方式中，如图4所示，硅基片210可以是SOI基片。SOI基片可以包括顶层硅211、绝缘埋层212和衬底硅213。自举电极230、绝缘层240、发射极222、栅极221和集电极223均可以在顶层硅211上形成。当然，可以将顶层硅211作为器件制作层，通过顶层硅211制作出晶体管结构。绝缘埋层212可以是埋氧层。在其他实施方式中，硅基片210可以是单晶硅片或多晶硅片。
在本实施方式中，半导体器件200还包括第一金属连接件和第二金属连接件，其中，第一金属连接件和第二金属连接件分别用于将发射极222和自举电极230与其余元件(可以是半导体元件)相连。第一金属连接件与发射极222相连。第二金属连接件与自举电极230相连。绝缘层240还可设置于第一金属连接件和第二金属连接件之间，用于将第一金属连接件和第二金属连接件分隔开来，作为第一金属连接件和第二金属连接件之间的绝缘介质，用于和第一金属连接件和第二金属连接件共同构成自举电容。
如图5所示，本申请还提供一种上述半导体器件的制备方法。该半导体器件的制备方法，包括步骤S101和步骤S102。
S101：提供硅基片。
在本实施方式中，硅基片可以包括依次层叠设置的第一硅层、绝缘层和第二硅层。该硅基片可以是通过SOI技术制备得到的SOI基片，绝缘层可以是SOI基片中的绝缘埋层。
当然，硅基片或者可以是单晶硅片和多晶硅片。
S102：在硅基片上形成绝缘层、自举电极和发射极。
在本实施方式中，在硅基片上形成绝缘层、自举电极和发射极步骤，之前可以包括：对硅基片进行刻蚀，形成凹槽；利用倾斜的离子注入对硅基片(可以是硅基片上与凹槽相邻的区域)进行掺杂形成掺杂区。在硅基片上形成绝缘层、自举电容和发射极，可以包括：对凹槽的内壁进行绝缘化处理，形成绝缘层；将导电材料(该导电材料可为导电多晶硅或导电金属)填充到凹槽内，形成自举电极；刻蚀掺杂区形成发射极窗口，往发射极窗口内填充导电材料，形成发射极。
对凹槽的内壁进行绝缘化处理的步骤，可以包括：对凹槽的内壁进行氧化或氮化处理，形成绝缘层。对凹槽的内壁进行绝缘化处理的步骤，或者可以包括：在凹槽内壁铺设一层绝缘层。
当然，在其他实施方式中，在硅基片上形成绝缘层、自举电极和发射极，可以包括：在硅基片上形成发射极(可以在硅基片上形成发射极时完成晶体管结构的制备，也可以在硅基片上形成发射极后完成晶体管结构的制备)；在发射极上形成绝缘层；在绝缘层上形成自举电极。
请参阅图6，图6为本申请电器设备300一实施方式的结构示意图。该电器设备300包括上述的半导体器件310。电器设备300可以是家用电器，例如洗衣机、洗碗机、电饭煲、电压力锅、电炖锅或烤箱。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

1.一种半导体器件，其特征在于，包括：
硅基片，所述硅基片上形成有发射极、栅极和集电极；
自举电极，形成在所述硅基片上；
绝缘层，形成于所述硅基片上；位于所述发射极和所述自举电极之间，使得所述绝缘层与所述发射极以及所述自举电极配合构成自举电容，且所述发射极为所述自举电容的一端电极；
其中，作为所述自举电容另一端电极的所述自举电极给所述栅极驱动供电。
2.根据权利要求1所述的半导体器件，其特征在于，所述硅基片上形成有凹槽，所述凹槽内壁形成所述绝缘层，所述自举电极设置于所述凹槽内。
3.根据权利要求2所述的半导体器件，其特征在于，
所述凹槽的数量为至少两个，每一凹槽中设置一自举电极，所述至少两个凹槽中的至少两个自举电极串联连接。
4.根据权利要求2所述的半导体器件，其特征在于，
所述凹槽进一步穿设形成于所述发射极，所述发射极被所述凹槽分隔为第一子发射极和第二子发射极，所述第一子发射极和所述第二子发射极串联。
5.根据权利要求4所述的半导体器件，其特征在于，
所述硅基片上还形成有第一子掺杂区和第二子掺杂区，所述第一子掺杂区和所述第二子掺杂区由所述凹槽分隔，所述第一子掺杂区连接于所述第一子发射极，所述第二子掺杂区连接所述第二子发射极。
6.根据权利要求1所述的半导体器件，其特征在于，
所述集电极位于所述硅基片的中间位置，所述栅极围绕所述集电极设置，所述发射极和所述自举电极均围绕所述栅极设置。
7.根据权利要求1所述的半导体器件，其特征在于，
所述硅基片上还形成有N型漂移区、P型体区、N型缓冲区、N型源区、P型源区、P型漏区和介质层；
所述P型源区围绕所述N型漂移区设置；
所述P型体区和所述N型缓冲区设置在所述N型漂移区上；
所述N型源区设置在所述P型体区内；
所述P型漏区设置在所述N型缓冲区内；
所述介质层设置在所述N型漂移区、所述P型体区、所述N型缓冲区、所述N型源区和所述P型漏区上；
所述发射极围绕所述介质层设置；
所述栅极和所述集电极设置在所述介质层内；
其中，所述P型源区和所述N型源区与所述发射极相连，所述集电极可与所述P型漏区相连；所述N型漂移区、所述P型体区、所述N型源区、所述P型源区、所述N型缓冲区和所述P型漏区中的至少部分由硅基片制备而成。
8.一种电器设备，其特征在于，所述电器设备包括如权利要求1至7任意一项所述的半导体器件。
9.一种半导体器件的制备方法，其特征在于，所述方法包括：
提供硅基片；
在所述硅基片上形成绝缘层、自举电极和发射极；
其中，所述绝缘层位于所述发射极和所述自举电极之间，使得所述绝缘层与所述发射极以及所述自举电极配合构成自举电容，且所述发射极为所述自举电容的一端电极；
其中，作为所述自举电容另一端电极的所述自举电极给栅极驱动供电。
10.根据权利要求9所述的制备方法，其特征在于，
所述在所述硅基片上形成绝缘层、自举电极和发射极，之前包括：
对所述硅基片进行刻蚀，形成凹槽；
利用倾斜的离子注入对硅基片进行掺杂形成掺杂区；
所述在所述硅基片上形成绝缘层、自举电极和发射极，包括：
对所述凹槽的内壁进行绝缘化处理，形成所述绝缘层；
将多晶硅填充到所述凹槽内，形成所述自举电极；
刻蚀所述掺杂区形成发射极窗口，往所述发射极窗口内填充导电材料，形成发射极。
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