CN111081779B - 一种屏蔽栅沟槽式mosfet及其制造方法 - Google Patents

一种屏蔽栅沟槽式mosfet及其制造方法 Download PDF

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CN111081779B
CN111081779B CN201911226821.6A CN201911226821A CN111081779B CN 111081779 B CN111081779 B CN 111081779B CN 201911226821 A CN201911226821 A CN 201911226821A CN 111081779 B CN111081779 B CN 111081779B
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Abstract

本发明公开了一种包括ESD钳位二极管的屏蔽栅沟槽式MOSFET及其制造方法。根据本发明的N沟道屏蔽栅沟槽式MOSFET，具有n+掺杂的屏蔽电极，且在制造过程中只需要提供两次多晶硅层。这使得，当通过缩小屏蔽栅的宽度以降低Rds并减小器件尺寸时，不会引起更高的开关损耗，且不会引起动态雪崩的不稳定性。

Description

一种屏蔽栅沟槽式MOSFET及其制造方法
技术领域
本发明主要涉及半导体功率器件的单元结构、器件构造和制造过程。更具体地，本发明涉及一种沟槽式MOSFET(金属氧化物半导体场效应管)的新型改良的单元结构、器件构造及其改良的制造过程。
背景技术
美国专利号7，855，415公开了一种具有屏蔽栅结构的沟槽式MOSFET，如图1A所示。与传统的沟槽栅相比，屏蔽栅沟槽式MOSFET(Shielded gate trench MOSFET)越来越受欢迎，原因在于其具有较低的栅漏电容(Cgd)以及相应较低的栅漏电荷(Qgd)和较高的击穿电压，使得在诸如反相器和直流-直流功率电路等功率开关应用中有了更好的选择。与此同时，屏蔽栅沟槽式MOSFET中的屏蔽栅结构作为一个内建的缓冲器，对减少电磁干扰至关重要。此外，该现有技术还公开了一种包括ESD(Electrostatic Discharge,静电释放)保护二极管的屏蔽栅沟槽式MOSFET，如图1B所示,其中，ESD保护二极管由交替排列的p型多晶硅和N+多晶硅组成。
然而，图1B所示的屏蔽栅沟槽式MOSFET在制造过程中需要提供三次多晶硅层(第一层多晶硅层用于形成屏蔽栅结构中的屏蔽电极，第二层多晶硅层用于制造栅电极，第三层多晶硅层用于制造ESD二极管)和两次掩模版(分别用于定义屏蔽栅和ESD二极管)，因此制造工艺较为复杂并且成本较高。
图2所示的是美国专利号9，963，969公开的另一种包括ESD二极管的屏蔽栅沟槽式MOSFET，与图1B相比，图2所示的现有技术在制造过程中仅需要提供两次多晶硅层，因为用于形成屏蔽电极的多晶硅层同时可以用于形成ESD二极管。同时，用于定义屏蔽栅的掩模版可以同时用来定义ESD二极管的位置，因此，图2所示的现有技术的制造成本显著降低。
然而，图2所示的N沟道屏蔽栅沟槽式MOSFET中具有p型掺杂的屏蔽电极结构，当通过缩小屏蔽栅的宽度来减少器件尺寸和降低导通电阻时，这种p掺杂的屏蔽电极结构会引起很高的屏蔽栅电阻，从而导致动态雪崩的不稳定性和更多的开关损耗。
因此，在半导体功率器件领域中，特别是对于屏蔽栅沟槽式MOSFET的设计和制造，仍需要提供一种新型的单元结构、器件结构和改良的制工艺，可以制造一种包括ESD二极管的屏蔽栅沟槽式MOSFET以及一种简单的制造工艺，可以解决现有技术中的问题，以提高器件性能并降低制造成本。
发明内容
本发明提供了一种包括ESD钳位二极管的屏蔽栅沟槽式MOSFET和只需要提供两层多晶硅层的制造工艺。同时，根据本发明的N沟道屏蔽栅沟槽式MOSFET，其屏蔽电极为具有n型掺杂的多晶硅，这意味着根据本发明的屏蔽栅沟槽式MOSFET通过减小屏蔽栅的宽度来减小器件尺寸时，不会引起更高的开关损耗和动态雪崩的不稳定性。
根据本发明的一个方面，提供了一种屏蔽栅沟槽式MOSFET，其包括：
(a)第一导电类型的外延层，覆盖第一导电类型的衬底的上方，其中所述外延层的多数载流子浓度低于所述衬底；
(b)多个第一类沟槽，形成于所述外延层中，且位于有源区，每个第一类沟槽中填充以屏蔽栅结构，其包括位于第一类沟槽下半部分作为屏蔽电极的第一多晶硅层和位于第一类沟槽上半部分作为栅电极的第二多晶硅层，其中所述屏蔽电极和所述外延层之间由第一绝缘层绝缘，所述栅电极和所述外延层之间由栅绝缘层绝缘，所述屏蔽电极和所述栅电极之间由第二绝缘层绝缘，其中所述栅绝缘层的厚度小于所述第一绝缘层的厚度；
(c)一个ESD钳位二极管，由所述第二多晶硅层构成，位于所述外延层和多个第二类沟槽的上方，其中每个所述第二类沟槽内包括作为单电极的所述第一多晶硅层；
(d)所述ESD钳位二极管和所述外延层之间由所述栅绝缘层绝缘，所述ESD钳位二极管和位于第二类沟槽中的所述单电极之间由所述第二绝缘层绝缘，位于第二类沟槽中的所述单电极和所述外延层之间由所述第一绝缘层绝缘；
(e)所述第一多晶硅层和所述第二多晶硅层中的多数载流子都是第一导电类型；和
(f)多个沟槽式阳极(阴极)接触区，分别延伸入所述ESD钳位二极管的阳极(阴极)，且均位于所述第二类沟槽的上方。
根据本发明的另一个方面，公开了一种屏蔽栅沟槽式MOSFET，其包括：
(a)第一导电类型的外延层，覆盖第一导电类型的衬底的上方，其中所述外延层的多数载流子浓度低于所述衬底；
(b)多个第一类沟槽，形成于所述外延层中，且位于有源区，每个第一类沟槽中填充以屏蔽栅结构，其包括位于第一类沟槽下半部分作为屏蔽电极的第一多晶硅层和位于第一类沟槽上半部分作为栅电极的第二多晶硅层，其中所述屏蔽电极和所述外延层之间由第一绝缘层绝缘，所述栅电极和所述外延层之间由栅绝缘层绝缘，所述屏蔽电极和所述栅电极之间由第二绝缘层绝缘，其中所述栅绝缘层的厚度小于所述第一绝缘层的厚度；
(c)一个ESD钳位二极管，由所述第二多晶硅层构成，位于所述外延层和多个第二类沟槽的上方，其中每个所述第二类沟槽内包括位于沟槽下半部分作为下方电极的所述第一多晶硅层和位于沟槽上半部分作为上方电极的所述第二多晶硅层，其中所述下方电极和所述上方电极之间由所述第二绝缘层绝缘；
(d)所述ESD钳位二极管和所述外延层之间由所述栅绝缘层绝缘，所述下方电极与所述外延层之间由所述第一绝缘层绝缘；
(e)所述第一多晶硅层和所述第二多晶硅层中的多数载流子都是第一导电类型；和
(f)多个沟槽式阳极(阴极)接触区，分别延伸入所述ESD钳位二极管的阳极(阴极)，且均位于所述第二类沟槽的上方。
根据本发明的优选的实施例还包括以下一个或多个细节特征：所述的ESD钳位二极管由至少一对背靠背的齐纳二极管组成，包括多个交替形成的第一导电类型和第二导电类型掺杂区，其中所述第二导电类型与第一导电类型相反；所述有源区还包括第一导电类型的源区和第二导电类型的体区，所述源区和体区通过沟槽式源体接触区中的接触金属插塞连接至源极金属，其中所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞；所述屏蔽电极连接至一个外接部分，并通过沟槽式屏蔽电极接触区中的接触金属插塞进一步连接至源极金属，其中所述屏蔽电极的外接部分位于一个第三类沟槽中，且由所述第一多晶硅层构成，所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞；所述栅电极连接至一个更宽的栅电极，并通过沟槽式栅接触区中的接触金属插塞进一步连接至栅极金属，其中所述更宽的栅电极位于一个第四类沟槽中，与所述栅电极同时形成，所述第四类沟槽的宽度大于所述第一类沟槽的宽度，所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞。
根据本发明的另一个方面，提供了一种制造屏蔽栅沟槽式MOSFET的方法，包括以下步骤：(a)在第一导电类型的衬底上生长形成第一导电类型的外延层，其中所述外延层的多数载流子浓度低于所述衬底；(b)在外延层中形成多个沟槽，包括位于有源区的多个第一类沟槽和多个第二类沟槽；(c)淀积第一多晶硅层填充所述多个沟槽，所述第一多晶硅层和所述多个沟槽之间衬有第一绝缘层；(d)进行多晶硅的化学机械抛光，使得所述第一多晶硅层被保留在所述多个沟槽的内部，同时形成位于所述第二沟槽中的单电极；(e)提供屏蔽栅掩模版，进行多晶硅刻蚀和氧化物刻蚀，使得所述第一多晶硅层和所述第一绝缘层被保留在所述第一类沟槽的下半部分，形成屏蔽电极；(f)生长形成栅绝缘层；(g)淀积一层未掺杂的多晶硅层，填充所述第一类沟槽的上半部分，同时覆盖所述外延层的上表面；(h)进行第二导电类型载流子的离子注入；(i)分别形成一层热氧化层和一层氮化物层，位于所述第二多晶硅层上方；(j)提供多晶硅掩模版，进行干法氮化物刻蚀和第一导电类型载流子的离子注入；(k)推进扩散注入的第一导电类型载流子；(l)刻蚀第二多晶硅层，保留位于所述第一类沟槽上半部分的第二多晶硅层，用作栅电极，同时保留位于第二类沟槽上方的第二多晶硅层，用于形成ESD钳位二极管；(m)进行第二导电类型载流子的离子注入；(n)移除所述氮化物层并推进扩散注入的第二导电类型载流子；(o)提供源掩模版，再次进行第一导电类型载流子的离子注入，形成源区和ESD钳位二极管的阳极(阴极)。
通过参考以下各个附图，阅读下文对优选实施例的详细描述，本发明的上述及其他目的和有点对于本领域的普通技术人员来说无疑是显而易见的。
附图说明
图1A示出了现有技术所揭示的一种屏蔽栅沟槽式MOSFET的剖面图。
图1B示出了现有技术所揭示的包括ESD保护二极管的屏蔽栅沟槽式MOSFET的剖面图。
图2示出了另一个现有技术所揭示的包括ESD保护二极管的屏蔽栅沟槽式MOSFET的剖面图。
图3A是根据本发明一个优选实施例的剖面图。
图3B是根据本发明另一个优选实施例的剖面图。
图3C是根据本发明另一个优选实施例的剖面图。
图3D是根据本发明另一个优选实施例的剖面图。
图3E是根据本发明另一个优选实施例的剖面图。
图3F是根据本发明另一个优选实施例的剖面图。
图3G是根据本发明另一个优选实施例的剖面图。
图4A-图4K示出了一系列剖面图，显示制造图3A中屏蔽栅沟槽式MOSFET的工艺步骤。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图3A所示的是本发明的一个优选实施例，其中包括一个ESD钳位二极管的N沟道屏蔽栅沟槽式MOSFET 300形成在位于N+衬底301上的N外延层302中。该N外延层302中包括：多个第一类沟槽303，位于有源区(如图3A所示)；多个第二类沟槽304，位于ESD钳位二极管下方(该实施例中包括两个第二类沟槽304)；一个第三类沟槽305，用于屏蔽栅电极连接；和一个第四类沟槽306，用于栅极连接，其宽度大于所述第一类沟槽303的宽度。每个所述第一类沟槽303中都填充以屏蔽栅结构，包括：第一多晶硅层，位于沟槽下半部分，作为n型掺杂的屏蔽电极307；第二多晶硅层，位于沟槽上半部分，作为n型掺杂的栅电极308；其中，所述屏蔽电极307与所述N外延层302之间由第一绝缘层309绝缘，所述栅电极308与所述N外延层302之间由栅绝缘层310绝缘，所述屏蔽电极307和所述栅电极308之间由第二绝缘层311绝缘，其中所述栅绝缘层310的厚度小于所述第一绝缘层309的厚度。有源区进一步包括P型体区312和n+源区313，其中，除了两个相邻的第二类沟槽304之间，所述P型体区312延伸于其余的每两个相邻的沟槽之间；所述n+源区313位于P型体区312上方，并延伸于每两个相邻的栅电极308之间，。所述n+源区313和所述P型体区312通过沟槽式源体接触区中的接触金属插塞315-1进一步连接至源极金属314，其中，所述接触金属插塞315-1延伸穿过一个接触绝缘层316、n+源区313并延伸入位于P型体区312中的一个p+体接触区中。位于有源区中的屏蔽电极307连接至一个n型掺杂的外接部分318，并通过沟槽式屏蔽电极接触区中的接触金属插塞315-2进一步连接至源极金属314，其中所述屏蔽电极的外接部分318位于第三类沟槽315中，由第一多晶硅层构成，并与所述N外延层302之间由所述第一绝缘层309绝缘。位于有源区中的栅电极308连接至一个n型掺杂的更宽的栅电极319，并通过沟槽式栅接触区中的接触金属插塞315-3进一步连接至栅极金属320，其中所述更宽的栅电极319位于第四类沟槽306中，与栅电极308同时形成。ESD钳位二极管形成于N外延层302上表面，并位于两个第二类沟槽304上方，其中每个第二类沟槽304中填充以第一多晶硅层作为n型掺杂的单电极321。所述ESD钳位二极管由至少一对背靠背的齐纳二极管组成，包括多个交替形成的n+/p/n+/p/n+掺杂区，该ESD钳位二极管由第二多晶硅层构成，并与所述N外延层302之间由所述栅绝缘层310绝缘，与所述单电极321之间由所述第二绝缘层311绝缘。位于该ESD钳位二极管两头的n+阳极通过沟槽式阳极接触区中的接触金属插塞315-4分别短接至源极金属314和栅极金属320，其中所述沟槽式阳极接触区分别位于每个第二类沟槽304上方。所有的接触金属插塞(315-1、315-2、315-3和315-4)都可以通过一个衬有Ti/TiN或Co/TiN或Ta/TiN势垒层的钨插塞实现。
图3B所示的是根据本发明的另一个优选的实施例，其中N沟道屏蔽栅沟槽式MOSFET 400与图3A具有相似的结构，除了在图3B中，ESD钳位二极管下方的N外延层402中包括至少三个第二类沟槽404，每个第二类沟槽404中都包括单电极结构。
图3C所示的是根据本发明的另一个优选的实施例，其中N沟道屏蔽栅沟槽式MOSFET 500与图3B具有相似的结构，除了在图3C中，包括一个P*掺杂区522，其位于ESD钳位二极管的下方并延伸于每两个相邻的第二类沟槽504之间，用以避免发生过早的击穿。该P*掺杂区522的多数载流子掺杂浓度低于P型体区512，同时，其结深小于所述P型体区512。
图3D所示的是根据本发明的另一个优选的实施例，其中N沟道屏蔽栅沟槽式MOSFET 600与图3A具有相似的结构，除了在图3D中，第二类沟槽604中填充以与第四类沟槽606中相同的屏蔽栅结构，而不是如图3A中所示的单电极结构。每个所述第二类沟槽604中包括一个位于沟槽下半部分的下方电极621和一个位于沟槽上半部分的上方电极619，该上方电极619为n型掺杂，并同时作为ESD钳位二极管两头的n+阳极。相应地，沟槽式阳极接触区623延伸入所述上方电极619中。
图3E所示的是根据本发明的另一个优选的实施例，其中N沟道屏蔽栅沟槽式MOSFET 700与图3D具有相似的结构，除了在图3E中，包括一个P*掺杂区722，其位于ESD钳位二极管的下方并延伸于两个相邻的第二类沟槽704之间，用以避免发生过早的击穿。该P*掺杂区722的所述载流子浓度低于P型体区712，同时，其结深小于所述P型体区712。
图3F所示的是根据本发明的另一个优选的实施例，其中N沟道屏蔽栅沟槽式MOSFET 800与图3D具有相似的结构，除了在图3F中，ESD钳位二极管下方的N外延层802中包括至少三个第二类沟槽804，每个第二类沟槽804中都包括屏蔽栅结构。
图3G是根据本发明的另一个优选的实施例，其中N沟道屏蔽栅沟槽式MOSFET 900与图3F具有相似的结构，除了在图3G中，还包括一个P*掺杂区922，其位于ESD钳位二极管的下方并延伸于每两个相邻的第二类沟槽904之间，用以避免发生过早的击穿。该P*掺杂区922的所述载流子浓度低于P型体区912，同时，其结深小于所述P型体区912。
图4A～4K是一系列典型的制造步骤，用于形成根据本发明的图3A中的N沟道屏蔽栅沟槽式MOSFET 300。如图4A所示，首先在N+衬底301上生长N外延层302，并在该N外延层302上提供沟槽掩模版(未示出)。根据该沟槽掩模版的定义，通过光刻和刻蚀，在N外延层302中形成多个沟槽，包括：多个第一类沟槽303、多个第二类沟槽304、一个第三类沟槽305和一个宽度大于第一类沟槽的第四类沟槽306。接着，沿所述N外延层302的上表面和所述多个沟槽的内表面形成第一绝缘层309。之后，在该第一绝缘层309上淀积形成n型掺杂的第一多晶硅层，以填充位于N外延层302中的多个沟槽。
在图4B中，通过实施多晶硅的化学机械抛光步骤，所述第一多晶硅层被从N外延层302上表面移除，保留在多个沟槽内，用于形成：位于第二类沟槽304中的单电极321；和位于第三类沟槽305中的屏蔽栅的外接部分318。之后，提供一层屏蔽栅掩模版来定义形成屏蔽栅结构的区域，包括：位于有源区的多个第一类沟槽303；和用于栅连接的第四类沟槽306。
在图4C中，通过进行干法多晶硅刻蚀，将第一多晶硅层从所述第一类沟槽303和第四类沟槽306的上半部分移除；通过进行氧化物刻蚀，将第一绝缘层309从所述第一类沟槽303和第四类沟槽306的上半部分移除，并从所述N外延层302的上表面未被屏蔽栅掩模版覆盖的部分移除。
在图4D中，先移除屏蔽栅掩模版，再沿器件暴露的外表面形成另一层氧化层作为栅绝缘层310。
在图4E中，淀积一层未掺杂的第二多晶硅层323，使其填充所述第一类沟槽303和第四类沟槽306的上半部分，并覆盖器件暴露的上表面。之后对第二多晶硅层323进行硼的离子注入，使其多数载流子为P型载流子。
在图4F中，在所述第二多晶硅层323的上表面形成厚度约为100埃的热氧化层324，之后在该热氧化层324上淀积形成厚度约为2000～3000埃的氮化物层325。随后，根据一层多晶硅掩模版的定义，该氮化物层325被刻蚀以保留部分位于所述热氧化层324上方。接着，在器件上方进行磷的离子注入，使得所述第二多晶硅层323的多数载流子为N型载流子。
在图4G中，移除多晶硅掩模版，并进行上一步所注入的磷离子的推进扩散，使得N型的磷离子进一步扩散进所述第二多晶硅层323。同时，该推进扩散的过程使得在没有被氮化物层325覆盖的地方，N型载流子被进一步扩散进所述第一类沟槽303和第四类沟槽306上方的第二多晶硅层中。
在图4H中，首先将热氧化层324从未被氮化物层325覆盖的区域移除，接着进行多晶硅的刻蚀，使得剩下的所述第二多晶硅层：填充于所述第一类沟槽303的上半部分，作为屏蔽栅结构的栅电极308；填充于所述第四类沟槽306的上半部分并突出于所述第四类沟槽306，作为用于栅连接的更宽的栅电极319；覆盖所述第二类沟槽304的上方，用以形成ESD钳位二极管。之后，再进行一次硼的离子注入，以在每两个相邻的沟槽(不包括两个相邻的第二类沟槽304)之间形成P型体区312。接下来，移除所述氮化物层325和热氧化层324，并进行P型载流子的推进扩散。
在图4I中，提供由同一层掩模版制成的源极掩模版和阳极掩模版，进行N型载流子的离子注入，以实现：在有源区内的P型体区312上方形成n+源区313；形成ESD钳位二极管的n+阳极327；使得栅电极319的多数载流子为N型载流子。
在图4J中，移除源极掩模版和阳极掩模版，在器件的上表面淀积一层接触绝缘层316，并在其上提供一层接触掩模版(未示出)。根据接触掩模版的定义，通过先后的干法氧化物刻蚀和干法硅刻蚀，形成多个接触沟槽。之后，进行BF2的离子注入，形成一个p+接触掺杂区317，其位于P型体区312中，且至少包围接触沟槽328的底部。
在图4K中，先在所有接触沟槽的内表面淀积形成Ti/TiN势垒层(或Ta/TiN或Co/TiN，未示出)，接着在该势垒层上淀积钨金属层并通过回刻分别形成：用于沟槽式源体接触区的接触金属插塞315-1、用于沟槽式屏蔽电极接触区的接触金属插塞315-2、用于沟槽式栅接触区的接触金属插塞315-3以及用于沟槽式阳极接触区的接触金属插塞315-4。之后，在器件的上表面淀积金属层，通过金属掩模版(未示出)定义，分别刻蚀形成源极金属314和栅极金属320。
尽管在此说明了各种实施例，可以理解，在不脱离本发明的精神和范围的所附权利要求书的范围内，通过所述的指导，可以对本发明作出各种修改。例如，可以用本发明的方法形成其导电类型与文中所描述的相反的导电类型的各种半导体区域的结构。

Claims (10)

1.一种屏蔽栅沟槽式MOSFET，其特征在于，包括：
第一导电类型的外延层，覆盖第一导电类型的衬底的上方，其中所述外延层的多数载流子浓度低于所述衬底；
多个第一类沟槽，形成于所述外延层中，且位于有源区，每个第一类沟槽中填充以屏蔽栅结构，其包括位于第一类沟槽下半部分作为屏蔽电极的第一多晶硅层和位于第一类沟槽上半部分作为栅电极的第二多晶硅层，其中所述屏蔽电极和所述外延层之间由第一绝缘层绝缘，所述栅电极和所述外延层之间由栅绝缘层绝缘，所述屏蔽电极和所述栅电极之间由第二绝缘层绝缘，其中所述栅绝缘层的厚度小于所述第一绝缘层的厚度；
一个ESD钳位二极管，由所述第二多晶硅层构成，位于所述外延层和多个第二类沟槽的上方，其中每个所述第二类沟槽内包括作为单电极的所述第一多晶硅层；
一个ESD钳位二极管，由所述第二多晶硅层构成，位于所述外延层和多个第二类沟槽的上方，其中每个所述第二类沟槽内包括位于沟槽下半部分作为下方电极的所述第一多晶硅层和位于沟槽上半部分作为上方电极的所述第二多晶硅层，其中所述下方电极和所述上方电极之间由所述第二绝缘层绝缘；
所述ESD钳位二极管和所述外延层之间由所述栅绝缘层绝缘，所述ESD钳位二极管和位于第二类沟槽中的所述单电极之间由所述第二绝缘层绝缘，位于第二类沟槽中的所述单电极和所述外延层之间由所述第一绝缘层绝缘；
所述第一多晶硅层和所述第二多晶硅层中的多数载流子都是第一导电类型；和
多个沟槽式阳极接触区，分别延伸入所述ESD钳位二极管的阳极，且均位于所述第二类沟槽的上方。
2.根据权利要求1所述的屏蔽栅沟槽式MOSFET，其特征在于，所述的ESD钳位二极管由至少一对背靠背的齐纳二极管组成，包括多个交替形成的第一导电类型和第二导电类型掺杂区，其中所述第二导电类型与第一导电类型相反。
3.根据权利要求1所述的屏蔽栅沟槽式MOSFET，其特征在于，所述有源区还包括第一导电类型的源区和第二导电类型的体区，所述源区和体区通过沟槽式源体接触区中的接触金属插塞连接至源极金属，其中所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞。
4.根据权利要求1所述的屏蔽栅沟槽式MOSFET，其特征在于，所述屏蔽电极连接至一个外接部分，并通过沟槽式屏蔽电极接触区中的接触金属插塞进一步连接至源极金属，其中所述屏蔽电极的外接部分位于一个第三类沟槽中，且由所述第一多晶硅层构成，所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞。
5.根据权利要求1所述的屏蔽栅沟槽式MOSFET，其特征在于，所述栅电极连接至一个更宽的栅电极，并通过沟槽式栅接触区中的接触金属插塞进一步连接至栅极金属，其中所述更宽的栅电极位于一个第四类沟槽中，与所述栅电极同时形成，所述第四类沟槽的宽度大于所述第一类沟槽的宽度，所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞。
6.一种屏蔽栅沟槽式MOSFET，其特征在于，包括：
第一导电类型的外延层，覆盖第一导电类型的衬底的上方，其中所述外延层的多数载流子浓度低于所述衬底；
多个第一类沟槽，形成于所述外延层中，且位于有源区，每个第一类沟槽中填充以屏蔽栅结构，其包括位于第一类沟槽下半部分作为屏蔽电极的第一多晶硅层和位于第一类沟槽上半部分作为栅电极的第二多晶硅层，其中所述屏蔽电极和所述外延层之间由第一绝缘层绝缘，所述栅电极和所述外延层之间由栅绝缘层绝缘，所述屏蔽电极和所述栅电极之间由第二绝缘层绝缘，其中所述栅绝缘层的厚度小于所述第一绝缘层的厚度；
一个ESD钳位二极管，由所述第二多晶硅层构成，位于所述外延层和多个第二类沟槽的上方，其中每个所述第二类沟槽内包括位于沟槽下半部分作为下方电极的所述第一多晶硅层和位于沟槽上半部分作为上方电极的所述第二多晶硅层，其中所述下方电极和所述上方电极之间由所述第二绝缘层绝缘；
所述ESD钳位二极管和所述外延层之间由所述栅绝缘层绝缘，所述下方电极与所述外延层之间由所述第一绝缘层绝缘；
所述第一多晶硅层和所述第二多晶硅层中的多数载流子都是第一导电类型；和
多个沟槽式阳极接触区，分别延伸入所述ESD钳位二极管的阳极，且均位于所述第二类沟槽的上方电极中。
7.根据权利要求6所述的屏蔽栅沟槽式MOSFET，其特征在于，所述的ESD钳位二极管由至少一对背靠背的齐纳二极管组成，包括多个交替形成的第一导电类型和第二导电类型掺杂区，其中所述第二导电类型与第一导电类型相反。
8.根据权利要求6所述的屏蔽栅沟槽式MOSFET，其特征在于，所述有源区还包括第一导电类型的源区和第二导电类型的体区，所述源区和体区通过沟槽式源体接触区中的接触金属插塞连接至源极金属，其中所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞。
9.根据权利要求6所述的屏蔽栅沟槽式MOSFET，其特征在于，所述屏蔽电极连接至一个外接部分，并通过沟槽式屏蔽电极接触区中的接触金属插塞进一步连接至源极金属，其中所述屏蔽电极的外接部分位于一个第三类沟槽中，且由所述第一多晶硅层构成，所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞。
10.根据权利要求6所述的屏蔽栅沟槽式MOSFET，其特征在于，所述栅电极连接至一个更宽的栅电极，并通过沟槽式栅接触区中的接触金属插塞进一步连接至栅极金属，其中所述更宽的栅电极位于一个第四类沟槽中，与所述栅电极同时形成，所述第四类沟槽的宽度大于所述第一类沟槽的宽度，所述接触金属插塞为衬有Ti/TiN或Co/TiN或Ta/TiN的钨插塞。
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