CN103872037A - 在功率晶体管中集成自举电路元件的系统和方法 - Google Patents
在功率晶体管中集成自举电路元件的系统和方法 Download PDFInfo
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Abstract
在功率晶体管中集成自举电路元件的系统和方法。实施例涉及与至少一个其它器件,例如功率晶体管或其它半导体器件集成的自举电路。在实施例中,自举电路可以包括自举电容器和自举二极管,或者自举电路可以包括自举电容器和自举晶体管。在实施例中,自举电容器包括基于半导体的电容器,与电解、陶瓷或其它电容器相对。在实施例中,自举电路与另一电路或器件(例如在一个实施例中的功率晶体管器件)的集成处于硅级,而不是作为传统方法的类模块的封装中系统。换句话说,自举电路元件和功率晶体管或其它器件的组合在实施例中形成硅上系统,或集成电路,并且另外可以被布置在单一封装中。
Description
技术领域
本发明总体上涉及集成电路并且更具体地涉及在功率晶体管和其它集成电路器件中集成自举电路元件。
背景技术
一些集成电路,例如用于功率晶体管的驱动器电路需要自举电路来最有效地运行。在一个示例中,自举电路包括电容器和二极管并且运行来除供给电压之外还提供在电容器中存储的电压使得存在足够的功率将晶体管偏置到线性操作中。在另一示例中,自举电路包括电容器和晶体管。
除了容纳功率晶体管或其它集成电路的封装之外通常还提供自举电路,然而有时在相同的封装中提供自举电路的至少一部分。例如,封装中系统配置可以包括自举电路模块或相似的配置,其中提供自举电路以及在单一封装中的其它模块,然而自举电路仍保持至少部分地不同于在封装内的其它模块。
然而,尤其关于基于半导体的自举电容器和自举二极管两者,或自举晶体管,与其它电路元件(例如功率晶体管和其它器件)的真正硅级集成,整个自举电路的完全集成仍然是一个挑战。至少因为需要的自举电容的范围,挑战存在于自举电路元件和功率晶体管或其它电路的进一步硅级集成中以例如节省空间和成本并且提供简化的解决方案。
发明内容
实施例涉及在功率晶体管和/或其它集成电路器件中集成自举电路元件。
在实施例中,一种半导体器件包括封装;和集成电路,该集成电路布置在封装中并且包括互相耦合的至少一个晶体管器件和自举电路,自举电路包括基于半导体的自举电容器器件。
在实施例中,一种集成电路包括半导体功率晶体管;和电路,该电路包括利用半导体功率晶体管单片地形成的半导体电容器。
在实施例中,一种方法包括形成至少一个晶体管器件;并且利用该至少一个晶体管器件单片地形成基于半导体的自举电容器元件;并且在封装中设置所述单片地形成的至少一个晶体管器件和自举电容器元件。
在阅读下面的描述并且浏览附图时,本领域技术人员将认识到可被包括的附加的特征以及实施例的优点。
附图说明
考虑到下面结合附图的本发明的各种实施例的详细描述,本发明可以被更加完全地理解,其中:
图1是根据实施例的包括自举电路的浮动驱动器电路的框图。
图2A是根据实施例的自举电路集成布局的框图。
图2B是根据实施例的自举电路集成布局的框图。
图2C是根据实施例的自举电路集成布局的框图。
图2D是根据实施例的自举电路集成布局的框图。
图3是根据实施例的形成沟槽的方法的流程图。
图4A是根据实施例的自举电容器的侧截面图。
图4B是根据实施例的注入过程的侧截面图。
图4C是根据实施例的注入过程的侧截面图。
图4D是根据实施例的高侧集成的自举电容器的侧截面图。
图4E是根据实施例的高侧集成的自举电容器的侧截面图。
图5A是根据实施例的利用不同蚀刻工艺来形成沟槽的工艺阶段的侧截面图。
图5B是根据实施例的利用不同蚀刻工艺来形成沟槽的工艺阶段的侧截面图。
图5C是根据实施例的利用不同蚀刻工艺来形成沟槽的工艺阶段的侧截面图。
图5D是根据实施例的利用不同蚀刻工艺来形成沟槽的工艺阶段的侧截面图。
图6A是根据实施例的形成集成自举电容器的工艺阶段的侧截面图。
图6B是根据实施例的形成集成自举电容器的工艺阶段的侧截面图。
图6C是根据实施例的形成集成自举电容器的工艺阶段的侧截面图。
图6D是根据实施例的形成集成自举电容器的工艺阶段的侧截面图。
图6E是根据实施例的形成集成自举电容器的工艺阶段的侧截面图。
图7A是根据实施例的包括自举电路的浮动驱动器电路的框图。
图7B是根据实施例的自举电容器和自举晶体管的耦合布置的侧截面图。
图7C是根据实施例的自举电容器和自举晶体管的耦合布置的侧截面图。
图8是根据实施例的自举电容器和二极管的耦合布置的顶视图。
图9是根据实施例的自举电容器和二极管的耦合布置的顶视图。
图10是根据实施例的自举电容器和二极管的耦合布置的顶视图。
虽然本发明服从于各种修改和替代的形式,其详细说明已经通过在图中的示例被示出并且将被详细地描述。然而,应该理解到意图不是将本发明限制到被描述的特定实施例。相反,意图是覆盖落入如由所附的权利要求限定的本发明的精神和范围内的所有修改,等同物,和替代物。
具体实施方式
实施例涉及单片地集成的和/或在与至少一个其它器件,例如MOSFET,SiC或GaN晶体管器件,和/或一些其它半导体器件相同的封装中的自举电路。在一个实施例中,晶体管器件包括功率晶体管器件。在实施例中,自举电路可以包括自举电容器和自举二极管,或者自举电路可以包括自举电容器和自举晶体管。在实施例中,自举电容器包括基于半导体的电容器,与电解、陶瓷或其它电容器相对。在实施例中,自举电路与另一电路或器件(例如在一个实施例中的功率晶体管器件)的集成处于硅级,而不是作为传统方法的类模块的封装中系统。换句话说,自举电路元件和功率晶体管或其它器件的组合在实施例中形成硅上系统(system-on-silicon),或集成电路,并且另外可以被布置在单一封装中。除其它之外,实施例的优点还包括减少的面积要求和成本,装配和板布局设计的简化,降低的寄生效应和在效率方面相关的增加,以及用于终端用户的简化的供给链。
参照图1,描绘了浮动驱动器降压转换器电路100。电路100可以包括在其它实施例中的其它电路类型或元件,例如一些其它MOSFET电路,SiC器件,例如jFET,GaN器件例如高电子迁移率晶体管(HEMT),或者一些其它集成电路或半导体器件。电路100包括自举电路102,驱动器电路104,MOSFET电路106和输出电感器108和电容器109。虽然被描绘并被称为单一电路,在实施例中每个电路部分实际上可以包括适当地耦合的分离的电路或电路部分。例如,在实施例中驱动器电路104可以包括高侧部分114和低侧部分115。因此本文并且在图1中提到的电路部分不是限制性的并且在本文用于说明的目的。而且,即使特定的示例被描绘和讨论,在一些实施例中特定的示例电路部分也可以由其它电路补充或者替代。
驱动器电路104的参考点被设置到高侧晶体管110的源极。这种驱动器电路104经常被称作浮动驱动器,其可以在许多实施方式中提供益处,包括用于驱动级的较低的击穿电压,BVDSS,以及对于高和低侧晶体管110和112两者使用单一电源的能力。在实施例中,晶体管110和112包括功率晶体管。
然而,许多降压转换器使用另外的部件,例如自举电路102。在实施例中,自举电路102包括电容器,Cboost,和二极管,Dboost。在其它实施例中,Dboost可以被自举晶体管替代,其在本文下面被讨论。Cboost为高侧驱动器114提供浮动电源,充当能量存储元件,同时Dboost充当用于浮动电压的块元件(block element)。在实施例中,Dboost包括肖特基二极管。在实施例中Cboost包括基于半导体的电容器,而不是电解、陶瓷或其它电容器类型。
在操作中,在低侧晶体管112的接通时间期间,通过Dboost将Cboost充电到驱动电压。一旦高侧晶体管110的接通时间开始,存储在Cboost中的电荷通过驱动器114被转移到高侧晶体管110的输入电容器。在高侧晶体管110被开启的时候,在源极电势处的电压上升;假定Cboost不放电,在Dboost的阴极处的电压也将上升。因此,两个电压将同时上升直到高侧晶体管110被完全地开启为止,产生“浮动”电源。
在实施例中,Cboost和Dboost与驱动器部分104和MOSFET部分106中的至少一个集成。在一个实施例中,Cboost和Dboost与在相同的封装120中的部分104和106集成。在实施例中,封装120也可以包括其它电路、电路部分和元件。
例如,在图2A中高侧电路106a,驱动器电路104,自举电路102和低侧电路106b被集成在封装120中。在实施例中,如被描绘的每个电路部分被实现在单独的硅管芯上。在其它实施例中,一个或多个部分可以被进一步集成。例如,在图2B中,自举电路102和低侧电路106b被布置在相同的管芯122上。在图2C中,高侧电路106a和自举电路102被布置在相同的管芯124上,同时在图2D中自举电路102和驱动器电路104被布置在管芯126上。在其它实施例中可以实现其它布置。例如,在实施例中高侧电路106a,驱动器104和自举电路102可以被实现在单一管芯上。特定的组合可以根据应用,技术,或者一些其它的因素来变化。例如,图2C的实施例可以是有利的,因为自举电路102支持高侧电路106a的驱动,但是图2B的实施例可以在技术上更容易实现。在另一实施例中,Cboost和Dboost与另一电路部分单片地集成。在又一实施例中,在图2A-2D中描绘的部分中的一个或多个可以与所述部分中的另一个或一些其它电路垂直地堆叠,一个管芯在另一个的顶部上。然而,与特定的布置无关,在实施例中自举部分102与其它电路部分集成在封装120中。
在还有的其它实施例中,自举电路102可以与其它电路部分单片地集成。在实施例中,这可以使用横向MOSFET工艺,使用氮化镓(GaN)和碳化硅(SiC)的技术等等来实现。在示例实施例中,使用功率MOSFET工艺,例如分裂式沟槽功率MOSFET的工艺流程,然而其它工艺和技术也可以具有优点。例如,相对于单位面积价格来说,横向MOSFET可以是廉价的,并且相对于重写来说提供较高的自由度,虽然可能需要用于自举电路的另外的工艺,其增加了成本。材料如GaN和SiC可能在高频应用方面是有利的。与使用的工艺无关,除了前面提到的封装级集成实施例,各种实施例提供用于单片地集成自举电路元件的机会。
在浮动驱动器实施例中,例如关于图1和2C讨论的其中自举部分102与高侧部分106a集成的实施例,自举部分102的集成在实施例中通常包括三个级:电容器级,二极管或晶体管级,和其中高侧晶体管110与自举部分102耦合的电连接级。虽然可以以这个顺序来实施各级,但是它们不需要在所有的实施例中。
在电容器级的实施例中,沟槽被用来形成Cboost。沟槽可以与在功率MOSFET中使用的其它沟槽相同或者不同,其在实施例中可以包括n沟道MOSFET。参照图3,在实施例中沟槽被蚀刻到在302处的硅衬底中。在304处,沟槽被涂覆有介电层,例如氧化硅,氮化硅,其组合,或者一些其它电介质,例如具有比氧化硅的介电常数更高的介电常数的电介质,并且在306处导电材料,例如高度掺杂的硅,填充沟槽。在实施例中以这个方式形成的电容器可以适合于低侧集成。
在图4A中描绘这种电容器400的示例。电容器400与在图4A的实施例中的低侧集成,其中自举电容器,Cboost,形成于在实施例中包括硅的体电极402和通过利用导电材料404填充沟槽406来形成的电极之间。介电层405分离体电极402和由材料404填充沟槽406形成的电极。寄生电容116可以形成在第一和第二金属层408和410之间,然而这个电容116可以是良好的虽然Cboost的经常可忽略的部分。在实施例中在金属层之间的绝缘层412可以包括氧化硅,氮化硅,氧化物,氮化物或者一些其它合适的绝缘材料。在另一实施例中,氮化物层可以被加入到沟槽406,使得其包括在体电极402和电极404之间的氧化物-氮化物-氧化物堆叠。
参照图4B和4C,与电容器400相似的沟槽电容器420也可以包括散射氧化物422,其隔离沟槽424和在使用中通常耦合到供给电压的n型衬底426的漏极电势,使得电容器420适合于高侧集成。因此,在实施例中,电容器420包括围绕沟槽424的p阱。可以以几个不同的方法来形成p阱。例如,可以实施在沟槽蚀刻之后的注入,例如如在图4B和4C中描绘的倾斜注入,以便充分到达沟槽404的侧面。在图4B中,发生来自第一方向的注入,紧接着是来自图4C中的第二方向的注入。注入的特定倾斜角度可以在实施例中变化。
在另一实施例中,沟槽424的侧面可以以一定角度形成,例如通常朝向沟槽的底部向内成斜坡或者在侧面上为“V”形状。当垂直注入将到达成斜坡的侧面以及沟槽的底部时,于是倾斜的注入通常不是必要的。在其它实施例中,可以沉积掺杂的材料,紧接着是扩散过程和随后的去除。例如,在一个实施例中掺杂的材料仅被沉积。在另一实施例中,第一层被沉积,然后掺杂层被沉积。实施热步骤以驱使掺杂剂从掺杂层通过第一层以产生阱。例如,如果掺杂层是p掺杂的,这个过程产生p掺杂的阱,在其后可以去除被掺杂的层和第一层。在其它实施例中,n和p布置可以被反过来,并且在这个实施例和本文讨论的其它实施例中正是如此。沟槽424可以被填充有导电材料以完成电容器420。
在图4D和4E中描绘电容器420的其它实施例。在图4D中,电容器420包括两个金属化层430和432以耦合到两个电极422和428,其中于其间描绘的电容再次是Cboost的电势附加的部件。在其它实施例中,可以实现单一金属化。在图4E中,隔离层422被延伸用于与金属化层430的不同的耦合布置。
在实施例中,Cboost是约100nF至约200nF。在其它实施例中,Cboost的电容量可以是更大或者更小,例如在实施例中在约50nF至约1μF的范围中,或者在其它实施例中在约200nF至约1μF的范围中。Cboost的大小可以在实施例中取决于高侧输入电容。因此,当硅工艺改进和/或其它材料(例如GaN)被实施时,在实施例中Cboost可能比前面提到的示例甚至更小并且是非限制性范围。例如,在实施例中可以根据其它电路部分104和106的要求和可用面积来优化Cboost的大小和其它特征。在实施例中,除其它之外,可以如下面讨论的那样来实施沟槽、电介质和导电电极的优化。
关于沟槽,在实施例中可以使用两个不同的蚀刻工艺用于电容器沟槽和晶体管沟槽,换句话说是Cboost和高侧晶体管110或低侧晶体管112中的至少一个。较深沟槽通常提供较高电容密度,使得具有双沟槽工艺的一个方法将使用两个连续的光刻步骤用于晶体管沟槽和电容器沟槽的蚀刻。参照图5,描绘工艺流程的一个示例实施例。在图5A中,外延层504被形成在衬底层502上。硬掩模506,例如氧化物,被施加于层504,并且光致抗蚀剂层508被施加用于待实施的第一光刻步骤。将变成沟槽的光致抗蚀剂层508中的间距,以及开口和最终沟槽本身的尺寸可以不同于在图5中描绘的那些。例如,如果接触将被放置在沟槽上,那么沟槽的尺寸可以被调整到更大或者可以使用局部接触延伸。在图5B中,在第一光致抗蚀剂层508已经被去除并且此处用于Cboost的两个沟槽510已经被蚀刻之后,光致抗蚀剂层512已经被施加在将形成用于晶体管的第二组沟槽的区域中。在图5C中,光致抗蚀剂层516已经被施加在沟槽510的区域中同时沟槽514已经被蚀刻。在图5D中,硬掩模层506已经被去除,并且用于电容器和用于晶体管的两组沟槽510,514已经被形成。在实施例中,沟槽510和514的宽度,深度,配置和其它方面可以与所描绘的不同并且彼此不同,例如减少或防止在沟槽层之间的不对准或者除根据所选择的布局所需的任何尺寸以外的沟槽510和514之间的关键尺寸的变化。
关于电容器的介电层(例如,参照图3,或者图4中的电容器400),实施例中的优化可以涉及层的厚度。在沟槽功率MOSFET的形成的传统工艺中,介电层形成场氧化物或者栅极氧化物。因为由电容器经历的电压通常比漏极到源极的电压更低,尤其对于分裂式栅极晶体管,较薄的介电层可以有益于增加比电容。因此,在实施例中,可以至少部分地从电容器沟槽蚀刻介电层。然后可以接着沉积或者生长新的电介质。在实施例中,并且如前面讨论的,电介质包括氧化硅,然而在其它实施例中可以使用其它电介质材料。
导电电极,例如在图4中填充沟槽424的导电材料428,在实施例中可以包括重n掺杂的多晶硅材料,其中电容器与低侧集成。在其它实施例中,可以在沟槽424中形成pn二极管,使得可以使用允许反向掺杂(counter-doping)的较低掺杂的硅,具有沉积并且然后是n和/或p掺杂的通孔注入的未掺杂的硅的未掺杂的电极,或者具有相反掺杂的电极。
在图6中描绘单片地集成电容器(例如自举电容器Cboost)和沟槽MOSFET器件的另一实施例。在图6的实施例中,Cboost和低侧集成,然而取决于p阱被短路到n外延层还是分离的焊盘,高侧集成也是可能的。在实施例中,替代地,p阱可以被省略,而不是被短路。在图6A中,描绘在沟槽蚀刻之后的MOSFET沟槽514和电容器沟槽510。在实施例中,使用相同的硬掩模蚀刻沟槽。在图6B中沉积或者生长氧化物层602。在其它实施例中,可以在层602中使用除了氧化物以外的电介质或者电介质堆叠,如由本领域技术人员领会到的。在实施例中,氧化物层602可以例如在电容器沟槽的区域中被部分地去除,并且可以沉积或者生长新的氧化物层。这个第二氧化物层可以在实施例中比氧化物层602更薄或更厚,和/或其也可以形成不同的电介质堆叠。在图6C中,其在实施例中可以是可选的,多晶硅层604,例如p多晶硅被沉积并且被掺杂,并且该掺杂然后扩散到主硅层504中以形成p阱603(参见图6D)。在另一实施例中,可以使用原位掺杂。在图6D中,氧化物层602形成电介质并且多晶硅填充沟槽510以形成场电极。在图6E中描绘的替代实施例中,去除多晶硅层604,并且形成另一氧化物层606,使得场电极保留在有源沟槽中并且栅极电极可被用于电容器。在实施例中,也可以以后去除多晶硅层604和/或不需要完全地填充沟槽510。
在另一实施例中,场板可以为在衬底的主体中的电荷提供镜像电荷,允许衬底的本体的较高掺杂并且减少接通器件的电阻率,然而在一些实施例中这种场板被不同地使用或者根本不被使用,例如包括单一多晶硅(poly)MOSFET的那些实施例。在实施例中,在晶体管沟槽中生长或者沉积电介质,例如场氧化物或栅极氧化物,在其之后可以生长热氧化物的薄层,或者可以沉积薄的四乙基原硅酸盐(TEOS)层,以用作用于多晶硅沉积的定义的扩散势垒。在这些步骤之间,可以在实施例中至少部分地去除初始的氧化物层。原位掺杂的多晶硅可以被沉积在这个薄层上以充当n或p扩散源和/或场板电极。在掺杂驱使形成电容器阱之后,多晶硅可以被留作电容器电极或被去除。如果多晶硅被去除,也可以从电容器沟槽中去除电介质,在其之后可以定义电容器电介质,例如氧化物-氮化物-氧化物(ONO)。在实施例中,在生成场氧化物或者栅极氧化物之后实施形成阱的步骤以便避免与温度处理相关的问题,然而在其它实施例中这些步骤可以在之前而不是在之后被实施。
接下来,将讨论产生自举二极管Dboost。在实施例中,Dboost可以被嵌入在电容器沟槽内,其可以节省面积。在一个实施例中,标准的pn结被形成在电容器的电极之间,包括n掺杂的多晶硅,和p掺杂的多晶硅层。可以在实施例中通过n掺杂的多晶硅的反向掺杂或者通过可跟随n掺杂的多晶硅的各部分的蚀刻的沉积来形成p掺杂的多晶硅区。在这种pn结的实施例中,蚀刻沟槽可以被形成在p掺杂的多晶硅层中并且被填充有n掺杂的硅。在另一实施例中,掺杂可以被反过来。然后在空间电荷区域两端形成的电容可以被用作Cboost。
在实施例中,Dboost可以包括约8,000μm2的面积,然而这只是一个示例并且在其它实施例中可以更小或更大。在实施例中Dboost的RDSon可以是约8欧姆,产生约50mA的电流,然而这只是一个示例,其可在其它实施例中变化。在实施例中Dboost的最大操作或者击穿电压可以是约28V,然而这只是一个示例,并且本领域技术人员将领会到本文提供的这些和其它尺寸、电压以及其它值和特征是示例并且不被认为是限制性的,因为许多可以是与应用相关的或者根据其它因素变化。Dboost的这些和其它特征,以及本文关于其它部件提供的其它特征只是示例并且不被认为是限制性的。
在其它实施例中,Dboost可以被自举晶体管Tboost代替。图7A描绘图1的电路100,其中根据实施例Tboost代替Dboost。其它电路元件与在图1中的相似或者相同,然而本领域技术人员将领会到耦合配置可以被相应地更新。在实施例中,Tboost包括PFET,其中其漏极耦合到Vsupply,源极耦合到Cboost并且栅极耦合到驱动器114。在其它实施例中,Tboost包括以相同的或者类似适合的方式耦合的一些其它晶体管器件,取决于使用的特定的晶体管器件,例如横向FET,包括GaN的HEMT,和其它合适的器件。照此耦合,在实施例中在操作中Tboost类似于肖特基二极管来起作用。在实施例中使用MOSFET Tboost的一个优点是例如晶体管两端的比二极管更低的电压降。
还参照图7B,描绘Cboost和Tboost的单片集成的示例实施例。在这个实施例中,Tboost包括pMOS FET。Cboost和Tboost被形成在共同的衬底702中,在图7B中其是n掺杂的。Tboost被形成在p阱704中,其是Tboost的漏极。本领域技术人员将领会到在其它实施例中特定的掺杂配置可以变化,并且在图7B中描绘的实施例仅是一个示例。而且,在图7B中,以及在本文的其它图中的描绘有点被简化,并且没有特定地描绘优化和其它特征。金属化层706形成在介电层708上用于各种器件的接触。第一接触706a形成用于Cboost的两个接触中的一个,并且第二接触706b也与Tboost的源极耦合。另一接触706c与p阱704,Tboost的漏极耦合。
在图7B中描绘的单片集成的变型也是可能的,例如其中使用背面漏极接触或者实现其它接触配置的实施例。另外,如在图7C的示例实施例中描绘的,实施例也可以包括NFET。
回到自举二极管实施例,可以形成金属或多晶硅的肖特基接触。这种实施例的一个优点是较低的正向电压,其可以在Cboost的充电期间减少损耗。在图8中的802处描绘这种肖特基接触。包括另一欧姆接触804用以将金属线806和808耦合到焊盘,管脚或其它电路元件。例如,图8的实施例可被最容易地集成到与图4A的低侧相关的低侧中,然而在实施例中高侧集成也是可能的。在图4中使用的参考数字在此也被用来指示图中的相同或相似的部分。另外,图8以及图9和10未按比例绘制,因为沟槽406以及器件400整体的长度可以是非常长。
在图9中描绘另一耦合布置,其是包括沟槽的高侧集成实施例,包括例如如在图4D和4E中的另外的阱或隔离层422。在图4D和4E中使用的参考数字在此也被用来指示图中的相同或相似的部分。也包括第二欧姆接触812以及第三金属线814以提供到第二电极的需要的另外耦合。例如,参照图4D和4E和与高侧集成实施例相关的讨论。在未被描绘的另一高侧集成实施例中,单一阱422被实现用于两个沟槽428并且可以包括单一接触。
在图10中,描绘又一耦合布置,其中两个接触802和804是欧姆的,并且掺杂区816围绕接触802中的一个。例如,如果衬底426是n掺杂的,那么掺杂区816是p掺杂的。或者,如果衬底426是p掺杂的,那么掺杂区816是n掺杂的。如在图10中描绘的,掺杂区816可以包括沟槽406的较小部分,或者在其它实施例中反向掺杂可以填充沟槽406的较大部分。
在图8-10中,接触(例如接触802,804和812)的特定放置可以在实施例中变化,并且被描绘的位置和放置仅是示例。本领域技术人员将领会到这个接触放置以及不同的接触放置可以影响或者确定其它元件(例如掺杂区等)的放置。
实施例提供对于传统方法的许多改进和优点。例如,单片地和/或在与根据本文讨论的一个或多个实施例的其它电路元件相同的封装中集成自举电路可以提供减小的电路元件尺寸,其又可以减少栅极电荷以改善开关损耗。当频率增加时,部件通常必须变得更小,其可以为应用提供机会。而且,集成自举电路提供简化的设计,减少的面积要求,降低的寄生以及由于这些中的一个或多个而减少的成本。也提供相对于传统的封装中系统或模块方法的优点,其需要另外的空间和复杂性并且不提供基于半导体的集成电路实施例可以提供的较高的集成度。
实施例也更普遍地涉及基于半导体的电容器和其它元件与功率晶体管的集成,包括单片集成。虽然那些电容器和其它元件可以包括自举电路或者形成自举电路的一部分,它们也可以包括其它非自举元件。这个集成提供优于传统方法的优点,包括仅使用模块的封装中系统配置而没有进一步集成(例如单片集成)的那些。因此,本文关于自举电路或元件描绘和讨论的实施例也更加普遍地适用于与功率晶体管和其它器件的电路元件集成,不管那些电路元件是不是自举电路元件,并且与自举电路相关的示例,包括自举电容器,自举二极管,和自举晶体管,不是限制性的。
本文已经描述了系统,器件和方法的各种实施例。这些实施例仅作为示例给出并且不旨在限制本发明的范围。而且,应该领会到已经描述的实施例的各种特征可以以多种方式组合来产生许多另外的实施例。而且,虽然已经描述了多种材料,尺寸,形状,配置和位置等供公开的实施例使用,但是可以利用除了公开的那些以外的其它材料,尺寸,形状,配置和位置等而不会超出本发明的范围。
相关领域的普通技术人员将认识到本发明可以包括比在上面描述的任何单个实施例中图示的更少的特征。本文描述的实施例不意味着是其中本发明的各种特征可以被组合的方式的详尽的表示。因此,实施例不是互相排斥的特征组合;更确切地,本发明可以包括从不同的各实施例中选择的不同的各特征的组合,如由本领域普通技术人员理解的。而且,关于一个实施例描述的元件可以被实现在其它实施例中,即使当在这样的实施例中未被描述,除非另外说明。尽管从属权利要求可以在权利要求中引用与一个或多个其它权利要求的特定组合,其它实施例也可以包括从属权利要求与每个其它从属权利要求的主题的组合或者一个或多个特征与其它从属或独立权利要求的组合。本文提出这样的组合,除非声明特定的组合不是预期的。此外,也旨在包括在任何其它独立权利要求中的权利要求的特征,即使这个权利要求不是直接地从属于该独立权利要求。
通过引用上面文献的任何并入是被限制的,使得没有与本文明确的公开相反的主题被并入。通过引用上面文献的任何并入被进一步限制,使得本文通过引用没有并入在文献中包括的权利要求。通过引用上面文献的任何并入被更进一步限制,使得本文通过引用没有并入在文献中提供的任何定义,除非本文明确地包括。
为了解释本发明的权利要求的目的,明确地旨在不援引35 U.S.C的112节,第六段的规定,除非在权利要求中阐述了特定术语“用于……的装置”或“用于……的步骤”。
Claims (26)
1.一种半导体器件,包括:
封装;和
集成电路,其被布置在所述封装中并且包括互相耦合的至少一个晶体管器件和自举电路,所述自举电路包括基于半导体的自举电容器器件。
2.权利要求1的集成电路,其中所述至少一个晶体管器件包括功率晶体管器件。
3.权利要求2的集成电路,其中所述至少一个晶体管器件包括金属氧化物半导体场效应晶体管(MOSFET)器件的一个。
4.权利要求3的集成电路,其中所述至少一个晶体管器件是具有高侧部分和低侧部分的浮动驱动器电路的一部分,并且其中所述自举电路至少部分地与所述高侧部分或所述低侧部分中的一个集成。
5.权利要求2的集成电路,其中所述至少一个晶体管器件包括氮化镓(GaN)或碳化硅(SiC)中的至少一个。
6.权利要求2的集成电路,其中利用所述至少一个晶体管器件单片地形成所述自举电路。
7.权利要求2的集成电路,其中所述自举电容器器件包括在硅衬底中形成的沟槽,并且其中所述自举电容器器件的第一电极包括所述硅衬底并且所述自举电容器器件的第二电极包括在所述沟槽内并且通过介电层与所述沟槽分离的导电材料。
8.权利要求2的集成电路,其中所述自举电容器器件包括在硅衬底中形成的沟槽,并且其中掺杂阱围绕所述沟槽并且形成所述自举电容器器件的第一电极,并且所述自举电容器器件的第二电极包括在所述沟槽内并且通过介电层与所述沟槽分离的导电材料。
9.权利要求1的集成电路,其中所述自举电路包括自举二极管器件或自举晶体管器件中的一个。
10.权利要求9的集成电路,其中所述自举晶体管器件包括MOSFET器件。
11.权利要求9的集成电路,其中所述自举二极管器件包括肖特基二极管器件。
12.一种集成电路,包括:
半导体功率晶体管;和
包括利用所述半导体功率晶体管单片地形成的半导体电容器的电路。
13.权利要求12的集成电路,其中所述电路包括自举电路。
14.权利要求12的集成电路,进一步包括其中设置所述半导体功率晶体管和所述电路的封装。
15.权利要求12的集成电路,其中所述半导体功率晶体管包括金属氧化物半导体场效应晶体管(MOSFET),氮化镓(GaN)晶体管,或碳化硅(SiC)晶体管中的一个。
16.权利要求12的集成电路,其中所述半导体功率晶体管和所述电路被单片地形成在硅衬底中,其中所述电路的至少一个沟槽和所述半导体功率晶体管的至少一个沟槽在所述硅衬底中具有不同的深度,并且使用相同的硬掩模来执行所述电路的所述至少一个沟槽和所述半导体功率晶体管的所述至少一个沟槽的蚀刻。
17.权利要求12的集成电路,其中所述半导体功率晶体管和所述电路被单片地形成在硅衬底中,并且其中氧化物层被形成在所述硅衬底上并且第一层被形成在所述氧化物层上,并且其中所述第一层的掺杂扩散到所述硅衬底中。
18.权利要求17的集成电路,其中所述第一层包括多晶硅或者氧化物中的至少一个。
19.一种方法,包括:
形成至少一个晶体管器件;和
利用所述至少一个晶体管器件单片地形成基于半导体的自举电容器元件;和
将所述单片地形成的至少一个晶体管器件和自举电容器元件设置在封装中。
20.权利要求19的方法,其中形成至少一个晶体管器件包括形成至少一个功率晶体管器件。
21.权利要求20的方法,其中所述至少一个功率晶体管器件包括金属氧化物硅场效应晶体管(MOSFET)器件,碳化硅(SiC)晶体管器件或氮化镓(GaN)晶体管器件中的至少一个。
22.权利要求21的方法,其中利用所述至少一个晶体管器件单片地形成基于半导体的自举电容器元件进一步包括:
通过驱使第一类型的掺杂通过介电层并且进入到具有与所述第一类型不同的第二类型的掺杂的硅衬底中来形成所述自举电容器的阱,作为形成所述MOSFET器件的工艺的一部分。
23.权利要求22的方法,进一步包括去除所述介电层。
24.权利要求19的方法,其中形成基于半导体的自举电容器元件进一步包括利用所述至少一个晶体管器件单片地形成自举晶体管或自举二极管中的至少一个。
25.权利要求19的方法,其中形成基于半导体的自举电容器元件进一步包括在硅衬底中蚀刻至少一个沟槽,并且其中形成至少一个晶体管器件进一步包括在所述硅衬底中蚀刻至少一个沟槽,其中所述自举电容器元件的至少一个沟槽和所述至少一个晶体管器件的所述至少一个沟槽被蚀刻到所述硅衬底的不同深度。
26.权利要求25的方法,进一步包括使用相同的硬掩模来蚀刻所述自举电容器元件的所述至少一个沟槽和所述至少一个晶体管器件的所述至少一个沟槽。
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US11605955B2 (en) | 2014-09-16 | 2023-03-14 | Navitas Semiconductor Limited | Half-bridge circuit using GaN power devices |
US11757290B2 (en) | 2014-09-16 | 2023-09-12 | Navitas Semiconductor Limited | Half-bridge circuit using flip-chip GaN power devices |
US11888332B2 (en) | 2014-09-16 | 2024-01-30 | Navitas Semiconductor Limited | Half-bridge circuit using monolithic flip-chip GaN power devices |
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US10897142B2 (en) | 2014-09-16 | 2021-01-19 | Navitas Semiconductor Limited | Half bridge circuit with bootstrap capacitor charging circuit |
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US10944270B1 (en) | 2014-09-16 | 2021-03-09 | Navitas Semiconductor Limited | GaN circuit drivers for GaN circuit loads |
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US10396579B2 (en) | 2014-09-16 | 2019-08-27 | Navitas Semiconductor, Inc. | GaN circuit drivers for GaN circuit loads |
CN105448909A (zh) * | 2014-09-19 | 2016-03-30 | 三垦电气株式会社 | 自举电路 |
CN107078736A (zh) * | 2014-10-10 | 2017-08-18 | 宜普电源转换公司 | 高电压零反向恢复电荷自举供应器 |
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CN104467371A (zh) * | 2014-12-12 | 2015-03-25 | 上海数明半导体有限公司 | 一种自举电路 |
US11935845B2 (en) | 2019-10-31 | 2024-03-19 | Guangdong Midea White Home Appliance Technology Innovation Center Co., Ltd. | Semiconductor device, preparation method therefor and electrical equipment thereof |
CN112750899B (zh) * | 2019-10-31 | 2022-05-27 | 广东美的白色家电技术创新中心有限公司 | 一种半导体器件及其制备方法、电器设备 |
WO2021082209A1 (zh) * | 2019-10-31 | 2021-05-06 | 广东美的白色家电技术创新中心有限公司 | 一种半导体器件及其制备方法、电器设备 |
CN112750899A (zh) * | 2019-10-31 | 2021-05-04 | 广东美的白色家电技术创新中心有限公司 | 一种半导体器件及其制备方法、电器设备 |
Also Published As
Publication number | Publication date |
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DE102013114346A1 (de) | 2014-06-18 |
DE102013114346B4 (de) | 2016-05-19 |
US9171738B2 (en) | 2015-10-27 |
US20140167069A1 (en) | 2014-06-19 |
US9530773B2 (en) | 2016-12-27 |
US20160043072A1 (en) | 2016-02-11 |
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