JP7327672B2 - 半導体装置 - Google Patents
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Description
[先行技術文献]
[特許文献]
[特許文献1] 特開2018-195798号公報
[特許文献2] 国際公開第2018/052098号パンフレット
コンタクト領域は、メサ部において、第1エミッタ領域の第1トレンチ部側の下端の下方に設けられてよい。
コンタクト領域は、メサ部において、第2エミッタ領域のゲートトレンチ部側の下端の下方にも設けられてよい。
本例の半導体装置100は、d-d'断面において、半導体基板10、層間絶縁膜38、エミッタ電極52およびコレクタ電極24を有する。エミッタ電極52は、半導体基板10および層間絶縁膜38の上方に形成される。また、本例の半導体装置100は、ドリフト領域18とベース領域14との間に蓄積領域16を有する。
Claims (20)
- ゲートトレンチ部と、第1トレンチ部と、を備える半導体装置であって、
半導体基板に設けられた第1導電型のドリフト領域と、
前記ドリフト領域の上方に設けられた第2導電型のベース領域と、
前記ベース領域の上方に設けられ、前記ドリフト領域よりもドーピング濃度の高い第1導電型のエミッタ領域と、
前記ベース領域の上方に設けられ、前記ベース領域よりもドーピング濃度の高い第2導電型のコンタクト領域と、
を備え、
前記ゲートトレンチ部と前記第1トレンチ部との間のメサ部において、前記コンタクト領域は、トレンチ配列方向と平行な断面において、前記エミッタ領域の下端の下方に設けられ、かつ、前記トレンチ配列方向において、前記下端の下方から前記ゲートトレンチ部へと延伸し、前記ゲートトレンチ部に到達せずに終端し、
前記第1トレンチ部は、ダミートレンチ部、ダミーゲートトレンチ部、および前記ゲートトレンチ部のいずれかを含み、
前記エミッタ領域は、前記メサ部において、前記ゲートトレンチ部と接する、
半導体装置。 - 前記コンタクト領域は、前記第1トレンチ部に接する
請求項1に記載の半導体装置。 - 前記メサ部において、前記コンタクト領域は、前記エミッタ領域の下面と接する、
請求項1または2に記載の半導体装置。 - 前記コンタクト領域は、前記トレンチ配列方向において、前記ゲートトレンチ部と0.6μm以上離間されている、
請求項3に記載の半導体装置。 - 前記コンタクト領域は、前記第1トレンチ部の側壁において、前記半導体基板のおもて面に設けられる
請求項1から4のいずれか一項に記載の半導体装置。 - 前記半導体基板の上方に設けられた層間絶縁膜を備え、
前記エミッタ領域は、前記層間絶縁膜を貫通して設けられたコンタクトホールを介してエミッタ電極に電気的に接続される、
請求項1から5のいずれか一項に記載の半導体装置。 - 前記エミッタ領域は、前記トレンチ配列方向において、前記ゲートトレンチ部から、前記コンタクトホールを越えて前記第1トレンチ部側へと延伸する、
請求項6に記載の半導体装置。 - 前記ドリフト領域と前記ベース領域との間に、前記ドリフト領域よりドーピング濃度の高い第1導電型の蓄積領域を備える、
請求項1から7のいずれか一項に記載の半導体装置。 - 複数の前記ゲートトレンチ部と、複数の前記第1トレンチ部とを備え、
前記第1トレンチ部は、前記ダミートレンチ部および/または前記ダミーゲートトレンチ部であり、
複数の前記ゲートトレンチ部の数と、複数の前記第1トレンチ部の数との比は1:1である、
請求項1から8のいずれか一項に記載の半導体装置。 - 複数の前記ゲートトレンチ部と、複数の前記第1トレンチ部とを備え、
前記第1トレンチ部は、前記ダミートレンチ部および/または前記ダミーゲートトレンチ部であり、
複数の前記ゲートトレンチ部の数と、複数の前記第1トレンチ部の数との比は1:2である、
請求項1から8のいずれか一項に記載の半導体装置。 - 前記エミッタ領域は、前記トレンチ配列方向において、前記ゲートトレンチ部から前記第1トレンチ部へと延伸し、前記第1トレンチ部に到達せずに終端する、
請求項1から10のいずれか一項に記載の半導体装置。 - 前記第1トレンチ部は、前記ダミートレンチ部であり、
前記エミッタ領域は、前記トレンチ配列方向において、前記ゲートトレンチ部から前記第1トレンチ部まで延伸する、
請求項1から10のいずれか一項に記載の半導体装置。 - 前記半導体装置のおもて面において、前記ゲートトレンチ部のトレンチ延伸方向に対して、前記コンタクト領域と前記エミッタ領域とが交互に接して設けられる、
請求項12に記載の半導体装置。 - 前記第1トレンチ部は、第1トレンチ絶縁膜と第1トレンチ導電部を有し、
前記第1トレンチ部は、前記ダミートレンチ部であり、
前記第1トレンチ導電部は、エミッタ電位もしくはフローティング電位に設定される、
請求項1から13のいずれか一項に記載の半導体装置。 - 前記第1トレンチ部は、第1トレンチ絶縁膜と第1トレンチ導電部を有し、
前記第1トレンチ部は、前記ダミーゲートトレンチ部および/または前記ゲートトレンチ部であり、
前記第1トレンチ導電部はゲート電位に設定される、
請求項1から11のいずれか一項に記載の半導体装置。 - 前記第1トレンチ部は、前記ダミーゲートトレンチ部である、
請求項1から11のいずれか一項に記載の半導体装置。 - 前記第1トレンチ部は、前記ダミートレンチ部である、
請求項1から11のいずれか一項に記載の半導体装置。 - 前記第1トレンチ部は前記ゲートトレンチ部であり、
前記エミッタ領域は、第1エミッタ領域と第2エミッタ領域とを有し、
前記メサ部において、前記第1エミッタ領域は、前記第1トレンチ部と対向する前記ゲートトレンチ部と接し、前記第1トレンチ部と離間しており、
前記メサ部において、前記第2エミッタ領域は、前記第1トレンチ部と接し、前記第1トレンチ部と対向する前記ゲートトレンチ部と離間している
請求項1に記載の半導体装置。 - 前記トレンチ配列方向において、前記コンタクト領域は、前記第1トレンチ部と対向する前記ゲートトレンチ部側における、前記第2エミッタ領域の下端の下方から前記第1トレンチ部へと延伸し、前記第1トレンチ部に到達せずに終端する
請求項18に記載の半導体装置。 - 前記ゲートトレンチ部および前記第1トレンチ部のトレンチ延伸方向において、前記第1エミッタ領域と前記第2エミッタ領域とが交互に設けられる
請求項19に記載の半導体装置。
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