WO2017155122A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2017155122A1 WO2017155122A1 PCT/JP2017/009843 JP2017009843W WO2017155122A1 WO 2017155122 A1 WO2017155122 A1 WO 2017155122A1 JP 2017009843 W JP2017009843 W JP 2017009843W WO 2017155122 A1 WO2017155122 A1 WO 2017155122A1
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- semiconductor device
- semiconductor substrate
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- diode
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Definitions
- the present invention relates to a semiconductor device.
- a semiconductor device may comprise a semiconductor substrate.
- the semiconductor substrate may have a drift region of the first conductivity type.
- the semiconductor substrate may have a base region of the second conductivity type provided above the drift region.
- the semiconductor device may include a transistor portion formed on a semiconductor substrate.
- the semiconductor device may include a diode portion formed on the semiconductor substrate adjacent to the transistor portion.
- a plurality of trench portions may be formed in the transistor portion and the diode portion along the predetermined arrangement direction. In the transistor portion and the diode portion, a plurality of mesa portions may be formed between the respective trench portions.
- At least one boundary mesa portion at the boundary between the transistor portion and the diode portion among the plurality of mesa portions may have a contact region of the second conductivity type higher in concentration than the base region on the upper surface of the semiconductor substrate.
- the area of the contact area at the boundary mesa may be larger than the area of the contact area at the other mesa.
- an accumulation region having a concentration higher than that of the drift region may be provided between the base region and the drift region.
- a storage region may not be provided in at least one of the boundary mesas.
- the trench adjacent to the boundary mesa may be a dummy trench.
- at least one trench portion provided closer to the transistor portion than the trench portion adjacent to the boundary mesa portion may be a dummy trench portion.
- the accumulation area may have a first accumulation area formed at a predetermined depth position.
- the storage region may have a second storage region formed closer to the diode portion than the first storage region and shallower than the first storage region.
- the trench portion adjacent to the second accumulation region may be a dummy trench portion.
- the diode portion may have a lifetime killer on the upper surface side of the semiconductor substrate.
- the transistor portion may not have the lifetime killer on the upper surface side of the semiconductor substrate in the region where the first accumulation region is formed.
- the boundary mesa may have a lifetime killer on the top side of the semiconductor substrate.
- the mesa portion closer to the transistor portion than the boundary mesa portion may have an emitter region of the first conductivity type higher in concentration than the drift region and a contact region on the upper surface of the semiconductor substrate.
- the boundary mesa may not have an emitter region.
- At least a part of the mesa portion closer to the diode portion than the boundary mesa portion may have a base region on the upper surface of the semiconductor substrate.
- the distance from the boundary between the transistor portion and the diode portion to the mesa portion having the emitter region and the trench portion between the boundary mesa portion is Da, and the distance from the lower surface of the semiconductor substrate to the lower surface of the base region is Dt.
- 100 ⁇ m ⁇ Da + Dt ⁇ 150 ⁇ m may be satisfied.
- Each trench portion may be formed to extend in the extension direction different from the arrangement direction on the upper surface of the semiconductor substrate.
- the mesa portion closer to the transistor portion than the boundary mesa portion may have emitter regions and contact regions alternately along the extending direction on the upper surface of the semiconductor substrate.
- the storage region may be formed to the outside of the end of the outermost formed emitter region in the extending direction.
- the semiconductor device may further include an interlayer insulating film formed on the upper surface of the semiconductor substrate.
- the interlayer insulating film may have a contact hole for exposing the emitter region and the contact region. In the extending direction, the contact hole may be formed outside the end of the accumulation region.
- a semiconductor device may comprise a semiconductor substrate.
- the semiconductor substrate may have a drift region of the first conductivity type.
- the semiconductor substrate may have a base region of the second conductivity type provided above the drift region.
- the semiconductor device may be provided with a trench portion formed extending in a predetermined extending direction on the upper surface of the semiconductor substrate and penetrating the base region.
- an emitter region of a first conductivity type higher in concentration than the drift region and a concentration higher than the base region are alternately formed in the region adjacent to the trench portion on the upper surface of the semiconductor substrate along the extending direction.
- a contact region of the second conductivity type may include a storage region of the first conductivity type formed between the base region and the drift region and having a higher concentration than the drift region. The storage region may be formed to the outside of the end of the outermost formed emitter region in the extending direction.
- the semiconductor device may further include an interlayer insulating film formed on the upper surface of the semiconductor substrate.
- the interlayer insulating film may have a contact hole for exposing the emitter region and the contact region. In the extending direction, the contact hole may be formed outside the end of the accumulation region. The end of the accumulation region in the stretching direction may be formed at a position shallower toward the outside.
- the semiconductor device of the second aspect may further include a well region of a second conductivity type higher in concentration than the base region, formed outside the contact region on the upper surface of the semiconductor substrate.
- a base region may be formed between the contact region and the well region on the top surface of the semiconductor substrate. In the extension direction, the distance from the end of the emitter region to the end of the accumulation region may be shorter than the distance from the end of the accumulation region to the end of the contact hole.
- At least a partial area below the emitter area may have a carrier passage area in which the storage area is not formed.
- a carrier passage area may be provided in the entire area below the emitter area.
- the carrier passage region may be provided below the end of the contact region adjacent to the emitter region.
- the accumulation area may have a first accumulation area formed at a predetermined depth position.
- the storage region may have a second storage region formed closer to the emitter region than the first storage region and shallower than the first storage region. Both the first accumulation region and the second accumulation region may be formed below the contact region.
- the semiconductor device may further include an interlayer insulating film formed on the upper surface of the semiconductor substrate.
- the interlayer insulating film may have a contact hole for exposing the emitter region and the contact region. In the extending direction, the accumulation region may be formed outside the end of the contact hole.
- a semiconductor device may comprise a semiconductor substrate.
- the semiconductor substrate may have a drift region of the first conductivity type.
- the semiconductor substrate may have a base region of the second conductivity type provided above the drift region.
- the semiconductor device may be provided with a trench portion formed extending in a predetermined extending direction on the upper surface of the semiconductor substrate and penetrating the base region.
- the semiconductor device is formed on the upper surface of the semiconductor substrate in a region adjacent to the trench portion, and is alternately formed along the extending direction, and has a higher concentration than the emitter region and the base region of the first conductivity type higher than the drift region. And a contact region of a second conductivity type.
- the semiconductor device may include a storage region of the first conductivity type formed between the base region and the drift region and having a higher concentration than the drift region.
- the semiconductor device may include an interlayer insulating film formed on the upper surface of the semiconductor substrate.
- the interlayer insulating film may have a contact hole for exposing the emitter region and the contact region. In the extending direction, the contact hole may be formed outside the end of the accumulation region.
- the transistor unit and the diode unit in the semiconductor device of the first aspect may further include a collector region of the second conductivity type.
- the collector region may be provided at least below the outermost contact region provided in the extending direction different from the arranging direction.
- the transistor unit may further include a storage region of the first conductivity type.
- An accumulation region may be provided between the base region and the drift region.
- the accumulation region may be of the first conductivity type higher in concentration than the drift region.
- the inner end of the collector region of the diode portion may be located inside the outer end of the storage region of the transistor portion.
- the transistor portion in the semiconductor device of the first aspect may further include an emitter region of the first conductivity type.
- the emitter region may be of a first conductivity type that is more heavily doped than the drift region.
- the inner end of the collector region of the diode portion may be located inside the outer end of the emitter region provided outermost in the extending direction in the transistor portion.
- the semiconductor device in the semiconductor device of the second and third aspects may further include a transistor portion and a diode portion.
- the transistor portion may be formed on a semiconductor substrate.
- the diode portion may be formed on the semiconductor substrate adjacent to the transistor portion.
- the transistor portion and the diode portion may further include a collector region of the second conductivity type.
- the collector region may be provided at least below the outermost contact region in the extending direction.
- the inner end of the collector region of the diode portion may be located inside the outer end of the storage region of the transistor portion.
- the inner end of the collector region of the diode portion may be located inside the outer end of the emitter region provided outermost in the extending direction in the transistor portion.
- FIG. 2 is a top view showing an example of a semiconductor device 100.
- FIG. 2 is a view showing an example of a cross section aa ′ of the semiconductor device 100 shown in FIG. 1;
- FIG. 7 is a view showing another example of the aa ′ cross section of the semiconductor substrate 10;
- FIG. 5 is a view for explaining the size of a predetermined portion in the semiconductor substrate 10 shown in FIG. 2 or 3;
- FIG. 2 is a view showing an example of the bb ′ cross section of the semiconductor device 100 shown in FIG. 1;
- FIG. 6 is an enlarged view of the vicinity of an end 98 of the accumulation region 16 in the cross section shown in FIG. 5; It is a figure showing an example of semiconductor device 200 concerning a comparative example.
- FIG. 1 is a view showing an example of a cross section aa ′ of the semiconductor device 100 shown in FIG. 1
- FIG. 7 is a view showing another example of the aa ′ cross section of the semiconductor substrate 10
- FIG. 31 is a top view showing an example of a semiconductor device 300. It is a figure which shows an example of the cc 'cross section in FIG.
- FIG. 9 is a view showing an example of a dd 'cross section in FIG. 8; It is a figure which shows an example of the ee 'cross section in FIG. It is a figure which shows an example of the cross section of the mesa 94 in a surface parallel to a YZ surface. It is a figure which shows the other example of the cross section of the mesa 94 in a surface parallel to a YZ surface.
- FIG. 31 is a top view showing an example of a semiconductor device 400.
- FIG. 9 is a view showing an example of a dd 'cross section in FIG. 8; It is a figure which shows an example of the ee 'cross section in FIG. It is a figure which shows an example of the cross section of the mesa 94 in a surface parallel to a YZ surface
- FIG. 15 is a view showing an example of a cross section taken along line cc 'of the semiconductor device 400 shown in FIG. 14;
- FIG. 31 is a top view showing an example of a semiconductor device 500.
- FIG. 17 is a view showing an example of a cross section aa ′ of the semiconductor device 500 shown in FIG. 16;
- FIG. 1 is a top view showing an example of a semiconductor device 100.
- the semiconductor device 100 of this example is a semiconductor chip having a transistor unit 70 including a transistor such as an IGBT (Insulated Gate Bipolar Transistor) and a diode unit 80 including a diode such as a FWD (Free Wheel Diode).
- the diode unit 80 is formed adjacent to the transistor unit 70 on the upper surface of the semiconductor substrate.
- the upper surface of the semiconductor substrate refers to one of two opposing main surfaces of the semiconductor substrate. In FIG. 1, the top surface of the chip around the chip end is shown, and the other regions are omitted.
- the diode portion 80 is projected when the cathode region is projected perpendicularly to the back surface of the semiconductor substrate with respect to the back surface region coinciding with the cathode region or the front surface side. It may be an area.
- the transistor portion 70 is a projection region when the collector region is projected perpendicularly to the back surface of the semiconductor substrate on the front surface side in the active region, and includes the emitter region 12 and the contact region 15.
- the unit structure of may be an area regularly arranged.
- FIG. 1 shows the active region of the semiconductor substrate in the semiconductor device 100
- the semiconductor device 100 may have an edge termination portion surrounding the active region.
- the active region indicates a region through which current flows when the semiconductor device 100 is controlled to be in an on state.
- the edge termination alleviates the concentration of the electric field on the upper surface side of the semiconductor substrate.
- the edge end has, for example, a guard ring, a field plate, a resurf, and a combination of these.
- the semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 17, an emitter region 12, a base region 14 and a contact region 15 formed inside the upper surface side of the semiconductor substrate.
- the semiconductor device 100 of this example includes the emitter electrode 52 and the gate electrode 50 provided above the upper surface of the semiconductor substrate. Emitter electrode 52 and gate electrode 50 are provided separately from each other.
- the gate trench portion 40 and the dummy trench portion 30 are an example of the trench portion.
- An interlayer insulating film is formed between the emitter electrode 52 and the gate electrode 50 and the upper surface of the semiconductor substrate, but is omitted in FIG.
- a contact hole 54, a contact hole 55 and a contact hole 56 are formed through the interlayer insulating film in the interlayer insulating film of this example.
- Emitter electrode 52 is in contact with emitter region 12, contact region 15 and base region 14 on the top surface of the semiconductor substrate through contact hole 54. Further, emitter electrode 52 is connected to the dummy conductive portion in dummy trench portion 30 through contact hole 56. Between the emitter electrode 52 and the dummy conductive portion, a connection portion 57 formed of a conductive material such as polysilicon doped with an impurity may be provided. The connection portion 57 is formed on the upper surface of the semiconductor substrate. An insulating film such as a thermal oxide film is formed between the connection portion 57 and the semiconductor substrate.
- Gate electrode 50 is in contact with gate interconnection 51 through contact hole 55.
- Gate interconnection 51 is formed of polysilicon or the like doped with an impurity. Gate interconnection 51 is connected to the gate conductive portion in gate trench portion 40 on the upper surface of the semiconductor substrate. That is, gate interconnection 51 is formed on the upper surface of the semiconductor substrate, between a portion of gate trench portion 40 and contact hole 55.
- Emitter electrode 52 and gate electrode 50 are formed of a material containing a metal.
- each electrode is formed of aluminum or aluminum-silicon alloy.
- Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like, and may have a plug formed of tungsten or the like in the contact hole.
- the one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged in the region of the transistor portion 70 at predetermined intervals along a predetermined arrangement direction.
- one or more gate trench portions 40 and one or more dummy trench portions 30 may be alternately formed along the arrangement direction. Further, the dummy trench portions 30 are arranged at predetermined intervals in the arrangement direction in the region of the diode portion 80.
- the dummy trench portion 30 is formed to extend in a predetermined extending direction on the upper surface of the semiconductor substrate.
- a part of the dummy trench portion 30 in the transistor portion 70 of the present example has a linear shape, and is formed extending in the extending direction perpendicular to the above-described arrangement direction.
- a part of the dummy trench portion 30 in the transistor portion 70 has a shape in which two straight lines are connected at the end portion by a curved portion.
- the X axis direction is taken as the arrangement direction of the trench portions.
- the Y-axis direction is taken as the extending direction of the trench portion.
- the X axis and the Y axis are axes orthogonal to each other in a plane parallel to the top surface of the semiconductor substrate.
- an axis orthogonal to the X axis and the Y axis is taken as a Z axis.
- the Z-axis direction may be referred to as the depth direction.
- a plurality of dummy trench sections 30 may be continuously arranged at the boundary with the diode section 80.
- the number of dummy trench portions 30 continuously arranged at the boundary with the diode portion 80 may be larger than the number of dummy trench portions 30 continuously arranged inside the transistor portion 70 separated from the diode portion 80 .
- a total of three dummy trench sections 30 of two connected at the end and one linear shape are continuously arranged. (The dummy trench portion 30 overlapping the boundary between the transistor portion 70 and the diode portion 80 is not counted).
- the gate trench portions 40 and the dummy trench portions 30 are alternately arranged one by one.
- the gate trench portion 40 has an opposing portion 41 and a projecting portion 43.
- the facing portion 41 is formed to extend in the above-described extending direction in a range facing the dummy trench portion 30 in the transistor portion 70. That is, the facing portion 41 is formed in parallel to the dummy trench portion 30.
- the protruding portion 43 is further extended from the facing portion 41 and is formed in a range not facing the dummy trench portion 30.
- two opposing portions 41 provided on both sides of the dummy trench portion 30 are connected by one projecting portion 43. At least a portion of the protrusion 43 may have a curvilinear shape.
- the gate conductive portion in the gate trench portion 40 and the gate wiring 51 are connected.
- the gate wire 51 may be connected to the gate conductive portion in a region farthest from the facing portion 41 of the protrusion 43.
- the projecting portion 43 in this example has a portion that extends in a direction orthogonal to the facing portion 41 in a region farthest from the facing portion 41.
- the gate wire 51 may be connected to the gate conductive portion at the corresponding portion of the protrusion 43.
- the dummy trench portion 30 in the diode portion 80 may have the same shape as the dummy trench portion 30 in the gate trench portion 40, and may have the same shape as the gate trench portion 40. However, dummy trench portion 30 in diode portion 80 has the same length as dummy trench portion 30 in transistor portion 70.
- Emitter electrode 52 is formed above gate trench portion 40, dummy trench portion 30, well region 17, emitter region 12, base region 14 and contact region 15.
- the well region 17 is formed in a predetermined range from the end of the active region on the side where the gate electrode 50 is provided.
- the diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30.
- a partial region of gate trench portion 40 and dummy trench portion 30 on the side of gate electrode 50 is formed in well region 17. The bottom of the end in the extension direction of the dummy trench portion 30 may be covered by the well region 17.
- the projecting portion 43 of the gate trench portion 40 may be entirely formed in the well region 17.
- the semiconductor substrate has a first conductivity type, and the well region 17 has a second conductivity type different from the semiconductor substrate.
- the semiconductor substrate of this example is N ⁇ type, and the well region 17 is P + type.
- the first conductivity type is described as N-type, and the second conductivity type is described as P-type.
- the first and second conductivity types may be opposite conductivity types.
- the base region 14 is formed in the mesa portion 94 which is a region sandwiched by the respective trench portions. Furthermore, the mesa portion 94 is a region sandwiched by adjacent trench portions along the arrangement direction, from the deepest position on the bottom surface of the trench portion to the upper surface (that is, the front surface) of the semiconductor substrate Good.
- the base region 14 is a second conductivity type having a doping concentration lower than that of the well region 17.
- the base region 14 in this example is P-type.
- a contact region 15 of the second conductivity type having a doping concentration higher than that of the base region 14 is formed on the top surface of the base region 14 in the mesa portion 94.
- the contact region 15 in this example is P + type.
- the emitter region 12 of the first conductivity type having a doping concentration higher than that of the semiconductor substrate is selectively formed on a part of the upper surface of the contact region 15.
- the emitter region 12 in this example is N + type.
- Each of contact region 15 and emitter region 12 is formed from one adjacent trench portion to the other trench portion.
- the one or more contact regions 15 and the one or more emitter regions 12 of the transistor portion 70 are formed to be alternately exposed on the upper surface of the mesa portion 94 along the extension direction of the trench portion.
- the contact region 15 is formed in a region facing the at least one contact region 15 in the transistor unit 70.
- the contact region 15 is formed in the region facing the contact region 15 closest to the gate electrode 50 in the transistor unit 70, and the base is provided in the other region. Region 14 is formed.
- the contact hole 54 is formed above each of the contact region 15 and the emitter region 12.
- the contact hole 54 is not formed in the region corresponding to the base region 14 and the well region 17.
- the contact hole 54 is formed above the contact region 15 and the base region 14.
- the contact hole 54 in the present example is not formed in the base region 14 closest to the gate electrode 50 among the plurality of base regions 14 in the mesa portion 94 of the diode portion 80.
- the contact holes 54 of the transistor section 70 and the contact holes 54 of the diode section 80 have the same length in the extending direction of the respective trench sections.
- the contact region 15 is formed at the end in the extension direction of the contact hole 54, but the contact region 15 may be omitted.
- the contact region 15 may be formed on the surface of the base region 14 exposed by the contact hole.
- At least one boundary mesa portion 94-1 at the boundary between the transistor portion 70 and the diode portion 80 among the plurality of mesa portions 94 is a P + -type contact region having a concentration higher than that of the base region 14 on the upper surface of the semiconductor substrate.
- the area of the contact region 15 exposed to the upper surface of the semiconductor substrate in the boundary mesa portion 94-1 is larger than the area of the contact region 15 exposed to the upper surface of the semiconductor substrate in the other mesa portion 94.
- one mesa portion 94 on the transistor portion 70 side adjacent to the boundary between the transistor portion 70 and the diode portion 80 is the boundary mesa portion 94-1.
- boundary mesa portion 94-1 in addition to the region where contact region 15 is formed in another mesa portion 94 of transistor portion 70, the region where emitter region 12 is formed in another mesa portion 94 of transistor portion 70. Also, the contact region 15 is formed. That is, the boundary mesa 94-1 in this example does not have the emitter region 12 on the upper surface of the semiconductor substrate.
- the mesa portion 94 closer to the diode portion 80 than the boundary mesa portion 94-1 has the base region 14 on the upper surface of the semiconductor substrate.
- a region facing the contact region 15 in the boundary mesa portion 94-1 is also the base region 14.
- the base region 14 functions as an anode region of the diode.
- an accumulation region 16 is formed below the base region 14 in a partial region of the transistor section 70.
- a region in which the storage region 16 is formed is indicated by a dotted line.
- a cathode region 82 is formed below the base region 14 in a partial region of the diode unit 80.
- a region where the cathode region 82 is formed is indicated by a dotted line.
- the cathode region 82 may be at a position where the base region 14 exposed on the upper surface (that is, the front surface) of the semiconductor substrate is projected on the lower surface of the semiconductor substrate. That is, the cathode region 82 may be separated from the position where the contact region 15 formed at the end of the contact hole 54 in the trench extension direction is projected onto the lower surface (that is, the back surface) of the semiconductor substrate.
- FIG. 2 is a view showing an example of the aa ′ cross section of the semiconductor device 100 shown in FIG.
- the aa ′ cross section is a cross section parallel to the XZ plane and passing through the emitter region 12 of the transistor section 70.
- the mask 110 used at the time of manufacture of the semiconductor device 100 is shown collectively.
- the semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 26, the emitter electrode 52, and the collector electrode 24 in the cross section.
- Emitter electrode 52 is formed on the upper surface of semiconductor substrate 10 and interlayer insulating film 26.
- the collector electrode 24 is formed on the lower surface of the semiconductor substrate 10.
- the lower surface refers to the surface opposite to the upper surface.
- Emitter electrode 52 and collector electrode 24 are formed of a conductive material such as metal.
- the surface or end of the emitter electrode 52 side of each member such as a substrate, layer, or region is referred to as the upper surface or the upper end, and the surface or end of the collector electrode 24 is referred to as the lower surface or the lower end.
- a direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.
- the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride.
- a P ⁇ -type base region 14 is formed on the upper surface side of the semiconductor substrate 10.
- the N + -type emitter region 12, the P ⁇ -type base region 14 and the N + -type storage region 16 are sequentially arranged from the upper surface side of the semiconductor substrate 10 on the upper surface side of each mesa portion 94 of the transistor portion 70. It is formed.
- a P ⁇ -type base region 14 is formed on the upper surface side of each of the mesa portions 94 of the diode portion 80.
- the storage region 16 is not formed in each mesa portion 94 of the diode portion 80.
- an N ⁇ -type drift region 18 is formed on the lower surface of the accumulation region 16.
- the storage region 16 is formed in each mesa 94 of the transistor unit 70.
- the storage region 16 may be provided to cover the entire lower surface of the base region 14 in each mesa 94. However, in the mesa portion 94 in the vicinity of the boundary between the transistor portion 70 and the diode portion 80, the lower surface of the base region 14 is not covered by the accumulation region 16.
- the drift region 18 is formed on the lower surface of the base region 14.
- an N ⁇ -type buffer region 20 is formed on the lower surface of the drift region 18.
- the buffer region 20 is formed on the lower surface side of the drift region 18.
- the doping concentration of buffer region 20 is higher than the doping concentration of drift region 18.
- Buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of base region 14 from reaching P + type collector region 22 and N + type cathode region 82.
- a P + type collector region 22 is formed on the lower surface of the buffer region 20.
- an N + -type cathode region 82 is formed on the lower surface of the buffer region 20.
- a plane parallel to the YZ plane passing through the boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80.
- the boundary between the collector region 22 and the cathode region 82 may be a position where the distribution of the net doping concentration of the impurity in the X-axis direction has a minimum value.
- One of the dummy trench portions 30 may be formed at the boundary between the transistor portion 70 and the diode portion 80. Further, the position of the dummy trench portion 30 closest to the position where the net doping concentration becomes the minimum value in the X axis may be taken as the boundary position of the transistor portion 70 and the diode portion 80.
- a collector electrode 24 is provided on the lower surface of the collector region 22 and the cathode region 82.
- One or more gate trench portions 40 and one or more dummy trench portions 30 are formed on the upper surface side of the semiconductor substrate 10. Each trench portion penetrates base region 14 from the upper surface of semiconductor substrate 10 to reach drift region 18. In the region where at least one of the emitter region 12, the contact region 15 and the storage region 16 is provided, each trench also penetrates these regions to reach the drift region 18.
- the gate trench portion 40 has a gate trench formed on the upper surface side of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44.
- the gate insulating film 42 is formed to cover the inner wall of the gate trench.
- the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
- the gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10.
- the gate conductive portion 44 is formed of a conductive material such as polysilicon.
- Gate conductive portion 44 includes a region facing at least adjacent base region 14 in the Z-axis direction. Gate trench portion 40 is covered with interlayer insulating film 26 on the upper surface of semiconductor substrate 10. In this example, as shown in FIG. 1, the gate conductive portion 44 in the projecting portion 43 is electrically connected to the gate electrode 50 through the gate wiring 51. When a predetermined voltage is applied to gate conductive portion 44, a channel is formed in the surface layer of the interface of base region 14 in contact with the gate trench.
- the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section.
- the dummy trench portion 30 has a dummy trench formed on the upper surface side of the semiconductor substrate 10, a dummy insulating film 32 and a dummy conductive portion 34.
- the dummy insulating film 32 is formed to cover the inner wall of the dummy trench.
- the dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32.
- the dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10.
- the dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.
- the dummy conductive portion 34 is formed of a conductive material such as polysilicon.
- the dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.
- the dummy trench portion 30 is covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10.
- the dummy conductive portion 34 is electrically connected to the emitter electrode 52 through the contact hole 56.
- the emitter region 12 exposed on the upper surface of the semiconductor substrate 10 is not formed in the boundary mesa portion 94-1 at the boundary between the transistor portion 70 and the diode portion 80 among the plurality of mesa portions 94.
- a contact region 15 exposed on the top surface of 10 is formed. As shown in FIG. 1, it is preferable that the emitter region 12 exposed on the top surface of the semiconductor substrate 10 is not formed in the entire boundary mesa portion 94-1.
- the contact region 15 of the boundary mesa portion 94-1 is connected to the emitter electrode 52 through the contact hole 54.
- the mesa portion 94 at the boundary between the transistor portion 70 and the diode portion 80 refers to the mesa portion 94 overlapping the boundary in the X-axis.
- the mesa 94 adjacent to the boundary between the transistor unit 70 and the diode unit 80 refers to the mesa 94 adjacent to the trench.
- the mesa portion 94 on the transistor portion 70 side is the boundary mesa portion 94-1.
- a plurality of mesa portions 94 continuous in the arrangement direction may be the boundary mesa portion 94-1 adjacent to the boundary between the transistor portion 70 and the diode portion 80. Further, the mesa portion 94 adjacent to the boundary on the diode portion 80 side may be the boundary mesa portion 94-1.
- the boundary mesa portion 94-1 By providing the boundary mesa portion 94-1, holes can be efficiently extracted near the boundary between the transistor portion 70 and the diode portion 80 when the semiconductor device 100 is turned off. Thus, it is possible to efficiently reduce the tail current at turn-off and to reduce the loss at the off-state. In addition, the decrease in withstand voltage of the semiconductor device 100 can be suppressed. Further, it is possible to suppress the holes accumulated in the region of the transistor portion 70 from flowing to the region of the diode portion 80, and to reduce the influence on the diode portion 80.
- the storage region 16 is not provided in at least one of the boundary mesas 94-1.
- no storage region 16 is provided in all boundary mesas 94-1.
- holes can be drawn out at the boundary mesa 94-1 without being blocked by the accumulation region 16.
- the mask 110 is used in the step of implanting an impurity into a region corresponding to the storage region 16.
- the mask 110 is disposed to cover the diode portion 80 and the boundary mesa portion 94-1.
- the mask 110 may be formed by applying a resist or the like and patterning it into a predetermined shape.
- the storage area 16 is not formed in the area covered by the mask 110, and the storage area 16 is formed in the area not covered by the mask 110.
- the end of the mask 110 is preferably formed vertically at a position facing the end of the boundary mesa 94-1. However, if resist mask or the like occurs on the mask 110, the excess portion 112 may be formed beyond the position.
- the storage region 16 is not formed at a predetermined depth in the mesa portion 94 covered by the excess portion 112. For example, in the mesa portion 94 covered by the excess portion 112, the accumulation region 16 is not formed at all or formed shallower than a predetermined depth.
- the storage area 16 of this example includes a first storage area 16-1 and a second storage area 16-2.
- the first accumulation region 16-1 is formed at a predetermined depth position.
- the first accumulation region 16-1 is formed inside the transistor unit 70.
- the second accumulation region 16-2 is formed at a position closer to the diode unit 80 than the first accumulation region 16-1.
- the second accumulation region 16-2 is formed at a position shallower than the first accumulation region 16-1. That is, the second accumulation region 16-2 is formed on the upper surface side of the semiconductor substrate 10 than the first accumulation region 16-1.
- the second storage region 16-2 may be formed to be shallow as it approaches the diode unit 80.
- the first accumulation region 16-1 and the second accumulation region 16-2 may be formed continuously or may be formed discontinuously in the depth direction.
- the depth position of the storage region 16 changes, the length in the depth direction of the base region 14 in the mesa portion 94 changes. Therefore, when the gate trench portion 40 is provided adjacent to the mesa portion 94, the threshold voltage Vth of the mesa portion 94 fluctuates with respect to the threshold voltage Vth of the other mesa portions 94. Variations in threshold voltage will increase. In addition, the variation in saturation current also increases. In addition, the forward voltage of the diode unit 80 may be lower than a predetermined design value.
- the trench portion adjacent to the boundary mesa portion 94-1 is the dummy trench portion 30. Further, at least one trench portion provided adjacent to the transistor portion 70 side further than the trench portion adjacent to the boundary mesa portion 94-1 is the dummy trench portion 30. Thereby, variations in threshold voltage can be reduced. More preferably, all the trench portions adjacent to the mesa portion 94 provided with the second accumulation region 16-2 are the dummy trench portions 30. In addition, it is preferable that all the trench portions closer to the diode portion 80 than the mesa portion 94 provided with the second accumulation region 16-2 be the dummy trench portions 30. Thereby, variations in threshold voltage can be further reduced.
- the trench portion adjacent to the first storage region 16-1 is a gate trench portion. 40 may be sufficient.
- the trench portion adjacent to the second storage region 16-2 is preferably the dummy trench portion 30.
- FIG. 3 is a view showing another example of the aa ′ cross section of the semiconductor substrate 10.
- a lifetime killer 96 is further provided in addition to the configuration of the semiconductor substrate 10 shown in FIG. 2, a lifetime killer 96 is further provided. Further, in the semiconductor substrate 10 of FIG. 3, a plurality of boundary mesa portions 94-1 are formed. Other structures may be identical to the example shown in FIG.
- the lifetime killer 96 is provided on the upper surface side of the semiconductor substrate 10.
- the upper surface side of the semiconductor substrate 10 refers to the upper surface side of at least the middle of the drift region 18 in the depth direction.
- the lifetime killer 96 may be formed on the entire diode unit 80. Thereby, the carrier lifetime in the diode unit 80 can be adjusted, and for example, the diode unit 80 can be made to perform a soft recovery operation.
- the lifetime killer 96 may be any one that can locally adjust the carrier lifetime of the semiconductor substrate 10 in the depth direction. For example, the lifetime killer 96 is helium locally injected into the semiconductor substrate 10.
- the lifetime killer 96 of this example is also formed in the region adjacent to the diode unit 80 in the transistor unit 70. However, in the transistor section 70, the lifetime killer 96 is not formed below the area where the first accumulation area 16-1 is formed. Thereby, it is possible to prevent the IE effect by the accumulation area 16 from being offset by the lifetime killer 96.
- the lifetime killer 96 of this example is not formed below the mesa portion 94 in which the first accumulation region 16-1 is formed. Further, the lifetime killer 96 may not be formed below the at least one mesa portion 94 adjacent to the diode portion 80 with respect to the mesa portion 94 in which the first storage region 16-1 is formed. This makes it possible to reduce the influence of the lifetime killer 96 on the IE effect.
- a lifetime killer 96 may be formed below at least the one boundary mesa 94-1 on the side of the diode 80.
- the lifetime killer 96 is formed below all the boundary mesas 94-1. Thereby, the influence of the carriers in the transistor unit 70 on the diode unit 80 can be reduced.
- the lifetime killer 96 may be formed below the mesa portion 94 in which the second accumulation region 16-2 is formed.
- the area where the lifetime killer 96 is formed may end below the area where the second accumulation area 16-2 is formed.
- FIG. 4 is a diagram for explaining the size of a predetermined portion in the semiconductor substrate 10 shown in FIG. 2 or FIG.
- the distance from the boundary between the transistor unit 70 and the diode unit 80 in the X-axis direction to the dummy trench 30-2 between the mesa unit 94-2 having the emitter region 12 and the boundary mesa unit 94-1 is Da I assume.
- the position of dummy trench portion 30 indicates the center position of dummy trench portion 30 in the X-axis direction.
- the distance from the dummy trench portion 30-2 to the dummy trench portion 30-3 is Db.
- the dummy trench portion 30-3 refers to the dummy trench portion 30 closest to the transistor portion 70 among the dummy trench portions 30 continuously arranged on the transistor portion 70 side from the boundary between the transistor portion 70 and the diode portion 80.
- a distance from the lower surface of the semiconductor substrate 10 to the lower surface of the base region 14 in the Z-axis direction is Dt.
- the thickness of the mask 110 is Dc.
- the distance between the mesa portion 94-2 and the cathode region 82 can be secured. Therefore, it is possible to suppress the fluctuation of the forward voltage in diode portion 80 due to the formation of storage region 16 in mesa portion 94-2. Further, by setting Da + Dt ⁇ 150 ⁇ m, the size of the invalid region which does not function as a transistor can be limited in the transistor section 70. As an example, Dt may be about 70 ⁇ m.
- the length in the X-axis direction of the excess portion 112 of the mask 110 depends on the thickness Dc of the mask 110.
- Db> 1.2 Dc the trench portion adjacent to the region where the second storage region 16-2 is likely to be formed can be used as the dummy trench portion 30. Therefore, variations in threshold voltage and saturation current can be reduced.
- Db may be 6 ⁇ m or more.
- 2.0 Dc> Db may be satisfied, and 1.5 Dc> Db may be satisfied.
- FIG. 5 is a view showing an example of the bb ′ cross section of the semiconductor device 100 shown in FIG.
- the bb ′ cross section is a plane parallel to the YZ plane, and is a plane passing through the connecting portion 57 at the mesa portion 94 closer to the transistor portion 70 than the boundary mesa portion 94-1.
- the storage region 16 is formed in the mesa portion 94. Further, in FIG. 5, the positions of the contact holes 54 formed to face the cross section are indicated by dotted lines.
- the mesa portion 94 alternately has emitter regions 12 and contact regions 15 along the extending direction of the trench portion on the upper surface of the semiconductor substrate 10. Further, a storage region 16 is formed on the lower surface of the base region 14.
- the end position of the storage region 16 on the outermost side (that is, the gate electrode 50 side) in the Y-axis direction is P1.
- the outermost end position of the contact hole 54 in the Y-axis direction is P2.
- An end position of the emitter region 12 formed on the outermost side in the Y-axis direction on the side of the gate electrode 50 is P3.
- An end position of the contact region 15 formed on the outermost side in the Y-axis direction on the gate electrode 50 side is P4.
- the storage region 16 is preferably formed to the outside of the end of the emitter region 12 formed on the outermost side in the Y-axis direction. That is, it is preferable that the end position P1 of the storage region 16 be disposed outside the end position P3 of the emitter region 12. Thereby, the IE effect in the accumulation region 16 can be enhanced.
- the contact hole 54 is preferably formed to the outside of the accumulation region 16 in the Y-axis direction. That is, the end position P2 of the contact hole 54 is preferably disposed outside the end position P1 of the accumulation region 16. As a result, when the semiconductor device 100 is turned off, holes can be efficiently extracted from the outside of the storage region 16.
- the contact region 15 formed on the outermost side in the Y-axis direction be formed to the outside of the contact hole 54. That is, the end position P4 of the contact region 15 is preferably disposed outside the end position P2 of the contact hole 54. As a result, when the semiconductor device 100 is turned off, holes can be efficiently extracted from the outside of the storage region 16.
- the distance from the end position P3 of the emitter region 12 to the end position P1 of the storage region 16 is shorter than the distance from the end position P1 of the storage region 16 to the end position P4 of the contact region 15 Good.
- the storage region 16 can suppress inhibition of hole extraction.
- the concentration of the electric field at the end of the accumulation region 16 can be alleviated.
- the distance from the end position P3 to P1 is preferably shorter than the distance from the end position P1 of the accumulation region 16 to the end position P2 of the contact hole 54.
- the distance from the end position P3 of the emitter region 12 to the end position P1 of the accumulation region 16 is 12 ⁇ m or less. Further, the distance from the end position P1 of the accumulation region 16 to the end position P2 of the contact hole 54 is 20 ⁇ m or less. The distance from the end position P2 of the contact hole 54 to the end position P4 of the contact region 15 is 1 ⁇ m or less.
- the semiconductor device 100 including the diode unit 80 has been described with reference to FIGS. 1 to 4.
- the semiconductor device 100 shown in FIG. 5 may or may not include the diode unit 80. Even without the diode unit 80, the semiconductor device 100 can exhibit the above-described effects.
- a base region 14 is formed between the outermost contact region 15 and the well region 17 on the upper surface of the semiconductor substrate 10. That is, a region of relatively high resistance is arranged outside the contact region 15. Thereby, the carriers coming from the transistor unit 70 to the diode unit 80 can be reduced at the time of reverse recovery. Therefore, it is possible to suppress concentration of carriers on the end of the contact region 15 in the diode unit 80, and to suppress a decrease in withstand voltage of the diode unit 80.
- the length of the base region 14 between the contact region 15 and the well region 17 in the Y axis direction may be 10 ⁇ m or more and 50 ⁇ m or less.
- the end 98 of the accumulation region 16 may be formed shallower toward the outside in the Y-axis direction.
- the tip of storage region 16 in the Y-axis direction is formed at a position shallower than storage region 16 below emitter region 12.
- the tip of the accumulation region 16 may be formed at a position not in contact with the drift region 18.
- the tip of the accumulation area 16 may be provided at a position shallower than the middle of the base area 14 in the Z-axis direction.
- the storage region 16 in this example can be easily formed by using the mask 110 having the excess portion 112 described in FIG.
- the shape of the end 98 of the accumulation region 16 can be controlled by adjusting the shape of the excess portion 112 of the mask 110.
- the bake temperature of the mask 110, the bake time, the thickness of the mask 110, or the material may be adjusted.
- FIG. 7 is a view showing an example of the semiconductor device 200 according to the comparative example.
- the gate trench portion 40 is formed adjacent to the second storage region 16-2.
- variations in the threshold voltage Vth and the saturation current in the transistor portion 70 become large.
- the semiconductor device 100 since the dummy trench portion 30 is provided adjacent to the second storage region 16-2, variations in the threshold voltage Vth and the saturation current in the transistor portion 70 can be reduced.
- FIG. 8 is a top view showing an example of the semiconductor device 300. As shown in FIG. The semiconductor device 300 differs from the semiconductor device 100 of each aspect described in FIGS. 1 to 6 in the structure of the storage region 16. Other structures may be identical to those of the semiconductor device 100 of any aspect.
- the storage region 16 in the semiconductor device 300 is provided in at least a partial region below the contact region 15 and is not provided in at least a partial region below the emitter region 12.
- the storage region 16 in this example has a band shape extending along the X-axis direction.
- Band-shaped storage regions 16 are provided discretely along the Y-axis direction.
- each band-shaped storage region 16 is formed in a range overlapping the contact region 15 and not overlapping the emitter region 12.
- the width of the band-shaped storage region 16 in the Y-axis direction is smaller than the width of the contact region 15 in the Y-axis direction.
- FIG. 9 is a view showing an example of a cross section taken along line cc 'in FIG.
- the cc ′ cross section is a plane parallel to the XZ plane and passing through the emitter region 12. As described above, at least a part of the area below the emitter area 12 is provided with the carrier passage area 19 in which the storage area 16 is not formed.
- the carrier passage area 19 is an area where the mobility of holes is larger than that of the accumulation area 16.
- the carrier passage region 19 in this example refers to a region in the vicinity of the interface where the base region 14 remaining without the accumulation region 16 formed and the drift region 18 are in contact.
- the carrier passage region 19 may be provided over the entire width in the X-axis direction of the mesa portion 94.
- the carrier passage region 19 may include an N-type region having a lower doping concentration than the storage region 16 and a higher doping concentration than the drift region 18. In this case, the concentration of the N-type impurity in the carrier passage region 19 may be 1/10 or less or 1/100 or less of the concentration of the N-type impurity in the accumulation region 16.
- FIG. 10 is a view showing an example of the dd ′ cross section in FIG.
- the dd ′ cross section is a plane parallel to the XZ plane and passing through the contact region 15.
- the storage region 16 is formed in at least a partial region below the contact region 15.
- FIG. 11 is a view showing an example of a cross section along line e-e 'in FIG.
- the ee ′ cross section is a plane which is parallel to the YZ plane and passes through the connecting portion 57.
- the carrier passage region 19 is provided below the emitter region 12, and the storage region 16 is provided below the contact region 15.
- the carrier passage region 19 is provided in the entire region below the emitter region 12. That is, the width of the carrier passage region 19 in the Y-axis direction is equal to or greater than the width of the emitter region 12 in the Y-axis direction.
- the width of the carrier passage region 19 in the Y-axis direction may be larger than the width of the emitter region 12 in the Y-axis direction.
- the carrier passage region 19 is provided below the end of the contact region 15 in addition to the region below the emitter region 12.
- the end position of the storage region 16 on the outermost side (that is, the gate electrode 50 side) in the Y-axis direction is P1.
- the other end positions P2, P3 and P4 are the same as in the example of FIG.
- the storage region 16 in this example is formed to the outside of the end position P2 of the contact hole 54 in the Y-axis direction. That is, the end position P1 of the accumulation region 16 is disposed outside the end position P2 of the contact hole 54.
- the carrier passage region 19 is provided, even if the storage region 16 is formed to the outside of the contact hole 54, the decrease in withstand voltage can be suppressed. Further, by forming the accumulation region 16 to the outside of the contact hole 54, a constant carrier can be accumulated also in the end region.
- the end position P ⁇ b> 1 of the accumulation region 16 may be disposed inside the end position P ⁇ b> 4 of the contact region 15. Thereby, it is possible to suppress that the extraction of holes from the end region is inhibited by the accumulation region 16 at the turn-off time.
- FIG. 12 is a view showing an example of the cross section of the mesa portion 94 in a plane parallel to the YZ plane.
- the contact regions 15 and the emitter regions 12 are alternately arranged on the upper surface of the mesa portion 94 along the Y-axis direction.
- the carrier passage region 19 is also provided below the end 21 of the contact region 15 adjacent to the emitter region 12.
- the length L in the Y-axis direction of the portion where the carrier passage region 19 overlaps with one end 21 of the contact region 15 may be 10% or more, 20% or more of the width of the contact region 15 in the Y-axis direction. It may be The length L may be 30% or less of the width of the contact region 15 in the Y-axis direction.
- FIG. 13 is a view showing another example of the cross section of the mesa portion 94 in a plane parallel to the YZ plane.
- the storage area 16 of the present embodiment includes a first storage area 16-1 formed at a predetermined depth position and a second storage area 16-2 formed at a position shallower than the first storage area 16-1. And.
- the second accumulation region 16-2 is closer to the emitter region 12 than the first accumulation region 16-1 in the Y-axis direction. That is, the second accumulation region 16-2 is disposed between the first accumulation region 16-1 and the emitter region 12 in the Y-axis direction.
- the first accumulation region 16-1 is disposed between the base region 14 and the drift region 18.
- the second storage region 16-2 may be in contact with the contact region 15 or may be separated from the contact region 15. In addition, at least a part of the second storage region 16-2 may be formed in the contact region 15.
- the first accumulation region 16-1 and the second accumulation region 16-2 may be formed continuously or separated from each other.
- the shallow second storage region 16-2 may be formed below the excess portion 112.
- neither the first storage region 16-1 nor the second storage region 16-2 is formed below the contact region 15, and not below the emitter region 12. Therefore, even when the second storage region 16-2 is formed, the characteristics such as the threshold voltage of the semiconductor device 100 are not affected.
- the mask 110 is disposed such that the end of the mask 110 and the end of the contact region 15 overlap. Thereby, even if the excess portion 112 is generated in the mask 110, the second storage region 16-2 formed below the excess portion 112 can be arranged so as not to overlap with the emitter region 12.
- FIG. 14 is a top view showing an example of the semiconductor device 400.
- the outer end of the N + -type cathode region 82 is recessed in the positive Y-axis direction as compared with any of the semiconductor devices shown in FIGS. 1 to 13.
- the collector region 22 is not shown in FIG. 14, the transistor unit 70 and the diode unit 80 may have the collector region 22.
- the transistor portion 70 of this example has a collector region 22 on the entire surface on the lower surface side.
- the diode unit 80 of this example has the collector region 22 in a part of the lower surface side and the cathode region 82 in another part of the lower surface side. That is, on the lower surface side of the diode unit 80 of this example, the cathode region 82 is provided in the region where the collector region 22 is not provided.
- the inner end of the collector region 22 of the diode unit 80 may be located inside the outer end of the storage region 16 of the transistor unit 70, and the emitter provided at the outermost side in the Y axis direction in the transistor unit 70. It may be located inside the outer end of the region 12.
- the inner end of the collector region 22 of the diode unit 80 matches the outer end of the cathode region 82 of the diode unit 80.
- the length in the Y-axis direction from the inner end of the collector region 22 of the diode unit 80 to the outer end of the accumulation region 16 of the transistor unit 70 is referred to as L.
- the length L may be 200 ⁇ m.
- FIG. 15 is a view showing an example of a cross section along line cc 'of the semiconductor device 400 shown in FIG. FIG. 14 is a YZ cross section of the diode section 80.
- the dotted line in the vicinity of the contact region 15 indicates the position in the Y-axis direction of the outer end of the storage region 16 of the transistor section 70 in FIG.
- the boundary between the collector region 22 and the cathode region 82 is positioned in the positive Y-axis direction by the length L than the end portion outside the storage region 16 of the transistor section 70.
- the P + -type collector region 22 is expanded in the diode portion 80, holes can be easily injected from the collector region 22 to the drift region 18.
- holes can be easily injected from the collector region 22 to the drift region 18.
- the curved portion of the well region 17 shown in FIG. 15 is likely to generate an avalanche due to the concentration of the electric field, the avalanche can be suppressed by the hole injection from the back surface side.
- FIG. 16 is a top view showing an example of the semiconductor device 500. As shown in FIG. The semiconductor device 500 is provided with a boundary mesa portion 94-1 having a structure different from that of the semiconductor device 100 of each aspect described in FIGS. The other structure of the semiconductor device 500 may be the same as the semiconductor device 100 of any aspect.
- the boundary mesa portion 94-1 includes one or more boundary mesa portions 94-1A in which the area of the contact region 15 exposed to the upper surface of the semiconductor substrate on the side of the transistor portion 70 is larger than the exposed area of the base region 14. .
- the boundary mesa 94-1 may include a plurality of boundary mesas 94-1A. Further, in the boundary mesa portion 94-1, one area of the contact region 15 exposed to the upper surface of the semiconductor substrate on the side of the diode portion 80 is smaller than the exposed area of the base region 14 by one boundary mesa portion 94-1B.
- the boundary mesa 94-1 may include a plurality of boundary mesas 94-1B.
- the mesa portion 94 located closest to the diode portion 80 is adjacent to the boundary mesa portion 94-1A along the arrangement direction.
- the mesa portion 94 located closest to the transistor portion 70 is adjacent to the boundary mesa portion 94-1B in the arrangement direction.
- the boundary mesa portion 94-1A may be sandwiched by the dummy trench portion 30.
- the boundary mesa portion 94-1B may be sandwiched by the dummy trench portion 30.
- the distance from the end position P3 of the emitter region 12 to the end position P1 of the accumulation region 16 shown in FIG. 5 is Df. Further, the distance from the end position P1 of the accumulation region 16 to the end position P4 of the contact region 15 is taken as Dg.
- FIG. 17 is a view showing an example of the cross section aa ′ of the semiconductor device 500 shown in FIG.
- the aa ′ cross section is a cross section parallel to the XZ plane and passing through the emitter region 12 of the transistor section 70.
- the emitter electrode 52 and the collector electrode 24 are not shown.
- the boundary mesa portion 94-1A and the boundary mesa portion 94-1B have collector regions 22 on the lower surface (ie, the back surface) of the corresponding semiconductor substrate.
- the collector region 22 may extend from the transistor unit 70.
- FIG. 17 also shows distribution examples of the doping concentration (/ cm 3 ) and the defect concentration (/ cm 3 ) in the gg ′ cross section.
- the solid line in the concentration distribution indicates the doping concentration, and the dotted line indicates the defect concentration.
- boundary mesa portion 94-1A and boundary mesa portion 94-1B The distance to the dummy trench portion 30 between them is Dd.
- the distance between the dummy trench 30 between the boundary mesa 94-1A and the boundary mesa 94-1B and the boundary between the transistor 70 and the diode 80 is De.
- the position of dummy trench portion 30 indicates the center position of dummy trench portion 30 in the X-axis direction. Further, in the Z-axis direction, the distance from the lower surface of the semiconductor substrate 10 to the lower surface of the base region 14 is Dt.
- the distance Dd may be larger than the distance De.
- the minority carriers are holes in this example.
- the distance De may be larger than the distance Dd.
- the diode section 80 When the diode section 80 is in a conductive state, minority carriers are injected from both of the boundary mesa 94-1A and the boundary mesa 94-1B. In the boundary mesa portion 94-1A, the area ratio of the contact region 15 which is higher in concentration than the base region 14 is larger than that of the boundary mesa portion 94-1B. Therefore, when the diode unit 80 is in the conductive state, the concentration of minority carriers becomes high at the end of the boundary mesa unit 94-1 and the trench unit arrangement direction of the diode unit 80, and destruction at the time of reverse recovery may easily occur.
- the distance De By making the distance De larger than the distance Dd, the boundary mesa portion 94-1A and the cathode region 82 can be separated, and the increase in the concentration of minority carriers can be suppressed.
- the sum (Da + Dt) of the distance Da and the distance Dt may be greater than 100 ⁇ m and less than 150 ⁇ m.
- the sum of the distance Dd and the distance De, or the distance Da may be larger than the distance Df from the end position P3 of the emitter region 12 to the end position P1 of the accumulation region 16.
- the sum of the distance Dd and the distance De, or the distance Da may be larger than Dg, which is the distance from the end position P1 of the accumulation region 16 to the end position P4 of the contact region 15.
- the sum of the distance Dd and the distance De or the distance Da may be larger than the distance Dh from the bottom of the base region 14 of the boundary mesa 94-1 to the peak position of the defect concentration of the lifetime killer 96. Furthermore, the distance Dd or the distance De may be larger than the distance Dh from the bottom surface of the boundary mesa 94-1A or the base region 14 of the boundary mesa 94-1B to the peak position of the defect concentration of the lifetime killer 96 .
- the transistor section 70 is turned off, minority carriers can be effectively extracted.
- the sum of the distances Dd and De or the distance Da may be larger than the distance Di from the bottom of the base region 14 of the boundary mesa 94-1 to the position where the doping concentration is higher than the doping concentration of the semiconductor substrate. Furthermore, the sum of the distance Dd and the distance De, or the distance Da is from the bottom surface of the base region 14 of the boundary mesa 94-1 to the top surface of the semiconductor substrate among peak positions of a plurality of doping concentrations in the buffer region 20. It may be larger than the distance Dj to the peak position. As a result, when the transistor section 70 is turned off, minority carriers can be effectively extracted. In addition, it is possible to suppress the injection and accumulation of minority carriers in the boundary mesa portion 94-1 and the diode portion 80 at the time of conduction of the diode portion 80, and to prevent reverse recovery destruction.
- the region at the peak position of the doping concentration in the buffer region 20 may be a region including a hydrogen donor.
- the hydrogen donor may be formed by proton injection.
- the hydrogen donor may be a vacancy, a VOH complex defect due to oxygen and hydrogen.
- the doping concentration of the region F from the position where the doping concentration is higher than the doping concentration of the semiconductor substrate to the peak position of the uppermost surface of the semiconductor substrate among the peak positions of the doping concentration in the buffer region 20 is substantially flat.
- the region F may be a region including a hydrogen donor.
- the region F may be formed longer in the depth direction below the region where the lifetime killer 96 is formed, as compared to the region below the region where the lifetime killer 96 is not formed. When the lifetime killer 96 is irradiated from the lower surface of the semiconductor substrate, relatively many defects are formed in the region below the region where the lifetime killer 96 is formed, and hydrogen from the buffer region 20 is easily diffused.
- the sum of the distance Dd and the distance De, or the distance Da may be smaller than the distance Dt from the lower surface of the semiconductor substrate 10 to the lower surface of the base region 14.
- the distance Dd and the distance De, or the distance Da are larger than the distance Dt, the effect of preventing minority carrier extraction and reverse recovery breakdown at turn-off is saturated and a region (inactive region) not contributing to current conduction is As it increases, conduction loss and switching loss turn to increase.
- the distance Dd may be smaller than the distance Dt.
- the sum of the distance Dd and the distance De, or the distance Da, may be larger than the thermal diffusion length Lt of the semiconductor substrate.
- the thermal conductivity of the semiconductor substrate is ⁇
- the heat capacity per unit volume is C
- ⁇ 1.5 ⁇ 10 -5 (m 2 / s) about once a t the switching (for example, once the turn-off or reverse recovery)
- Lt is 7.7 ⁇ m.
- the sum of the distance Dd and the distance De or the distance Da may be, for example, larger than 7.7 ⁇ m.
- the distance Dd or the distance De may be larger than the thermal diffusion length Lt.
- the temperature of the diode unit 80 also increases.
- the heat generation of the diode unit 80 affects the transistor unit 70, the temperature of the transistor unit 70 also increases. Since the increase in temperature causes the concentration of minority carriers to increase, it is necessary to extract more carriers accordingly.
- the predetermined time t for heat diffusion may be the time required for one switching and may be 0.1 ⁇ s to 10 ⁇ s, for example 1 ⁇ s.
- the example which does not include the above-mentioned boundary mesa part 94-1B (for example, the semiconductor device 100 of FIGS. 1 to 6, the semiconductor device 300 of FIGS. 8 to 13, the semiconductor device 400 of FIGS. 14 to 15, or a combination thereof)
- the above relationship may be satisfied by setting the distance De of this example to zero.
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Abstract
Description
特開2015-135954号公報
Claims (28)
- 第1導電型のドリフト領域および前記ドリフト領域の上方に設けられた第2導電型のベース領域を有する半導体基板と、
前記半導体基板に形成されたトランジスタ部と、
前記トランジスタ部と隣接して前記半導体基板に形成されたダイオード部と
を備え、
前記トランジスタ部および前記ダイオード部には、
それぞれ予め定められた配列方向に沿って配列された複数のトレンチ部と、
それぞれのトレンチ部の間に形成された複数のメサ部と
が形成され、
前記複数のメサ部のうち、前記トランジスタ部および前記ダイオード部との境界における少なくとも1つの境界メサ部は、前記半導体基板の上面において前記ベース領域よりも高濃度の第2導電型のコンタクト領域を有し、
前記境界メサ部における前記コンタクト領域の面積は、他のメサ部における前記コンタクト領域の面積よりも大きい、半導体装置。 - 前記境界メサ部のうち少なくとも一つは、前記トランジスタ部に設けられる
請求項1に記載の半導体装置。 - 前記トランジスタ部に形成された前記メサ部の少なくとも一つには、前記ベース領域および前記ドリフト領域の間に前記ドリフト領域よりも高濃度の第1導電型の蓄積領域が設けられ、
前記境界メサ部のうち少なくとも一つには、前記蓄積領域が設けられない
請求項1または2に記載の半導体装置。 - 前記複数のトレンチ部のうち、前記境界メサ部に隣接するトレンチ部は、ダミートレンチ部である
請求項3に記載の半導体装置。 - 前記複数のトレンチ部のうち、前記境界メサ部に隣接するトレンチ部よりも前記トランジスタ部側に隣接して設けられた少なくとも一つのトレンチ部も、ダミートレンチ部である
請求項4に記載の半導体装置。 - 前記蓄積領域は、
予め定められた深さ位置に形成された第1蓄積領域と、
前記第1蓄積領域よりも前記ダイオード部に近く、且つ、前記第1蓄積領域よりも浅い位置に形成された第2蓄積領域と
を有し、
前記第2蓄積領域に隣接するトレンチ部も、ダミートレンチ部である
請求項4または5に記載の半導体装置。 - 前記ダイオード部は、前記半導体基板の上面側にライフタイムキラーを有し、
前記トランジスタ部は、前記第1蓄積領域が形成された領域において、前記半導体基板の上面側に前記ライフタイムキラーを有さない
請求項6に記載の半導体装置。 - 前記境界メサ部は、前記半導体基板の上面側にライフタイムキラーを有する
請求項7に記載の半導体装置。 - 前記境界メサ部よりも前記トランジスタ部側の前記メサ部は、前記半導体基板の上面において、前記ドリフト領域よりも高濃度の第1導電型のエミッタ領域と、前記コンタクト領域とを有し、
前記境界メサ部は、前記エミッタ領域を有さない
請求項6から8のいずれか一項に記載の半導体装置。 - 前記境界メサ部よりも前記ダイオード部側の前記メサ部のうち少なくとも一部は、前記半導体基板の上面において前記ベース領域を有する
請求項6から9のいずれか一項に記載の半導体装置。 - 前記トランジスタ部と前記ダイオード部との境界から、前記エミッタ領域を有する前記メサ部と、前記境界メサ部との間の前記トレンチ部までの距離をDaとし、
前記半導体基板の下面から、前記ベース領域の下面までの距離をDtとした場合に、
100μm<Da+Dt<150μm
である、請求項9に記載の半導体装置。 - それぞれのトレンチ部は、前記半導体基板の上面において、前記配列方向とは異なる延伸方向に延伸して形成されており、
前記境界メサ部よりも前記トランジスタ部側の前記メサ部は、前記半導体基板の上面において、前記延伸方向に沿って前記エミッタ領域および前記コンタクト領域を交互に有し、
前記延伸方向において、最も外側に形成された前記エミッタ領域の端部よりも外側まで前記蓄積領域が形成されている
請求項9に記載の半導体装置。 - 前記半導体基板の上面に形成された層間絶縁膜を更に備え、
前記層間絶縁膜には、前記エミッタ領域および前記コンタクト領域を露出させるコンタクトホールが形成され、
前記延伸方向において、前記コンタクトホールは前記蓄積領域の端部よりも外側まで形成されている
請求項12に記載の半導体装置。 - 前記エミッタ領域の下方の少なくとも一部の領域において、前記蓄積領域が形成されていないキャリア通過領域を有する
請求項12に記載の半導体装置。 - 前記エミッタ領域の下方の領域全体に、前記キャリア通過領域が設けられている
請求項14に記載の半導体装置。 - 前記キャリア通過領域は、前記コンタクト領域のうち、前記エミッタ領域に隣接する端部の下方にも設けられている
請求項15に記載の半導体装置。 - 前記蓄積領域は、
予め定められた深さ位置に形成された第1蓄積領域と、
前記第1蓄積領域よりも前記エミッタ領域に近く、且つ、前記第1蓄積領域よりも浅い位置に形成された第2蓄積領域と
を有し、
前記第1蓄積領域および前記第2蓄積領域のいずれも、前記コンタクト領域の下方に形成されている
請求項14から16のいずれか一項に記載の半導体装置。 - 前記半導体基板の上面に形成された層間絶縁膜を更に備え、
前記層間絶縁膜には、前記エミッタ領域および前記コンタクト領域を露出させるコンタクトホールが形成され、
前記延伸方向において、前記蓄積領域は、前記コンタクトホールの端部よりも外側まで形成されている
請求項14から17のいずれか一項に記載の半導体装置。 - 第1導電型のドリフト領域および前記ドリフト領域の上方に設けられた第2導電型のベース領域を有する半導体基板と、
前記半導体基板の上面において、予め定められた延伸方向において延伸して形成され、前記ベース領域を貫通するトレンチ部と、
前記半導体基板の上面において前記トレンチ部と隣接する領域に、前記延伸方向に沿って交互に形成された、前記ドリフト領域よりも高濃度の前記第1導電型のエミッタ領域および前記ベース領域よりも高濃度の前記第2導電型のコンタクト領域と、
前記ベース領域および前記ドリフト領域の間に形成され、前記ドリフト領域よりも高濃度の前記第1導電型の蓄積領域と
を備え、
前記延伸方向において、最も外側に形成された前記エミッタ領域の端部よりも外側まで前記蓄積領域が形成されている半導体装置。 - 前記半導体基板の上面に形成された層間絶縁膜を更に備え、
前記層間絶縁膜には、前記エミッタ領域および前記コンタクト領域を露出させるコンタクトホールが形成され、
前記延伸方向において、前記コンタクトホールは前記蓄積領域の端部よりも外側まで形成されている
請求項19に記載の半導体装置。 - 前記延伸方向における前記蓄積領域の端部は、外側ほど浅い位置に形成されている
請求項19または20に記載の半導体装置。 - 前記半導体基板の上面において、前記コンタクト領域よりも外側に形成された、前記ベース領域よりも高濃度の前記第2導電型のウェル領域を更に備え、
前記半導体基板の上面において、前記コンタクト領域および前記ウェル領域の間に前記ベース領域が形成されている
請求項19から21のいずれか一項に記載の半導体装置。 - 前記延伸方向において、前記エミッタ領域の端部から前記蓄積領域の端部までの距離が、前記蓄積領域の端部から前記コンタクトホールの端部までの距離よりも短い
請求項20に記載の半導体装置。 - 第1導電型のドリフト領域および前記ドリフト領域の上方に設けられた第2導電型のベース領域を有する半導体基板と、
前記半導体基板の上面において、予め定められた延伸方向において延伸して形成され、前記ベース領域を貫通するトレンチ部と、
前記半導体基板の上面において前記トレンチ部と隣接する領域に、前記延伸方向に沿って交互に形成された、前記ドリフト領域よりも高濃度の前記第1導電型のエミッタ領域および前記ベース領域よりも高濃度の前記第2導電型のコンタクト領域と、
前記ベース領域および前記ドリフト領域の間に形成され、前記ドリフト領域よりも高濃度の前記第1導電型の蓄積領域と、
前記半導体基板の上面に形成された層間絶縁膜と
を備え、
前記層間絶縁膜には、前記エミッタ領域および前記コンタクト領域を露出させるコンタクトホールが形成され、
前記延伸方向において、前記コンタクトホールは前記蓄積領域の端部よりも外側まで形成されている半導体装置。 - 前記トランジスタ部および前記ダイオード部は、
前記配列方向とは異なる延伸方向の最も外側に設けられた前記コンタクト領域の下方に、少なくとも設けられた第2導電型のコレクタ領域
をさらに備え
前記トランジスタ部は、
前記ベース領域および前記ドリフト領域の間に設けられ、前記ドリフト領域よりも高濃度の前記第1導電型の蓄積領域
をさらに備え、
前記ダイオード部の前記コレクタ領域の内側の端部は、前記トランジスタ部の前記蓄積領域の外側の端部よりも内側に位置する
請求項1または2に記載の半導体装置。 - 前記トランジスタ部は、前記ドリフト領域よりも高濃度の第1導電型のエミッタ領域をさらに備え、
前記ダイオード部の前記コレクタ領域の内側の端部は、前記トランジスタ部において前記延伸方向の最も外側に設けられた前記エミッタ領域の外側の端部よりも内側に位置する
請求項25に記載の半導体装置。 - 前記半導体装置は、
前記半導体基板に形成されたトランジスタ部と、
前記トランジスタ部と隣接して前記半導体基板に形成されたダイオード部と
をさらに備え、
前記トランジスタ部および前記ダイオード部は、
前記延伸方向の最も外側に設けられた前記コンタクト領域の下方に、少なくとも設けられた第2導電型のコレクタ領域
をさらに有し、
前記ダイオード部の前記コレクタ領域の内側の端部は、前記トランジスタ部の前記蓄積領域の外側の端部よりも内側に位置する
請求項19から24のいずれか一項に記載の半導体装置。 - 前記ダイオード部の前記コレクタ領域の内側の端部は、前記トランジスタ部において前記延伸方向の最も外側に設けられた前記エミッタ領域の外側の端部よりも内側に位置する
請求項27に記載の半導体装置。
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US12080707B2 (en) | 2024-09-03 |
US20220392891A1 (en) | 2022-12-08 |
US20230361111A1 (en) | 2023-11-09 |
CN107924951A (zh) | 2018-04-17 |
JP6604430B2 (ja) | 2019-11-13 |
JPWO2017155122A1 (ja) | 2018-07-12 |
US10930647B2 (en) | 2021-02-23 |
JP6791312B2 (ja) | 2020-11-25 |
DE112017000079T5 (de) | 2018-05-17 |
US20210175231A1 (en) | 2021-06-10 |
JP2019195093A (ja) | 2019-11-07 |
US11430784B2 (en) | 2022-08-30 |
CN107924951B (zh) | 2021-11-23 |
US20180182754A1 (en) | 2018-06-28 |
US11735584B2 (en) | 2023-08-22 |
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