JP5918288B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5918288B2 JP5918288B2 JP2014040412A JP2014040412A JP5918288B2 JP 5918288 B2 JP5918288 B2 JP 5918288B2 JP 2014040412 A JP2014040412 A JP 2014040412A JP 2014040412 A JP2014040412 A JP 2014040412A JP 5918288 B2 JP5918288 B2 JP 5918288B2
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- 239000004065 semiconductor Substances 0.000 title claims description 68
- 230000004888 barrier function Effects 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 23
- 210000000746 body region Anatomy 0.000 claims description 22
- 230000000630 rising effect Effects 0.000 description 10
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Description
(特徴1) 第1ピラー領域のアノード電極に対する接触面積が、第2ピラー領域のアノード電極に対する接触面積よりも狭い。
(特徴2) 第1ピラー領域の半導体基板表面におけるn型不純物濃度が、第2ピラー領域の半導体基板表面におけるn型不純物濃度よりも低い。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
12:半導体基板
14:上部電極
16:下部電極
20:エミッタ領域
22:ボディ領域
24:ピラー領域
26:バリア領域
28:ドリフト領域
30:バッファ領域
32:コレクタ領域
34:アノード領域
36:カソード領域
42:ゲート電極
52:制御電極
90:IGBT領域
92:ダイオード領域
Claims (3)
- ダイオード領域とIGBT領域を有する半導体基板と、
前記ダイオード領域内の前記半導体基板の表面に形成されているアノード電極と、
前記ダイオード領域内の前記半導体基板の裏面に形成されているカソード電極と、
前記IGBT領域内の前記表面に形成されているエミッタ電極と、
前記IGBT領域内の前記裏面に形成されているコレクタ電極と、
ゲート絶縁膜と、
ゲート電極、
を有しており、
前記ダイオード領域が、
前記アノード電極に対してオーミック接続されているp型のアノード領域と、
前記アノード領域の側方に配置されており、前記アノード領域に接しており、前記アノード電極に対してショットキー接続されているn型の複数のピラー領域と、
前記アノード領域の裏面側に配置されており、前記アノード領域に接しており、複数の前記ピラー領域と繋がっているn型のバリア領域と、
前記バリア領域の裏面側に配置されており、前記バリア領域よりもn型不純物濃度が低いn型のダイオードドリフト領域と、
前記ダイオードドリフト領域の裏面側に配置されており、前記カソード電極に接続されており、前記ダイオードドリフト領域よりもn型不純物濃度が高いn型のカソード領域、
を有しており、
前記IGBT領域が、
前記エミッタ電極に対してオーミック接続されているn型のエミッタ領域と、
前記エミッタ電極に対してオーミック接続されているp型のボディ領域と、
前記ダイオードドリフト領域と繋がっており、前記ボディ領域によって前記エミッタ領域から分離されているn型のIGBTドリフト領域と、
前記コレクタ電極に接続されており、前記IGBTドリフト領域によって前記ボディ領域から分離されているp型のコレクタ領域、
を有しており、
前記ゲート電極が、前記エミッタ領域と前記IGBTドリフト領域の間を分離している前記ボディ領域に対して前記ゲート絶縁膜を介して対向しており、
複数の前記ピラー領域のうちの第1ピラー領域の前記アノード電極に対するオン抵抗が、複数の前記ピラー領域のうちの第1ピラー領域よりも前記IGBT領域に近い位置にある第2ピラー領域の前記アノード電極に対するオン抵抗よりも高い、
半導体装置。 - 前記第1ピラー領域の前記アノード電極に対する接触面積が、前記第2ピラー領域の前記アノード電極に対する接触面積よりも狭い請求項1の半導体装置。
- 前記第1ピラー領域の前記表面におけるn型不純物濃度が、前記第2ピラー領域の前記表面におけるn型不純物濃度よりも低い請求項1の半導体装置。
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