CN104900690A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104900690A
CN104900690A CN201510093283.3A CN201510093283A CN104900690A CN 104900690 A CN104900690 A CN 104900690A CN 201510093283 A CN201510093283 A CN 201510093283A CN 104900690 A CN104900690 A CN 104900690A
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diode
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CN104900690B (zh
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大河原淳
山下侑佑
町田悟
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Denso Corp
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Toyota Motor Corp
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Abstract

本发明提供一种半导体装置，其在采用了具有肖特基接触的二极管结构的RC-IGBT中，对栅极干扰进行抑制。所述半导体装置具有半导体基板(12)，该半导体基板(12)具有二极管区域(92)和IGBT区域(90)。该半导体装置中，二极管区域(92)具有：p型的阳极区(34)，其与阳极电极(14)欧姆接触；n型的多个柱区(24)，其与阳极电极(14)肖特基接触；n型的势垒区(26)；n型的二极管漂移区(28)；以及n型的阴极区(36)。第一柱区(24a)相对于阳极电极(14)的导通电阻与位于距IGBT区域(90)较近的位置处的第二柱区(24b)相对于阳极电极(14)的导通电阻相比较高。

Description

半导体装置
技术领域
本说明书所公开的技术涉及一种半导体装置。
背景技术
在专利文献1中公开了一种在一个半导体基板上形成有IGBT(InsulatedGate Bipolar Transistor,绝缘栅双极性晶体管)和二极管的半导体装置(所谓的RC-IGBT，反向导通型绝缘栅双极性晶体管)。
另外，在专利文献2中公开了一种为了对二极管的pn结导通的情况进行抑制，而设置了n柱区和n势垒区的二极管。n柱区与阳极电极肖特基接触。通过n柱区和n势垒区而形成了对pn结进行旁通的电路路径。由于肖特基接触与pn结相比先导通，因此抑制了pn结导通的情况。
专利文献1：日本特开2012-043890号公报
专利文献2：日本特开2013-048230号公报
发明内容
如专利文献1所记载的那样，在RC-IGBT中有时会产生被称作栅极干扰的现象。即，当向IGBT的栅极施加预定电压时，将会对二极管的动作产生影响，从而使二极管的动作变得不稳定。
也能够如专利文献2那样在RC-IGBT的二极管部分采用具有肖特基接触的二极管结构。在这种情况下，也会产生栅极干扰的问题。因此，在本说明书中，提供一种在采用了具有肖特基接触的二极管结构的RC-IGBT中，对栅极干扰进行抑制的技术。
本说明书所公开的半导体装置具有：半导体基板，其具有二极管区域和IGBT区域；阳极电极，其被形成于所述二极管区域内的所述半导体基板的表面上；阴极电极，其被形成于所述二极管区域内的所述半导体基板的背面上；发射极，其被形成于所述IGBT区域内的所述表面上；集电极，其被形成于所述IGBT区域内的所述背面上；栅极绝缘膜；以及栅电极。所述二极管区域具有：p型的阳极区，其与所述阳极电极欧姆接触；n型的多个柱区，其被配置于所述阳极区的侧方，并与所述阳极区相接，且与所述阳极电极肖特基接触；n型的势垒区，其被配置于所述阳极区的背面侧，并与所述阳极区相接，且与多个所述柱区相连；n型的二极管漂移区，其被配置于所述势垒区的背面侧，且与所述势垒区相比n型杂质浓度较低；以及n型的阴极区，其被配置于所述二极管漂移区的背面侧，并被连接于所述阴极电极，且与所述二极管漂移区相比n型杂质浓度较高。所述IGBT区域具有：n型的发射区，其与所述发射极欧姆接触；p型的体区，其与所述发射极欧姆接触；n型的IGBT漂移区，其与所述二极管漂移区相连，并通过所述体区而与所述发射区分离；以及p型的集电区，其被连接于所述集电极，并通过所述IGBT漂移区而与所述体区分离。所述栅电极隔着所述栅极绝缘膜而与将所述发射区和所述IGBT漂移区之间分离的所述体区对置。多个所述柱区中的第一柱区相对于所述阳极电极的导通电阻与多个所述柱区中的第二柱区相对于所述阳极电极的导通电阻相比较高，所述第二柱区处于与第一柱区相比距所述IGBT区域较近的位置处。
另外，上述“导通电阻”是指，由阳极电极和柱区构成的肖特基势垒二极管的电流的流通容易度。肖特基势垒二极管的开启电压较高是指导通电阻较高。此外，肖特基势垒二极管的电流的上升角度较小是指导通电阻较高。此外，上述阳极电极和上述发射极既可以被一体化，也可以被分离。此外，上述阴极电极和上述集电极既可以被一体化，也可以被分离。
在该半导体装置中，在与距IGBT区域较近的第二柱区相比离IGBT区域较远的第一柱区中，相对于阳极电极的电阻较高。因此，与在第一柱区的附近相比，在第二柱区的附近，pn结(即，由阳极区和势垒区构成的pn结)较难导通，从而电流难以流通。因此，即使由于栅极干扰而使电流未在距IGBT区域较近的第二柱区周围流通，对二极管区域整体的电流值的影响也较小。因此，该半导体装置不易受到栅极干扰的影响。
附图说明
图1为实施例1的半导体装置10的剖视图。
图2为实施例1的半导体装置10的俯视图。
图3为表示实施例1的SBD24a、24b的特性的曲线图。
图4为实施例2的半导体装置的纵向剖视图。
图5为表示实施例2的SBD24a、24b的特性的曲线图。
图6为改变例的半导体装置的俯视图。
图7为改变例的半导体装置的俯视图。
图8为改变例的半导体装置的纵向剖视图。
具体实施方式
首先，对以下所说明的实施例的特征进行列举。另外，以下所列举的特征均为独立且有用的特征。
(特征1)第一柱区相对于阳极电极的接触面积与第二柱区相对于阳极电极的接触面积相比较窄。
(特征2)第一柱区的半导体基板表面上的n型杂质浓度与第二柱区的半导体基板表面上的n型杂质浓度相比较低。
[实施例1])
图1所示的实施例1的半导体装置10具有半导体基板12、上部电极14、下部电极16。半导体基板12为硅制的基板。上部电极14被形成于半导体基板12的上表面12a上。下部电极16a被形成于半导体基板12的下表面上。半导体基板12具有形成有IGBT的IGBT区域90和形成有二极管的二极管区域92。即，半导体装置10为所谓的RC-IGBT。如图2所示，在半导体基板12上交替地形成有IGBT区域90和二极管区域92。
如图1所示，在二极管区域92内的半导体基板12中形成有阳极区34、柱区24、势垒区26、漂移区28、缓冲区30以及阴极区36。
阳极区34为p型，并被形成在半导体基板12的露出于上表面12a的范围内。阳极区34具有阳极接触区34a和低浓度阳极区34b。阳极接触区34a被形成在半导体基板12的露出于上表面12a的范围内。阳极接触区34a的p型杂质浓度较高，并且阳极接触区34a与上部电极14欧姆接触。低浓度阳极区34b被形成于阳极接触区34a的下侧和侧方。低浓度阳极区34b的p型杂质浓度与阳极接触区34a相比较低。
柱区24为n型，并被形成在半导体基板12的露出于上表面12a的范围内。柱区24在低浓度阳极区34b的侧方与低浓度阳极区34b相接。柱区24从半导体基板12的上表面12a起延伸至阳极区34的下端的深度。换言之，在与阳极区34的下端相比较浅的位置处从侧方与阳极区34相接的n型区域为柱区24。柱区24与上部电极14肖特基接触。
在实施例1中，被配置于距IGBT区域90较近的位置处的两个柱区24b的宽度W2，宽于被配置于与柱区24b相比距IGBT区域90较远的位置处的柱区24a的宽度W1。因此，各柱区24b露出于上表面12a的面积与各柱区24a露出于上表面12a的面积相比较大。换言之，各柱区24b与上部电极14肖特基接触的区域的面积大于各柱区24a与上部电极14肖特基接触的区域的面积。另外，以下将二极管区域92中的形成有柱区24a的区域(即，距IGBT区域90较远的区域)称作第一二极管区域92a，将形成有柱区24b的区域(即，距IGBT区域90较近的区域)称作第二二极管区域92b。
势垒区26为n型，并被形成于阳极区34和柱区24的下侧。势垒区26与柱区24相连接。势垒区26与阳极区34相接。
漂移区28为n型，并被形成于势垒区26的下侧。漂移区28通过势垒区26而与阳极区34分离。在漂移区28内，n型杂质浓度大致均匀地分布。换言之，n型杂质浓度大致均匀地分布的区域为漂移区28，而存在于漂移区28的上侧，并且n型杂质浓度与大致均匀地分布的值相比较高的区域为势垒区26。
缓冲区30为n型，并被形成于漂移区28的下侧。缓冲区30的n型杂质浓度与漂移区28相比较高。
阴极区36为n型，并被形成于缓冲区30的下侧。阴极区36具有与缓冲区30相比较高的n型杂质浓度。阴极区36被形成在半导体基板12的露出于下表面的范围内。阴极区36与下部电极16欧姆接触。
在二极管区域92内的半导体基板12的上表面12a上形成有多个沟槽。各沟槽贯穿阳极区34以及势垒区26直至漂移区28。各沟槽的内表面被绝缘膜50所覆盖。在各沟槽内形成有控制电极52。控制电极52通过绝缘膜50而与半导体基板12绝缘。控制电极52的上表面12a被绝缘膜54所覆盖。控制电极52通过绝缘膜54而与上部电极14绝缘。
在IGBT区域90内的半导体基板12中形成有发射区20、体区22、柱区24、势垒区26、漂移区28、缓冲区30、集电区32。
发射区20为n型，并被形成在半导体基板12的露出于上表面12a的范围内。发射区20与上部电极14欧姆接触。
体区22为p型，并被形成在半导体基板12的露出于上表面12a的范围内。体区22具有体接触区22a和低浓度体区22b。体接触区22a被形成在半导体基板12的露出于上表面12a的范围内。体接触区22a的p型杂质浓度较高，并且体接触区22a与上部电极14欧姆接触。低浓度体区22b被形成于发射区20以及体接触区22a的下侧和体接触区22a的侧方。低浓度体区22b的p型杂质浓度与体接触区22a相比较低。体区22被形成在与阳极区34大致相同的深度范围内。
在体区22的侧方形成有上述的柱区24。
在体区22的下侧形成有上述的势垒区26。
在IGBT区域90内的势垒区26的下侧形成有上述的漂移区28。漂移区28从二极管区域92跨及IGBT区域90而延伸。漂移区28通过势垒区26而与体区22分离。
在IGBT区域90内的漂移区28的下侧形成有上述的缓冲区30。缓冲区30从二极管区域92跨及IGBT区域90而延伸。
集电区32为p型，并被形成于IGBT区域90内的缓冲区30的下侧。集电区32被形成在半导体基板12的露出于下表面的范围内。集电区32与下部基板16欧姆接触。
在IGBT区域90内的半导体基板12的上表面12a上形成有多个沟槽。各个沟槽贯穿发射区20、低浓度体区22b和势垒区26直至漂移区28。各沟槽的内表面被栅极绝缘膜40所覆盖。在各沟槽内形成有栅电极42。栅电极42通过栅极绝缘膜40而与半导体基板12绝缘。栅电极42隔着栅极绝缘膜40而与发射区20、低浓度体区22b、势垒区26以及漂移区28对置。栅电极42的上表面12a被绝缘膜44所覆盖。栅电极42通过绝缘膜44而与上部电极14绝缘。
接下来，对柱区24a、24b的特性进行说明。在二极管区域92内，通过上部电极14和与上部电极14肖特基接触的柱区24而形成了肖特基势垒二极管(以下称作SBD)。在此，如上所述，柱区24a的肖特基接触区域的面积与柱区24b的肖特基接触区域的面积相比较小。因此，在由上部电极14和柱区24a形成的SBD(以下称作SBD24a)和由上部电极14和柱区24b形成的SBD(以下称作SBD24b)中，特性不同。如图3所示，SBD24a的电流的上升角度dI/dV与SBD24b的电流的上升角度dI/dV相比较小。另一方面，SBD24a和SBD24b具有几乎相同的开启电压VF。如图3所示，在SBD24a中，与SBD24b相比，电流难以流通。即，SBD24a具有与SBD24b相比较高的电阻。
接下来，对二极管区域92的动作进行说明。考虑如下情况，即，使向上部电极14施加的施加电压(上部电极14相对于下部电极16而成为正的电压：以下称作二极管正向电压)逐渐上升的情况。当二极管正向电压大于SBD24a、24b的开启电压VF时，SBD24a、24b将导通。即，如图1的箭头60所示，电子从下部电极16起经由阴极区36、缓冲区30、漂移区28、势垒区26以及柱区24，而流通至上部电极14。此外，在二极管区域92内，通过阳极区34和势垒区26而形成了pn结。被施加于各pn结的电压(即被施加于上部电极14与势垒区26之间的电压)同被施加于与pn结邻接的SBD24的电压大致相等。由于pn结导通的电压与SBD24a、24b的开启电压相比较高，因此在该阶段pn结不导通。
当进一步使二极管正向电压增加时，SBD24a、24b中流通的电流也将增加，并且，向SBD24a、24b施加的施加电压将上升。此时，由于SBD24a的导通电阻较高，因此与在SBD24b中相比，在SBD24a中，施加电压较易于上升。因此，当使二极管正向电压逐渐增加时，与SBD24a(即柱区24a)邻接的pn结先于与SBD24b(即柱区24b)邻接的pn结而导通。由此，如图1的箭头62所示，空穴从上部电极14起经由阳极区34、势垒区26、漂移区28、缓冲区30以及阴极区36，流通至下部电极16。此外，电子在箭头62所示的路径中向反方向流通。当如箭头62所示那样空穴流入至漂移区28中时，由于被空穴吸引，从而电子从第二二极管区域92内的漂移区28向第一二极管区域92a内的漂移区移动。其结果为，在第二二极管区域92b内的漂移区28中电子的浓度下降。
当进一步使二极管正向电压增加时，向SBD24b施加的施加电压将上升，并且与柱区24b邻接的pn结将导通。如此，在该半导体装置10中，在距IGBT区域90较近的第二二极管区域92b中pn结难以导通，从而在第二二极管区域92b中电流难以流通。即，在第二二极管区域92b中流通的电流与在第一二极管区域92a中流通的电流相比较小。
接下来，对栅极干扰时的动作进行说明。在向IGBT的栅电极42施加有栅极电压的状态下，即使施加了二极管正向电压，IGBT区域90附近的二极管(即二极管区域92b内的二极管)也难以导通。这是由于，由于栅极电压的施加，从而在体区22内形成有沟道，使第二二极管区域92b内的漂移区28的电位成为与上部电极14的电位接近的电位。关于栅极干扰的详细内容，请参照上述的专利文献1。此外，如专利文献1所记载的那样，当发生栅极干扰时，IGBT区域附近的二极管将进行急变返回(snapback)动作。
但是，在本实施例的半导体装置10中，如上所述，在距IGBT区域90较近的第二二极管区域92b中流通的电流较小。因此，即使由于栅极干扰而在第二二极管区域92b中未流通有电流，在二极管区域92整体中流通的电流的减小幅度也较小。因此，在实施例1的半导体装置10中，栅极干扰对二极管的电流的影响极小。
此外，如上所述，在实施例1的半导体装置10中，在第一二极管区域92a内的pn结导通，第二二极管区域92b内的pn结未导通的状态下，电子从第二二极管区域92b向第一二极管区域92a移动。因此，在第二二极管区域92b内的pn结导通的定时，第二二极管区域92b内的漂移区28中的电子的浓度较低。如此，在漂移区28的电子的浓度较低的状态下pn结导通时，即使产生了栅极干扰，也不易产生急变返回。因此，根据实施例1的半导体装置10，能够对栅极干扰时的二极管的急变返回进行抑制。
如以上所说明的那样，在实施例1的半导体装置10中，能够将栅极干涉对二极管的特性的影响最小化。在实施例1的半导体装置10中，二极管能够稳定地进行动作。
[实施例2]
图4所示的实施例2的半导体装置除了柱区24的结构以外，具有与实施例1的半导体装置10相同的结构。在实施例2的半导体装置中，柱区24b的宽度与柱区24a的宽度相等。即，柱区24b的肖特基接触区域的面积与柱区24a的肖特基接触区域的面积相等。另一方面，在实施例2的半导体装置中，柱区24a的n型杂质浓度与柱区24b的n型杂质浓度相比较低。因此，在实施例2的半导体装置中，SBD24a、24b具有图5所示的特性。
如图5所示，在实施例2的半导体装置中，SBD24a的开启电压VFa与SBD24b的开启电压VFb相比较高。而且，SBD24a的电流的上升角度dI/dV与SBD24b的电流的上升角度dI/dV相比较小。即，在实施例2的半导体装置中，也与实施例1相同，SBD24a的导通电阻与SBD24b的导通电阻相比较高。
如此，在实施例2的半导体装置中，距IGBT区域90较远的SBD24a的导通电阻也与距IGBT区域90较近的SBD24b的导通电阻相比较高。因此，实施例2的半导体装置能够与实施例1的半导体装置同样地进行动作。在实施例2的半导体装置中，也与实施例1相同，由栅极干扰产生的电流值的减小幅度较小，并且在栅极干扰时不易产生二极管的急变返回。
另外，在上述的实施例2中，柱区24a的n型杂质浓度与柱区24b的n型杂质浓度相比较低。但是，只需至少使柱区24a的上表面12a中的n型杂质浓度低于柱区24b的上表面12a中的n型杂质浓度即可。根据这种结构，能够使SBD24a的导通电阻高于SBD24b的导通电阻。
此外，虽然在上述的实施例1、2中，在IGBT区域90内形成了柱区24和势垒区26，但是这些区域并非必须被形成于IGBT区域90内。此外，虽然在上述的实施例1、2中，在二极管区域92内形成了控制电极52，但是控制电极52并非必须被形成于二极管区域92内。另外，虽然在上述的实施例1、2中，IGBT具有沟槽型的栅电极，但是栅电极也可以为平面型。
此外，虽然在上述的实施例1、2中，如图2所示，配置了IGBT区域90和二极管区域92，但是能够对IGBT区域90和二极管区域92的配置自由地进行变更。例如，也可以如图6、7所示那样进行配置。
以上虽然对本发明的具体示例进行了详细说明，但是这些仅为例示，并不对权利要求的范围进行限定。在权利要求范围所记载的技术中包含对以上例示的具体示例进行各种改变、变更的技术。
本说明书和附图所说明的技术要素为，通过单独或各种组合的方式来发挥技术有用性的技术要素，并不限定于申请时权利要求所记载的组合。此外，本说明书或附图所例示的技术为同时达成多个目的的技术，并且达成其中一个目的本身便具有技术有用性。
符号说明
10…半导体装置；
12…半导体基板；
14…上部电极；
16…下部电极；
20…发射区；
22…体区；
24…柱区；
26…势垒区；
28…漂移区；
30…缓冲区；
32…集电区；
34…阳极区；
36…阴极区；
42…栅电极；
52…控制电极；
90…IGBT区域；
92…二极管区域。

Claims (3)

1.一种半导体装置，具有：
半导体基板，其具有二极管区域和绝缘栅双极性晶体管区域；
阳极电极，其被形成于所述二极管区域内的所述半导体基板的表面上；
阴极电极，其被形成于所述二极管区域内的所述半导体基板的背面上；
发射极，其被形成于所述绝缘栅双极性晶体管区域内的所述表面上；
集电极，其被形成于所述绝缘栅双极性晶体管区域内的所述背面上；
栅极绝缘膜；以及
栅电极，
所述二极管区域具有：
p型的阳极区，其与所述阳极电极欧姆接触；
n型的多个柱区，其被配置于所述阳极区的侧方，并与所述阳极区相接，且与所述阳极电极肖特基接触；
n型的势垒区，其被配置于所述阳极区的背面侧，并与所述阳极区相接，且与多个所述柱区相连；
n型的二极管漂移区，其被配置于所述势垒区的背面侧，且与所述势垒区相比n型杂质浓度较低；以及
n型的阴极区，其被配置于所述二极管漂移区的背面侧，并被连接于所述阴极电极，且与所述二极管漂移区相比n型杂质浓度较高，
所述绝缘栅双极性晶体管区域具有：
n型的发射区，其与所述发射极欧姆接触；
p型的体区，其与所述发射极欧姆接触；
n型的绝缘栅双极性晶体管漂移区，其与所述二极管漂移区相连，并通过所述体区而与所述发射区分离；以及
p型的集电区，其被连接于所述集电极，并通过所述绝缘栅双极性晶体管漂移区而与所述体区分离，
所述栅电极隔着所述栅极绝缘膜而与将所述发射区和所述绝缘栅双极性晶体管漂移区之间分离的所述体区对置，
多个所述柱区中的第一柱区相对于所述阳极电极的导通电阻与多个所述柱区中的第二柱区相对于所述阳极电极的导通电阻相比较高，所述第二柱区处于与第一柱区相比距所述绝缘栅双极性晶体管区域较近的位置处。
2.如权利要求1所述的半导体装置，其中，
所述第一柱区相对于所述阳极电极的接触面积与所述第二柱区相对于所述阳极电极的接触面积相比较窄。
3.如权利要求1所述的半导体装置，其中，
所述第一柱区的所述表面上的n型杂质浓度与所述第二柱区的所述表面上的n型杂质浓度相比较低。
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