JP6354525B2 - 炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6354525B2 JP6354525B2 JP2014226051A JP2014226051A JP6354525B2 JP 6354525 B2 JP6354525 B2 JP 6354525B2 JP 2014226051 A JP2014226051 A JP 2014226051A JP 2014226051 A JP2014226051 A JP 2014226051A JP 6354525 B2 JP6354525 B2 JP 6354525B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- forming
- recess
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 46
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 46
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000000034 method Methods 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010410 layer Substances 0.000 claims description 158
- 239000012535 impurity Substances 0.000 claims description 38
- 239000011229 interlayer Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 27
- 230000002093 peripheral effect Effects 0.000 claims description 23
- 230000015556 catabolic process Effects 0.000 claims description 8
- 239000002344 surface layer Substances 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 12
- 238000000059 patterning Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0869—Shape
Description
本発明の第1実施形態について説明する。本実施形態にかかるSiC半導体装置は、図1に示すように、MOSFETが形成されたセル領域とセル領域を囲むように外周耐圧構造が形成された外周領域とを有して構成されている。
まず、SiCからなるn+型基板1を用意したのち、このn+型基板1の表面にSiCからなるn-型ドリフト層2をエピタキシャル成長させる。続いて、n-型ドリフト層2の表面にLTOなどで構成されるマスク20を形成したのち、フォトリソグラフィ工程を経て、p型ディープ層10やp型リサーフ層15およびp型ガードリング層16の形成予定領域においてマスク20を開口させる。そして、マスク20上からp型不純物(例えばボロンやアルミニウム)のイオン注入を行うことで、p型ディープ層10およびp型ガードリング層16を形成する。この後、マスク20を除去する。
n-型ドリフト層2の表面に、p型不純物層をエピタキシャル成長させることにより、p型ベース領域3を形成する。
p型ベース領域3の上に、p型ベース領域3よりも高濃度なp型不純物層をエピタキシャル成長させることにより、p+型コンタクト層5を形成する。
p型ベース領域3の上にマスク21を形成したのち、フォトリソグラフィ工程を経て、n+型ソース領域4の形成予定領域、つまりトレンチゲート構造の形成予定領域よりも広い幅の領域においてマスク21を開口させる。そして、マスク21を用いて所定深さエッチングすることでp+型コンタクト層5およびp型ベース領域3の一部を除去する。これにより、凹部22が形成される。この凹部22の深さは、p型ベース領域3の底部よりも浅く、かつ、後工程で形成されるn+型ソース領域4の底部と同じ深さとされている。また、凹部22の幅は、トレンチ6の幅よりも広ければ良いが、本実施形態では、トレンチ6の両側面に形成されるn+型ソース領域4のうちトレンチ6と反対側の端同士の間の距離分に設定してある。この後、マスク21を除去する。
凹部22内を含めてp+型コンタクト層5の表面上に高濃度なn型不純物層23を所定厚さエピタキシャル成長させる。
CMP(Chemical Mechanical Polishing)などにより、セル領域および外周領域において、n型不純物層23のうちp+型コンタクト層5の表面上に形成された部分、つまり凹部22内以外の部分を除去する。これにより、凹部22内に形成されたn型不純物層23が残ることでn+型ソース領域4が形成される。このとき、n+型ソース領域4の表面に凹部4aが残るようにする。
n+型ソース領域4およびp+型コンタクト層5の上に、エッチングマスク24を成膜したのち、トレンチ6やメサ構造部14を構成する凹部の形成予定領域においてエッチングマスク24を開口させる。そして、エッチングマスク24を用いた異方性エッチングを行うことで、トレンチ6および凹部にて構成されるメサ構造部14を同時に形成する。この後、エッチングマスク24を除去する。
必要に応じて犠牲酸化等のトレンチ内表面の改質工程を行ったのち、熱酸化等によるゲート酸化膜8の形成工程を行うことにより、トレンチ6内を含む基板表面全面に所定厚さのゲート酸化膜8を形成する。これにより、n+型ソース領域4上においては、ゲート酸化膜8にも凹部4aの形状が引き継がれ、凹部8aが形成されることになる。
ゲート酸化膜8の表面にn型不純物をドーピングしたPoly−Si層を成膜したのち、エッチバック工程等を行うことにより、トレンチ6内にゲート酸化膜8およびゲート電極9を残す。このとき、ゲート電極9の表面がゲート酸化膜8の凹部8aの底面と同一平面となるようにしている。これにより、ゲート電極9を形成した後においても、ゲート酸化膜8に凹部8aが残った状態となる。
熱酸化により、ゲート電極9の表層部を酸化する。これにより、ゲート電極9の表面がキャップ酸化膜9aによって覆われる。このとき、ゲート電極9の表面が凹部8aの底面と同一平面とされており、さらに、今回の熱酸化によるキャップ酸化膜9aの厚みとゲート酸化膜8の酸化膜増加分がほぼ同じになることから、キャップ酸化膜9aの表面もほぼ凹部8aの底面と同一平面となる。このようにして、トレンチゲート構造が構成される。
ゲート酸化膜8やゲート電極9の上に層間絶縁膜12を成膜する。例えば、化学的気相(CVD:Chemical Vapor Deposition)成長法を用いて、厚さ0.7μm程度で層間絶縁膜12を成膜している。このとき、ゲート酸化膜8の表面に凹部8aが残されていることから、トレンチゲート構造の上においては、層間絶縁膜12が部分的に沈められた状態になる。
図示しないエッチングマスクを用いて層間絶縁膜12をパターニングする。これにより、層間絶縁膜12に対してn+型ソース領域4およびp+型コンタクト層5を部分的に露出させるコンタクトホールを形成すると共に、別断面においてゲート電極9の引き出し部分を部分的に露出させるコンタクトホールを形成する。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対してゲート電極9の構造を変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
2 n-型ドリフト層
3 p型ベース領域
4 n+型ソース領域
6 トレンチ
8 ゲート酸化膜
9 ゲート電極
10 p型ディープ層
11 ソース電極
12 層間絶縁膜
14 メサ構造部
15 p型リサーフ層
16 p型ガードリング層
Claims (4)
- 炭化珪素からなる第1または第2導電型の基板(1)上に、該基板よりも低不純物濃度とされた第1導電型の炭化珪素からなるドリフト層(2)を形成する工程と、
セル領域における前記ドリフト層の表層部に第2導電型のディープ層(10)を形成すると共に、前記セル領域を囲む外周領域において、前記セル領域を囲む第2導電型不純物層(15、16)を形成する工程と、
前記ディープ層、前記第2導電型不純物層および前記ドリフト層の上に第2導電型の炭化珪素からなるベース領域(3)を成膜する工程と、
前記ベース領域に第1凹部(22)を形成する工程と、
前記第1凹部内を含め、前記ベース領域の上に前記ドリフト層よりも高不純物濃度とされた第1導電型の炭化珪素からなる第1導電型不純物層(23)を成膜したのち、該第1導電型不純物層のうち前記第1凹部内以外の部分を除去し、前記第1凹部内に残された部分によってソース領域(4)を形成しつつ、該ソース領域の表面に第2凹部(4a)を残す工程と、
前記ソース領域における前記第2凹部の底面から前記ベース領域を貫通して前記ドリフト層に達し、かつ、前記ディープ層よりも浅くなるように、前記ディープ層が延設された方向と同方向を長手方向とするトレンチ(6)を形成すると同時に、前記外周領域において、前記ベース領域を除去して前記ドリフト層を露出させる凹部にて構成されるメサ構造部(14)を形成し、該メサ構造部の底面に位置する前記第2導電型不純物層によって外周耐圧構造を構成する工程と、
前記第2凹部の表面を含め、前記トレンチ内に、前記第2凹部が引き継がれた第3凹部(8a)を有するゲート絶縁膜(8)を形成する工程と、
前記トレンチ内において、前記ゲート絶縁膜の上にゲート電極(9)を形成する工程と、
前記ゲート電極および前記ゲート絶縁膜を覆う層間絶縁膜(12)を形成する工程と、
前記層間絶縁膜にコンタクトホールを形成する工程と、
前記コンタクトホールを通じて、前記ソース領域および前記ベース領域に電気的に接続されるソース電極(11)を形成する工程と、
前記基板(1)の裏面側にドレイン電極(13)を形成する工程と、を有していることを特徴とする炭化珪素半導体装置の製造方法。 - 前記ゲート電極を形成する工程では、前記第3凹部の底面と前記ゲート電極の表面が同一平面とされるようにすることを特徴とする請求項1に記載の炭化珪素半導体装置の製造方法。
- 前記ゲート電極を形成する工程では、前記ゲート電極の表面が、前記ゲート絶縁膜のうちの前記第3凹部の上面となる表面と同一平面もしくはそれ以下の位置とされるようにすることを特徴とする請求項1に記載の炭化珪素半導体装置の製造方法。
- 前記ゲート電極を形成する工程は、前記ゲート電極の表面を酸化することでキャップ酸化膜(9a)を形成する工程を含み、前記ゲート電極のうちの前記キャップ酸化膜の表面が、前記ゲート絶縁膜のうちの前記第3凹部の上面となる表面と同一平面もしくはそれ以下の位置となるようにすることを特徴とする請求項3に記載の炭化珪素半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014226051A JP6354525B2 (ja) | 2014-11-06 | 2014-11-06 | 炭化珪素半導体装置の製造方法 |
CN201510717810.3A CN105590962A (zh) | 2014-11-06 | 2015-10-29 | 碳化硅半导体装置和用于制造碳化硅半导体装置的方法 |
DE102015118698.5A DE102015118698A1 (de) | 2014-11-06 | 2015-11-02 | Siliziumkarbidhalbleitereinrichtung und Verfahren zum Herstellen der Siliziumkarbidhalbleitereinrichtung |
KR1020150153059A KR20160054408A (ko) | 2014-11-06 | 2015-11-02 | 탄화규소 반도체 장치 및 탄화규소 반도체 장치의 제조 방법 |
US14/929,742 US20160133741A1 (en) | 2014-11-06 | 2015-11-02 | Silicon carbide semiconductor device and method for manufacturing the silicon carbide semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014226051A JP6354525B2 (ja) | 2014-11-06 | 2014-11-06 | 炭化珪素半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016092257A JP2016092257A (ja) | 2016-05-23 |
JP6354525B2 true JP6354525B2 (ja) | 2018-07-11 |
Family
ID=55802953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014226051A Active JP6354525B2 (ja) | 2014-11-06 | 2014-11-06 | 炭化珪素半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20160133741A1 (ja) |
JP (1) | JP6354525B2 (ja) |
KR (1) | KR20160054408A (ja) |
CN (1) | CN105590962A (ja) |
DE (1) | DE102015118698A1 (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6231396B2 (ja) * | 2014-02-10 | 2017-11-15 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
US10453952B2 (en) * | 2015-09-09 | 2019-10-22 | Sumitomo Electric Industries, Ltd. | Semiconductor device |
JP6560141B2 (ja) * | 2016-02-26 | 2019-08-14 | トヨタ自動車株式会社 | スイッチング素子 |
JP6560142B2 (ja) * | 2016-02-26 | 2019-08-14 | トヨタ自動車株式会社 | スイッチング素子 |
JP6604430B2 (ja) * | 2016-03-10 | 2019-11-13 | 富士電機株式会社 | 半導体装置 |
DE102016112721B4 (de) | 2016-07-12 | 2022-02-03 | Infineon Technologies Ag | n-Kanal-Leistungshalbleitervorrichtung mit p-Schicht im Driftvolumen |
JP6871562B2 (ja) * | 2016-11-16 | 2021-05-12 | 富士電機株式会社 | 炭化珪素半導体素子およびその製造方法 |
US10861931B2 (en) * | 2016-12-08 | 2020-12-08 | Cree, Inc. | Power semiconductor devices having gate trenches and buried edge terminations and related methods |
JP6855793B2 (ja) * | 2016-12-28 | 2021-04-07 | 富士電機株式会社 | 半導体装置 |
JP6717242B2 (ja) * | 2017-03-13 | 2020-07-01 | 豊田合成株式会社 | 半導体装置 |
CN106876445A (zh) * | 2017-03-23 | 2017-06-20 | 深圳基本半导体有限公司 | 一种大功率平面栅d‑mosfet结构设计 |
JP6750590B2 (ja) * | 2017-09-27 | 2020-09-02 | 株式会社デンソー | 炭化珪素半導体装置 |
CN107658341B (zh) * | 2017-09-27 | 2020-09-15 | 上海朕芯微电子科技有限公司 | 一种沟槽型功率mosfet及其制备方法 |
JP7139596B2 (ja) * | 2017-12-06 | 2022-09-21 | 富士電機株式会社 | 半導体装置及びその製造方法 |
JPWO2020031971A1 (ja) * | 2018-08-07 | 2021-08-10 | ローム株式会社 | SiC半導体装置 |
JP7420485B2 (ja) * | 2019-05-23 | 2024-01-23 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
CN111276545B (zh) * | 2020-02-12 | 2023-03-14 | 重庆伟特森电子科技有限公司 | 一种新型沟槽碳化硅晶体管器件及其制作方法 |
CN114512402A (zh) * | 2022-04-19 | 2022-05-17 | 深圳芯能半导体技术有限公司 | 一种沟槽型碳化硅肖特基二极管及其制作方法 |
CN116314279B (zh) * | 2023-05-22 | 2023-08-04 | 南京第三代半导体技术创新中心有限公司 | 一种电力电子芯片终端保护结构 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002314081A (ja) * | 2001-04-12 | 2002-10-25 | Denso Corp | トレンチゲート型半導体装置およびその製造方法 |
JP2010147222A (ja) * | 2008-12-18 | 2010-07-01 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
JP4683075B2 (ja) * | 2008-06-10 | 2011-05-11 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP5533677B2 (ja) | 2011-01-07 | 2014-06-25 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP5482745B2 (ja) * | 2011-08-10 | 2014-05-07 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP5751213B2 (ja) * | 2012-06-14 | 2015-07-22 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
US9825166B2 (en) * | 2013-01-23 | 2017-11-21 | Hitachi, Ltd. | Silicon carbide semiconductor device and method for producing same |
US20150380537A1 (en) * | 2013-02-22 | 2015-12-31 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
JP6164636B2 (ja) * | 2013-03-05 | 2017-07-19 | ローム株式会社 | 半導体装置 |
JP6077380B2 (ja) * | 2013-04-24 | 2017-02-08 | トヨタ自動車株式会社 | 半導体装置 |
CN103258847B (zh) * | 2013-05-09 | 2015-06-17 | 电子科技大学 | 一种双面场截止带埋层的rb-igbt器件 |
-
2014
- 2014-11-06 JP JP2014226051A patent/JP6354525B2/ja active Active
-
2015
- 2015-10-29 CN CN201510717810.3A patent/CN105590962A/zh active Pending
- 2015-11-02 KR KR1020150153059A patent/KR20160054408A/ko not_active Application Discontinuation
- 2015-11-02 DE DE102015118698.5A patent/DE102015118698A1/de not_active Withdrawn
- 2015-11-02 US US14/929,742 patent/US20160133741A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20160133741A1 (en) | 2016-05-12 |
DE102015118698A1 (de) | 2016-05-12 |
CN105590962A (zh) | 2016-05-18 |
JP2016092257A (ja) | 2016-05-23 |
KR20160054408A (ko) | 2016-05-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6354525B2 (ja) | 炭化珪素半導体装置の製造方法 | |
JP6341074B2 (ja) | 半導体装置の製造方法 | |
JP5812029B2 (ja) | 炭化珪素半導体装置およびその製造方法 | |
JP6048317B2 (ja) | 炭化珪素半導体装置 | |
JP5751213B2 (ja) | 炭化珪素半導体装置およびその製造方法 | |
JP6022082B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
JP6409681B2 (ja) | 半導体装置およびその製造方法 | |
JP6428489B2 (ja) | 炭化珪素半導体装置およびその製造方法 | |
JP5298565B2 (ja) | 半導体装置およびその製造方法 | |
JP5621340B2 (ja) | 炭化珪素半導体装置の製造方法および炭化珪素半導体装置 | |
JP6179409B2 (ja) | 炭化珪素半導体装置の製造方法 | |
JP2013038308A (ja) | 炭化珪素半導体装置およびその製造方法 | |
TWI590449B (zh) | Silicon carbide semiconductor device, method of manufacturing the silicon carbide semiconductor device, and method of designing the silicon carbide semiconductor device | |
CN110050349B (zh) | 碳化硅半导体装置及其制造方法 | |
JP2017045776A (ja) | 半導体装置およびその製造方法 | |
JP2018046251A (ja) | 半導体装置およびその製造方法 | |
JP2011101036A (ja) | 炭化珪素半導体装置およびその製造方法 | |
WO2017145548A1 (ja) | 化合物半導体装置およびその製造方法 | |
WO2020235676A1 (ja) | 炭化珪素半導体装置およびその製造方法 | |
JP2014127547A (ja) | 半導体装置の製造方法 | |
JP2018046256A (ja) | 半導体装置 | |
JP2012199468A (ja) | 半導体装置の製造方法 | |
TWI574405B (zh) | Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and design method of silicon carbide semiconductor device | |
JP5738094B2 (ja) | 半導体装置の製造方法 | |
TW201635539A (zh) | 半導體裝置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160711 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170314 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170316 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170512 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170808 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20171006 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20171212 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180307 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20180413 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180515 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180528 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6354525 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |