WO2016063683A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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WO2016063683A1
WO2016063683A1 PCT/JP2015/077376 JP2015077376W WO2016063683A1 WO 2016063683 A1 WO2016063683 A1 WO 2016063683A1 JP 2015077376 W JP2015077376 W JP 2015077376W WO 2016063683 A1 WO2016063683 A1 WO 2016063683A1
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semiconductor substrate
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PCT/JP2015/077376
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French (fr)
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内藤　達也
正人 大月
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富士電機株式会社
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Priority to JP2016555145A priority Critical patent/JP6319454B2/ja
Publication of WO2016063683A1 publication Critical patent/WO2016063683A1/ja
Priority to US15/335,440 priority patent/US9905555B2/en

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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • Patent Document 1 a semiconductor chip having a superjunction MOSFET and a semiconductor chip having an insulated gate bipolar transistor are connected in parallel (see, for example, Patent Document 1).
  • super junction Super Junction
  • SJ super junction
  • IGBT insulated gate bipolar transistor
  • Patent Document 2 Japanese Patent Application Publication No. 2013-102111 (US Patent Application Publication No. 2013/134478)
  • the semiconductor chip having the SJ-MOSFET and the semiconductor chip having the IGBT are connected by wiring and modularized. Therefore, the module can not be miniaturized as compared with the case where the SJ-MOSFET and the IGBT are formed in one semiconductor chip.
  • the upper edge of the depletion layer relaxation region having protons is provided so as to substantially coincide with the bottom surface of the p-type column layer (FIG. 1, paragraph 0055 and paragraph 0056).
  • the donor protons and the n-type base layer are in contact with each other, so the number of electrons as carriers of the n-type base layer is greater than the number of holes as carriers of the p-type column layer, and the carrier balance is broken. . Therefore, the depletion layer is less likely to be formed by the n-type base layer and the p-type column layer.
  • a first aspect of the present invention provides a semiconductor device comprising a semiconductor substrate, a super junction structure, and a field stop layer.
  • the super junction structure may be formed on the surface side of the semiconductor substrate.
  • the field stop layer may be formed at a position overlapping the super junction structure on the back surface side of the semiconductor substrate and may be formed so as not to be in contact with the back surface side end of the super junction structure.
  • the impurity concentration distribution in the field stop layer may have the largest peak on the back surface side of the semiconductor substrate.
  • the field stop layer may have protons as impurities.
  • the impurity concentration distribution in the field stop layer may gradually decrease from the back surface side of the semiconductor substrate toward the front surface side of the semiconductor substrate.
  • the field stop layer may have selenium as an impurity.
  • the distance between the super junction structure and the field stop layer in the depth direction may be 20 ⁇ m or less.
  • the semiconductor device may have a superjunction transistor element and an IGBT element.
  • the superjunction transistor device may be formed on a semiconductor substrate.
  • the superjunction transistor device may include a superjunction structure and part of the field stop layer.
  • the IGBT element may be formed on a semiconductor substrate.
  • the IGBT device may include a portion of the field stop layer.
  • the semiconductor substrate may have a drain layer on the back side of the field stop layer.
  • the semiconductor substrate may have a floating region between the field stop layer and the drain layer.
  • the floating region may have a different polarity than the field stop and drain layers.
  • a second aspect of the present invention provides a method of manufacturing a semiconductor device, comprising the steps of: forming a superjunction structure on a semiconductor substrate; and forming a field stop layer.
  • the field stop layer may be formed at a position overlapping the super junction structure on the back surface side of the semiconductor substrate and not in contact with the back surface side end portion of the super junction structure.
  • the method of manufacturing the semiconductor device may further include the step of polishing the back surface side of the semiconductor substrate after the step of forming the super junction structure.
  • FIG. 6 is a plan view of the semiconductor device 200 as viewed from the front side of the semiconductor substrate 100.
  • FIG. 6 is a cross-sectional view of the semiconductor device 200 taken along line S1-S2.
  • (A) It is a figure which shows the impurity concentration in A1-A2 of the SJ-MOSFET part 10, and (b) the impurity concentration in B1-B2 of the IGBT part 20.
  • FIG. FIG. 16 is a diagram showing another example of the (a) impurity concentration in A1-A2 of the SJ-MOSFET unit 10 and (b) the impurity concentration in B1-B2 of the IGBT unit 20.
  • FIG. 4A is a view showing a step of forming an epitaxial layer 120, FIG.
  • FIG. 4B is a step of forming an epitaxial layer 122 doped with an impurity in multiple stages
  • FIG. 4C is a step of forming an epitaxial layer 124. It is a figure which shows (d) surface structure formation process and back surface grinding
  • FIG. 18 is a cross-sectional view of a semiconductor device 210 which is a modified example of the SJ-MOSFET unit 10
  • FIG. 1 is a plan view of a semiconductor device 200 as viewed from the surface side of a semiconductor substrate 100.
  • the semiconductor device 200 includes the semiconductor substrate 100.
  • the semiconductor substrate 100 is provided with an SJ-MOSFET unit 10 and an IGBT unit 20.
  • a breakdown voltage structure portion 30 is provided so as to surround the SJ-MOSFET portion 10 and the IGBT portion 20 in the xy plane.
  • the x direction is the direction perpendicular to the y direction.
  • the z direction is the direction perpendicular to the plane defined by the x and y directions.
  • the z direction may not necessarily be parallel to the direction of gravity.
  • the lengths in the x and y directions of the semiconductor substrate 100 are sufficiently larger than the lengths in the z direction.
  • the surface on the + z side of the semiconductor substrate 100 is referred to as the front surface, and the opposite surface is referred to as the back surface.
  • the xy plane is a plane parallel to the front and back surfaces of the semiconductor substrate 100.
  • the semiconductor device 200 of this example includes the SJ-MOSFET unit 10 and the IGBT unit 20, each of which has a longer y direction than the x direction. That is, the SJ-MOSFET unit 10 and the IGBT unit 20 have a stripe shape elongated in the y direction.
  • the semiconductor device 200 has a boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20.
  • the semiconductor device 200 has the SJ-MOSFET unit 10 at the end in the x direction.
  • the semiconductor device 200 has a repeated structure of the SJ-MOSFET portion 10 and the IGBT portion 20 along the x direction.
  • the semiconductor device 200 also has the SJ-MOSFET unit 10 at the end opposite to the x direction. That is, the semiconductor device 200 has the SJ-MOSFET unit 10 at both ends in the x direction.
  • the semiconductor device 200 has an IGBT portion 20 in a region sandwiched by the SJ-MOSFET portion 10 in a cross section obtained by cutting the semiconductor device 200 along the xz plane perpendicular to the surface of the semiconductor substrate 100.
  • the region sandwiched by the SJ-MOSFET portion 10 means a region in which the IGBT portion 20 in which both sides in the x direction are sandwiched by two SJ-MOSFET portions 10 is provided.
  • the SJ-MOSFET portion 10 has one or more super junction transistor regions. Also, the IGBT unit 20 has one or more IGBT regions. However, the SJ-MOSFET portion 10 has only a superjunction transistor region and does not have an IGBT region. Further, the IGBT portion 20 has only the IGBT region and does not have the super junction type transistor region.
  • the superjunction transistor region means a region of the smallest unit constituting the superjunction transistor.
  • the IGBT region means a region of the minimum unit constituting the IGBT.
  • the breakdown voltage of the IGBT region is higher than the breakdown voltage of the super junction transistor region.
  • the breakdown voltage of the IGBT region is about 700 V
  • the breakdown voltage of the super junction transistor region is about 650 V.
  • a group of superjunction transistor regions having two or more superjunction transistor regions is referred to as an SJ-MOSFET portion 10.
  • the plurality of SJ-MOSFET portions 10 in one semiconductor substrate 100 are collectively referred to as an SJ-MOSFET element 11.
  • a group of IGBT regions having two or more IGBT regions is referred to as an IGBT portion 20.
  • the plurality of IGBT units 20 in one semiconductor substrate 100 are collectively referred to as an IGBT element 21.
  • the semiconductor device 200 of this example repeatedly includes the SJ-MOSFET portion 10 and the IGBT portion 20 along the x direction, the super junction transistor region and the IGBT region are respectively provided in different places of the semiconductor substrate 100. Specifically, one or more IGBT regions are provided in a region where two or more super junction transistor regions are sandwiched. Further, the SJ-MOSFET unit 10 is provided at both ends of the semiconductor substrate 100 in the x direction.
  • the power supply of the semiconductor device 200 When the power supply of the semiconductor device 200 is turned on to gradually raise the drain-source voltage (V DS ) of the superjunction transistor region and the collector-emitter voltage (V CE ) of the IGBT region, predetermined voltage values are obtained.
  • the current (I CE ) flowing through the IGBT region is larger than the current (I DS ) flowing through the super junction transistor region.
  • the load on the superjunction transistor region and the IGBT region is determined by the product of the current (I CE or I DS ) and the voltage (V DS or V CE ). Therefore, when a voltage higher than the predetermined voltage value is applied, the load of the super junction transistor region is smaller than the load of the IGBT region.
  • the superjunction transistor region and the IGBT region are reverse biased.
  • the smaller the load in the on state the higher the breakdown resistance.
  • the load in the superjunction transistor region is smaller than the load in the IGBT region. Therefore, in reverse bias, the breakdown tolerance of the superjunction transistor region is higher than the breakdown tolerance of the IGBT region.
  • the super junction transistor region and the IGBT region are electrically connected in parallel.
  • the superjunction transistor region functions as a diode during reverse recovery. If the amount of the superjunction transistor region is too small, the semiconductor device 200 has a hard recovery characteristic at the time of reverse recovery. Therefore, in order to obtain a certain degree of soft recovery characteristics, a certain number of superjunction transistor regions are required. If the number of super junction type transistor regions is larger than the number of IGBT regions, the characteristics of the IGBT in the semiconductor device 200 are lost. Therefore, a balance between the two is required.
  • the semiconductor device 200 includes an IGBT unit 20 having two or more IGBT regions in regions sandwiched by the super junction transistor regions.
  • IGBT unit 20 having two or more IGBT regions in regions sandwiched by the super junction transistor regions.
  • two super junction type transistor regions and two IGBT regions are respectively provided.
  • the ratio of the number of IGBT regions in the IGBT portion 20 to the number of super junction type transistor regions in the SJ-MOSFET portion 10 varies depending on the use of the product, but is preferably 1: 1 to 3: 1.
  • the super junction type transistor regions and the IGBT regions are not provided alternately, but a plurality of super junction type transistor regions and the IGBT regions are provided alternately. Thereby, the ratio of the boundary 12 can be reduced as compared with the case where both are provided alternately.
  • the output characteristics of the super junction transistor region can be obtained in the low voltage region, and the output characteristics of the IGBT region can be obtained in the high voltage Is preferred.
  • the abnormal junction between the super junction type transistor region and the IGBT region causes anomalous voltage-current characteristics (ie, jumps in characteristics). Can occur. Therefore, it is not desirable to provide alternating super junction transistor regions and IGBT regions alternately.
  • FIG. 2 is a cross-sectional view of the semiconductor device 200 taken along S1-S2.
  • the semiconductor device 200 in the cross-sectional view has an SJ-MOSFET portion 10, an IGBT portion 20, a boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20, and a breakdown voltage structure portion 30.
  • the first conductivity type is described as n-type
  • the second conductivity type is described as p-type.
  • this may be inverted to make the first conductivity type p-type and the second conductivity type n-type.
  • the n-type and p-type of the semiconductor substrate 100 can be formed by a known element and a known preparation method unless the element and the preparation method are specified.
  • the SJ-MOSFET portion 10 has a super junction structure formed on the surface side of the semiconductor substrate 100.
  • the superjunction structure means an n-type column 54 and a p-type column 56 repeatedly provided adjacent to each other in the x direction of the superjunction transistor region 14.
  • the SJ-MOSFET portion 10 has two or more superjunction transistor regions 14.
  • the SJ-MOSFET portion 10 has five superjunction transistor regions 14.
  • only one super junction type transistor region 14 is denoted by reference numeral in consideration of the viewability of the figure.
  • the superjunction transistor region 14 includes a p-type base layer 42, a contact region 44, a source region 45, a gate electrode 50, a gate insulating film 52, and an n-type column 54 and a p-type column 56 adjacent in the x direction. .
  • the p-type base layer 42 has ap ⁇ -type impurity
  • the contact region 44 has ap + -type impurity
  • the source region 45 has an n + -type impurity.
  • the n-type column 54 adjacent in the x direction has an n-type impurity
  • the p-type column 56 has ap-type impurity.
  • Two adjacent superjunction transistor regions 14 share one n-type column 54 or one p-type column 56. In this example, two adjacent superjunction transistor regions 14 share one n-type column 54. Also, two adjacent super junction transistor regions 14 share one gate electrode 50 and gate insulating film 52.
  • the IGBT portion 20 has two or more IGBT regions 24. In the portion shown in FIG. 2, IGBT portion 20 has six IGBT regions 24. However, in consideration of the legibility of the drawing, only one IGBT region 24 is denoted by a reference numeral.
  • the IGBT region 24 includes a p-type base layer 42, a contact region 44, an emitter region 46, a gate electrode 50, a gate insulating film 52, and an n-type base layer 40.
  • Emitter region 46 has an n + -type impurity.
  • Two adjacent IGBT regions 24 share an n-type base layer 40. Further, two adjacent IGBT regions 24 share one gate electrode 50 and gate insulating film 52.
  • the distance between the gate electrodes 50 of the adjacent IGBT regions 24 is made the adjacent super junction type
  • the distance between the gate electrodes 50 of the transistor region 14 is made wider.
  • the breakdown voltage of the IGBT region can also be increased by decreasing the impurity concentration of the n-type base layer 40 in the IGBT region.
  • the n-type base layer 40 in the boundary portion 12 of this example has a larger amount of carriers than the n-type column 54 of the SJ-MOSFET portion 10 when a forward voltage is applied to the semiconductor device 200 to turn it on.
  • This is a region in which the amount of carriers is smaller than that of the n-type base layer 40 of the IGBT unit 20.
  • the carriers in the IGBT region 24 are holes and electrons, and the carriers in the superjunction transistor region 14 are electrons only. Therefore, when the semiconductor device 200 is operated at a forward voltage, the amount of carriers in the IGBT region 24 is larger than the amount of carriers in the superjunction transistor region 14. For example, the amount of carriers in the IGBT region 24 is one digit larger than the amount of carriers in the superjunction transistor region 14.
  • the n-type base of the boundary portion between the SJ-MOSFET portion 10 and the IGBT portion 20 is a portion where the carrier amount rapidly changes. In this case, since the electric field is strongly applied to the n-type base layer 40 in the boundary portion, the semiconductor device 200 may be broken down and destroyed.
  • the n-type base layer 40 of the boundary portion 12 a region having a carrier amount intermediate between the carrier amount of the n-type column 54 and the carrier amount of the n-type base layer 40 when a forward voltage is applied is provided.
  • the n-type base layer 40 as a drift region at the boundary 12 between the IGBT region 24 and the super junction transistor region 14 has a defect region 58 in which a lifetime killer is injected.
  • the injection of the lifetime killer means that the n-type base layer 40 is formed by injecting an electron beam, proton (H + ) or helium (He) from the front side and / or the back side of the semiconductor substrate 100 in the manufacturing process. It may mean that a defect region 58 having a lattice defect is formed in
  • the boundary portion 12 has the defect region 58, the change in carrier amount between the n-type column 54 and the n-type base layer 40 can be smoothed when the semiconductor device 200 is reverse biased. Therefore, the electric field concentration in the n-type base layer 40 of the boundary 12 can be prevented at the time of reverse bias, and the semiconductor device 200 can be prevented from being broken.
  • the structure on the surface side of the semiconductor substrate 100 is the same in the SJ-MOSFET portion 10 and the IGBT portion 20.
  • the gate electrode 50 of this example is a trench type gate electrode. Gate electrode 50 is electrically insulated from semiconductor substrate 100 by gate insulating film 52. The p-type base layer 42 and the contact region 44 are provided between the two gate electrodes 50.
  • a source region 45 is provided between the contact region 44 and the gate electrode 50.
  • an emitter region 46 is provided between the contact region 44 and the gate electrode 50.
  • the insulating layer 60 is provided on the surface side of the gate electrode 50.
  • the surface electrode 62 is provided on the surface side of the insulating layer 60.
  • the surface electrode 62 is in contact with at least the contact region 44 among the contact region 44, the source region 45 and the emitter region 46.
  • the structure on the surface side of the boundary portion 12 is substantially the same as the SJ-MOSFET portion 10 and the IGBT portion 20. However, the emitter region 46 is not provided between the boundary portion 12 and the IGBT portion 20. Thereby, the boundary 12 is prevented from operating as the IGBT region 24.
  • the n-type layer 70 is provided on the back surface side of the n-type base layer 40 in contact with the n-type base layer 40 in the IGBT section 20.
  • the n-type layer 70 is provided on the back surface side of the superjunction structure in contact with the superjunction structure of the n-type column 54 and the p-type column 56.
  • the n-type column 54 and the p-type column 56 in the SJ-MOSFET portion 10 are in direct contact with the FS layer 72. Since the FS layer 72 is n + type and the n type column 54 is n ⁇ type, when the n type column 54 and the FS layer 72 are in direct contact, the carrier amount of the n type column 54 is increased. As a result, the balance between the amount of electrons that are carriers of the n-type column 54 and the amount of holes that are carriers of the p-type column 56 is lost.
  • the n-type layer 70 is provided to balance the carrier amounts of the n-type column 54 and the p-type column 56.
  • the n-type layer 70 may be the same n-type as the n-type column 54.
  • the SJ-MOSFET unit 10 improves the withstand voltage when the reverse voltage is applied.
  • the FS layer 72 is a field stop layer.
  • the FS layer 72 is provided on the back side of the n-type layer 70.
  • the FS layer 72 is formed at a position overlapping the super junction structure of the SJ-MOSFET portion 10 on the back surface side of the semiconductor substrate 100 and is formed so as not to be in contact with the back surface side end of the super junction structure.
  • the FS layer 72 may be formed by heat treatment with a dose of proton (H + ) or selenium (Se).
  • the FS layer 72 in this example is an n + layer.
  • the FS layer 72 prevents the depletion layer from reaching the collector layer 80 when the semiconductor device 200 is reverse biased. In the FS layer 72, a part of the defect region 58 is formed.
  • the collector layer 80 is provided on the back side of the FS layer 72. That is, the collector layer 80 is provided on the back side of the FS layer 72.
  • the collector layer 80 functions as a collector layer of the IGBT unit 20.
  • the collector layer 80 in this example is a p + -type layer.
  • the drain layer 82 is provided on the back side of the FS layer 72.
  • the drain layer 82 functions as a drain layer of the SJ-MOSFET unit 10.
  • the drain layer 82 in this example is an n + -type layer.
  • IGBT region 24 further includes a part of n-type layer 70, a part of FS layer 72, a part of collector layer 80, and a part of back surface electrode 90.
  • the semiconductor device 200 includes the withstand voltage structure 30 provided outside the outermost super junction transistor region 14 in the super junction transistor region 14.
  • the pressure resistant structure portion 30 has a first pressure resistant portion 32 provided on the inner circumferential portion in the xy plane and a second pressure resistant portion 34 provided on the outer circumferential portion in the xy plane.
  • the first pressure portion 32 has a guard ring 47.
  • the guard ring 47 of this example is p + -type.
  • Guard ring 47 is provided on the surface side of n-type region 48.
  • the first pressure-resistant portion 32 has a field plate 64 connected to the guard ring 47 through a slit or a hole provided in the insulating layer 60.
  • the field plate 64 and the guard ring 47 are provided in a ring shape surrounding the SJ-MOSFET portion 10 and the IGBT portion 20 in the xy plane.
  • the first breakdown voltage unit 32 has a repeated structure of the n-type column 54 and the p-type column 56.
  • the n-type column 54 and the p-type column 56 are present from the back side end of the n-type region 48 to the front side end of the FS layer 72.
  • the repeated structure of the n-type column 54 and the p-type column 56 can prevent the spread of the depletion layer in the xy plane direction when the semiconductor device 200 is reverse biased.
  • the field plate 64 collects surface charges collected on the surface of the semiconductor substrate 100, it is possible to prevent the withstand voltage of the semiconductor device 200 from changing due to the surface charges.
  • the second withstand voltage portion 34 has an n-type region 48 as a first conductivity type region.
  • the second withstand voltage section 34 has a p-type region 49 as a second conductivity type column.
  • An n-type base layer 40 exists between the n-type region 48 and the FS layer 72 of the second withstand voltage portion 34.
  • the p-type region 49 is spaced apart in the n-type base layer 40. The depth of the end of the p-type region 49 is shallower than the depth of the end of the p-type column 56 of the superjunction transistor region 14.
  • the depth of the end of the p-type column 56 means the z coordinate at the end of the p-type column 56 near the FS layer 72.
  • the depth of the end of the p-type region 49 means the z-coordinate at the end of the p-type region 49 on the back side. When the depth of the end portion is shallow, it means that the end portion located on the back surface side is located on the front surface side when compared with the z coordinate of the end portion.
  • the pitch width P1 of the p-type column 56 in the first breakdown voltage unit 32 and the pitch width P1 of the p-type region 49 in the second breakdown voltage unit 34 have the same pitch width.
  • the pitch width P1 is smaller than the pitch width P2 of the p-type column 56 in the SJ-MOSFET unit 10.
  • the second breakdown voltage section 34 has a larger n-type region than the p-type region. . Therefore, when the reverse bias depletion layer of the semiconductor device 200 spreads from the first breakdown voltage section 32 to the second breakdown voltage section 34, carriers mainly composed of electrons are supplied to the depletion layer from the n-type base layer 40. Be done. This can prevent the depletion layer from reaching the x-direction end of the semiconductor substrate 100.
  • FIG. 3 is a diagram showing (a) the impurity concentration in A1-A2 of the SJ-MOSFET unit 10 and (b) the impurity concentration in B1-B2 of the IGBT unit 20.
  • the horizontal axis indicates the length in the z direction ( ⁇ m) as thickness, and the vertical axes on both ends indicate n-type and p-type impurity concentrations (cm ⁇ 3 ).
  • the lengths from A1 to A2 and the lengths from B1 to B2 are equal, and both are the thickness of the semiconductor substrate 100.
  • the thickness of the semiconductor substrate 100 is adjusted in accordance with the withstand voltage of the semiconductor device 200. When the withstand voltage of the semiconductor device 200 is 600 V to 1200 V, the thickness of the semiconductor substrate 100 may be 60 ⁇ m to 120 ⁇ m.
  • n type layer 70 (n ⁇ type) sequentially from A1 to A2 of the SJ-MOSFET portion 10 , FS layer 72 (n + type) and drain layer 82 (n + type) are provided.
  • the n-type layer 70 between the n-type column 54 and the FS layer 72 is a region that is not affected by the impurities used to form the FS layer 72. That is, it is a region to which the impurity used to form the FS layer 72 does not diffuse.
  • the FS layer 72 is formed by impurity doping from the back side.
  • the FS layer 72 contains selenium (Se) as an impurity.
  • the impurity concentration distribution in the FS layer 72 is formed so as to gradually decrease from the back surface side to the front surface side of the semiconductor substrate 100.
  • selenium doped from the back surface side of the semiconductor substrate 100 is thermally diffused to the surface side of the semiconductor substrate 100 by heat treatment after doping.
  • the heat treatment temperature and heat treatment time are controlled so that the doped selenium does not reach the n-type column 54.
  • the heat treatment may be about 900 ° C., and the heat treatment time may be about 2 hours. This forms an n-type layer 70 free of doped selenium.
  • the thickness of the n-type layer 70 is the distance in the depth direction between the superjunction structure of the n-type column 54 and the p-type column 56 and the FS layer 72.
  • the depth direction may be a direction parallel to the z direction, may be a direction from the super junction structure to the FS layer 72, or may be a direction from the FS layer 72 to the super junction structure.
  • the thickness of the n-type layer 70 may be a constant thickness regardless of the thickness of the substrate.
  • the thickness of the n-type layer 70 is 20 ⁇ m or less.
  • the thickness of the n-type layer 70 may be 20, 15, 10, 9, 5, .. 3 or 1 ⁇ m. In this example, the thickness of the n-type layer 70 is 3 to 5 ⁇ m.
  • phosphorus (P) can not be used as an impurity for forming the FS layer 72 of this example.
  • Phosphorus can not be deeply doped to the surface side even if it is doped from the back side. For example, at most 1.5 ⁇ m can be doped from the back side.
  • phosphorus can not be driven in deeply from the back side to the front side even by heat treatment. Therefore, when phosphorus is used, the thickness of the n-type layer 70 is larger than 20 ⁇ m, and the thickness of the FS layer 72 is relatively reduced.
  • the FS layer 72 can suppress the spread of the depletion layer by having a higher impurity concentration than the n-type layer 70, the position as close to the n-type layer 70 as possible in order to exert the function of the FS layer 72. It is better to dope the FS layer 72 with impurities. Therefore, as the impurity of the FS layer 72, it is preferable to use the aforementioned selenium or proton instead of phosphorus.
  • the combined thickness of the FS layer 72 and the drain layer 82 is about 25 ⁇ m. However, depending on the thickness of the semiconductor substrate 100, the combined thickness of the FS layer 72 and the drain layer 82 may be adjusted as appropriate.
  • the drain layer 82 is formed by further doping the FS layer 72 with an n-type impurity.
  • B1-B2 differs from A1-A2 in that it has an n-type base layer 40 instead of the n-type column 54, and a collector layer 80 instead of the drain layer 82. The other points are the same as A1-A2.
  • the n-type base layer 40 is the same n-type as the n-type column 54.
  • the impurity concentration of the n-type base layer 40 may be the same as the impurity concentration of the n-type layer 70.
  • FIG. 4 is a diagram showing another example of (a) the impurity concentration in A1-A2 of the SJ-MOSFET unit 10 and (b) the impurity concentration in B1-B2 of the IGBT unit 20.
  • the present example differs from the example of FIG. 3 in that the FS layer 72 contains protons as impurities.
  • the other points are the same as in the example of FIG.
  • the FS layer 72 is formed to have a plurality of peaks from the front side to the back side. However, the peak value is formed so as to gradually decrease from the back side to the front side.
  • the impurity concentration distribution in the FS layer 72 has the largest peak on the back surface side of the semiconductor substrate 100.
  • the FS layer 72 can supply sufficient carriers when applying a reverse voltage, and the amount of carriers can be suppressed near the n-type layer 70.
  • the peaks of the impurity concentration are provided at three different z coordinate positions, but the number of peaks is not limited to three, and may be four or more.
  • the FS layer 72 having a plurality of proton impurity concentration peaks can be formed by adjusting the acceleration voltage and the doping amount in multiple times.
  • protons can be doped more on the surface side by increasing the acceleration voltage.
  • the acceleration voltage may be appropriately selected in the range of 1.45 MeV to 0.4 MeV
  • the doping amount of impurities may be appropriately selected in the range of 1E + 12 cm ⁇ 2 to 3E + 14 cm ⁇ 2 .
  • FIG. 5 is a view showing (a) forming an epitaxial layer 120, (b) forming an epitaxial layer 122 doped with impurities in multiple stages, and (c) forming an epitaxial layer 124.
  • the epitaxial layer 120 is formed in contact with the surface side of the semiconductor substrate 110.
  • both the semiconductor substrate 110 and the epitaxial layer 120 are n-type.
  • the p-type impurity and the n-type impurity are locally doped in different places from the surface side of the epitaxial layer 120 (FIG. 5B).
  • the p-type impurity may be boron (B) and the n-type impurity may be phosphorus (P).
  • the epitaxial layer 122 is formed on the surface side of the epitaxial layer 120.
  • the epitaxial layer 122 is n-type as the epitaxial layer 120 is.
  • p-type impurities and n-type impurities are locally doped from different positions on the surface side of the epitaxial layer 122.
  • the x and y coordinates of the positions at which the n-type impurity and the p-type impurity are respectively doped are approximately the same.
  • to make the x and y coordinates of the doping position approximately coincide with each other may mean that it is within the error range of the mask alignment accuracy used for doping the impurity.
  • the formation of the epitaxial layer 122 and the local doping of the p-type impurity and the n-type impurity are repeated a plurality of times.
  • heat treatment is performed to form an epitaxial layer 124 having an n-type base layer 40, an n-type column 54 and a p-type column 56.
  • a super junction structure having the n-type column 54 and the p-type column 56 is formed in the semiconductor substrate 110.
  • FIG. 6 is a diagram showing (d) a surface structure forming step and a back surface structure polishing step, (e) a FS layer forming step, and (f) a back surface structure forming step.
  • step of (c) of FIG. 5 is the step of (d) of FIG.
  • FIG. 6 (d) Surface Structure Forming Step and Back Surface Polishing Step First, a lifetime killer is introduced from the surface side (+ z side) and / or the back side ( ⁇ z side) to form a defect region 58. Thereafter, a surface structure including gate electrode 50, gate insulating film 52, p-type base layer 42, contact region 44, source region 45, emitter region 46, insulating layer 60, and surface electrode 62 is formed. Next, the back surface side ( ⁇ z side) of the semiconductor substrate 110 is polished. Note that the entire thickness of the semiconductor substrate 110 may not be removed by polishing. That is, the semiconductor substrate 110 may remain its thickness after polishing. The thickness variation of the semiconductor substrate 100 resulting from the back surface polishing is 3 to 5 ⁇ m.
  • the above-mentioned back side polishing is not performed. This is because the SJ-MOSFET device is not a device that adjusts the breakdown voltage by the thickness of the semiconductor substrate like an IGBT device. It is one of the features in the present specification to have a polishing process when forming the semiconductor device 200 having the SJ-MOSFET portion 10.
  • Step of Forming FS Layer 72 Next, on the back surface side of the semiconductor substrate 110, the superjunction structure of the n-type column 54 and the p-type column 56 and the n-type base layer 40 overlap each other, The FS layer 72 is formed so as not to be in contact with the back surface side end of the super junction structure. As described above, the FS layer 72 may be formed by doping with selenium or by doping with protons multiple times.
  • a collector layer 80 is formed by counterdoping a p-type impurity into the FS layer 72 from the back surface side of the IGBT portion 20. Then, as shown in FIG. Collector layer 80 may also be provided on the back side of boundary 12. Further, the drain layer 82 is formed by further doping the FS layer 72 with an n-type impurity from the back surface side of the SJ-MOSFET portion 10. Finally, the back electrode 90 is formed on the back side of the collector layer 80 and the drain layer 82. The back electrode 90 may be an aluminum layer formed by a sputtering method.
  • FIG. 7 is a cross-sectional view of a semiconductor device 210 which is a modified example of the SJ-MOSFET unit 10.
  • the semiconductor substrate 100 has a floating region 84 between the FS layer 72 and the drain layer 82.
  • the floating region 84 has a p-type impurity different in polarity from the FS layer 72 (n + -type) and the drain layer 82 (n + -type).
  • the other points are the same as in the example of FIG.
  • the p-type floating region 84 When the p-type floating region 84 is brought into contact with the back electrode 90, the on voltage rises. Therefore, the p-type floating region 84 is not in contact with the back electrode 90.
  • the p-type floating region 84 may be provided only in the drain layer 82 unless the p-type floating region 84 is in contact with the back surface electrode 90.
  • the diode formed of the p-type floating region 84 and the drain layer 82 performs avalanche breakdown when a high voltage is applied during reverse recovery. A hole is injected. Therefore, the soft recovery characteristic of the IGBT unit 20 at the time of applying the reverse voltage can be further improved.

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Abstract

　ＳＪ‐ＭＯＳＦＥＴおよびＩＧＢＴを１つの半導体チップに設ける。加えて、ｎ型カラム５４のキャリア量とｐ型カラム５６のキャリア量とのバランスを取ることにより、ＳＪ‐ＭＯＳＦＥＴ部１０において逆電圧印加時に空乏層の形成を促進させる。半導体基板と、半導体基板の表面側に形成された超接合構造と、半導体基板の裏面側において超接合構造と重なる位置に形成され、且つ、超接合構造の裏面側端部と接しないように形成されたフィールドストップ層とを備える半導体装置を提供する。

Description

半導体装置および半導体装置の製造方法
　従来、超接合型ＭＯＳＦＥＴを有する半導体チップと、絶縁ゲートバイポーラトランジスタを有する半導体チップとを並列に接続していた（例えば、特許文献１参照）。なお、超接合（Ｓｕｐｅｒ　Ｊｕｎｃｔｉｏｎ）は、以下においてＳＪと略記する。また、絶縁ゲートバイポーラトランジスタ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）は、以下においてＩＧＢＴと略記する。また従来、ｐ＋コレクタ層を有するＳＪ‐ＭＯＳＦＥＴ構造が知られている（例えば、特許文献２参照）。
［先行技術文献］
［特許文献］
　［特許文献１］　特開２０１４－１３０９０９号公報（米国特許出願公開第２０１４／１８４３０３号明細書）
　［特許文献２］　特開２０１３－１０２１１１号公報（米国特許出願公開第２０１３／１３４４７８号明細書）
　しかしながら、特許文献１では、ＳＪ‐ＭＯＳＦＥＴを有する半導体チップとＩＧＢＴを有する半導体チップとを配線により接続してモジュール化する。それゆえ、ＳＪ‐ＭＯＳＦＥＴおよびＩＧＢＴを１つの半導体チップに形成する場合と比較して、モジュールを小型化することができない。また、特許文献２では、プロトンを有する空乏層緩和領域の上側縁がｐ型カラム層の底面とほぼ一致するように設けられる（図１、段落００５５および段落００５６）。これにより、ドナー化したプロトンとｎ－型ベース層とが接触するので、ｎ－型ベース層のキャリアである電子がｐ型カラム層のキャリアである正孔よりも多くなり、キャリアのバランスが崩れる。従って、ｎ－型ベース層とｐ型カラム層とにより空乏層が形成されにくい。
　本発明の第１の態様においては、半導体基板と、超接合構造と、フィールドストップ層とを備える半導体装置を提供する。超接合構造は、半導体基板の表面側に形成されてよい。フィールドストップ層は、半導体基板の裏面側において超接合構造と重なる位置に形成され、且つ、超接合構造の裏面側端部と接しないように形成されてよい。
　フィールドストップ層における不純物濃度分布は、半導体基板の最も裏面側に最大ピークを有してよい。フィールドストップ層は、プロトンを不純物として有してよい。
　フィールドストップ層における不純物濃度分布は、半導体基板の裏面側から半導体基板の表面側に向けて徐々に減少してよい。フィールドストップ層は、セレンを不純物として有してよい。
　超接合構造とフィールドストップ層との深さ方向における距離は、２０μｍ以下であってよい。半導体装置は、超接合型トランジスタ素子と、ＩＧＢＴ素子とを有してよい。超接合型トランジスタ素子は、半導体基板に形成されてよい。超接合型トランジスタ素子は、超接合構造と、フィールドストップ層の一部とを含んでよい。ＩＧＢＴ素子は、半導体基板に形成されてよい。ＩＧＢＴ素子は、フィールドストップ層の一部を含んでよい。
　半導体基板は、フィールドストップ層よりも裏面側にドレイン層を有してよい。半導体基板は、フィールドストップ層とドレイン層との間に、フローティング領域を有してよい。フローティング領域は、フィールドストップ層およびドレイン層とは異なる極性を有してよい。
　本発明の第２の態様においては、半導体基板に超接合構造を形成する工程と、フィールドストップ層を形成する工程と、を備える半導体装置の製造方法を提供する。フィールドストップ層を形成する工程においては、半導体基板の裏面側において超接合構造と重なる位置であり、且つ、超接合構造の裏面側端部と接しないように、フィールドストップ層を形成してよい。また、半導体装置の製造方法は、超接合構造を形成する工程の後に、半導体基板の裏面側を研磨する工程をさらに備えてよい。
　なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではない。また、これらの特徴群のサブコンビネーションもまた、発明となりうる。
半導体装置２００を半導体基板１００の表面側から見た平面図である。 半導体装置２００のＳ１－Ｓ２断面図である。 （ａ）ＳＪ‐ＭＯＳＦＥＴ部１０のＡ１‐Ａ２における不純物濃度、および、（ｂ）ＩＧＢＴ部２０のＢ１‐Ｂ２における不純物濃度を示す図である。 （ａ）ＳＪ‐ＭＯＳＦＥＴ部１０のＡ１‐Ａ２における不純物濃度、および、（ｂ）ＩＧＢＴ部２０のＢ１‐Ｂ２における不純物濃度の他の例を示す図である。 （ａ）エピタキシャル層１２０の形成工程、（ｂ）不純物をドープしたエピタキシャル層１２２を多段形成する工程、ならびに、（ｃ）エピタキシャル層１２４を形成する工程を示す図である。 （ｄ）表面構造形成工程および裏面研磨工程、（ｅ）ＦＳ層７２形成工程、ならびに、（ｆ）裏面構造形成工程を示す図である。 ＳＪ‐ＭＯＳＦＥＴ部１０の変形例である半導体装置２１０の断面図である。
　以下、発明の実施の形態を通じて本発明を説明するが、以下の実施形態は請求の範囲にかかる発明を限定するものではない。また、実施形態の中で説明されている特徴の組み合わせの全てが発明の解決手段に必須であるとは限らない。
　図１は、半導体装置２００を半導体基板１００の表面側から見た平面図である。半導体装置２００は、半導体基板１００を備える。半導体基板１００には、ＳＪ‐ＭＯＳＦＥＴ部１０およびＩＧＢＴ部２０が設けられる。半導体基板１００には、ＳＪ‐ＭＯＳＦＥＴ部１０およびＩＧＢＴ部２０をｘ‐ｙ平面において囲むように耐圧構造部３０が設けられる。
　本明細書において、ｘ方向はｙ方向に垂直な方向である。ｚ方向は、ｘ方向およびｙ方向により規定される平面に垂直な方向である。ｚ方向は、必ずしも重力の方向と平行でなくてよい。半導体基板１００のｘ方向およびｙ方向の長さは、そのｚ方向の長さよりも十分に大きい。本明細書においては便宜的に、半導体基板１００の＋ｚ側の面を表面と称し、その反対側の面を裏面と称する。ｘ‐ｙ平面は半導体基板１００の表面および裏面に平行な面である。
　本例の半導体装置２００は、それぞれｘ方向よりもｙ方向が長いＳＪ‐ＭＯＳＦＥＴ部１０およびＩＧＢＴ部２０を有する。つまり、ＳＪ‐ＭＯＳＦＥＴ部１０およびＩＧＢＴ部２０は、ｙ方向に長いストライプ形状を有する。半導体装置２００は、ＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０との間に境界部１２を有する。
　半導体装置２００は、ｘ方向の端部にＳＪ‐ＭＯＳＦＥＴ部１０を有する。半導体装置２００はｘ方向に沿って、ＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０との繰り返し構造を有する。また半導体装置２００は、ｘ方向の反対側の端部に、ＳＪ‐ＭＯＳＦＥＴ部１０を有する。つまり、半導体装置２００は、ｘ方向の両端部にはＳＪ‐ＭＯＳＦＥＴ部１０を有する。
　半導体装置２００は、半導体基板１００の表面に垂直なｘ‐ｚ面で半導体装置２００を切断した断面において、ＳＪ‐ＭＯＳＦＥＴ部１０が挟む領域に、ＩＧＢＴ部２０を有する。なお、ＳＪ‐ＭＯＳＦＥＴ部１０が挟む領域とは、２つのＳＪ‐ＭＯＳＦＥＴ部１０によりｘ方向の両側が挟まれたＩＧＢＴ部２０が設けられる領域を意味する。
　ＳＪ‐ＭＯＳＦＥＴ部１０は、１以上の超接合型トランジスタ領域を有する。また、ＩＧＢＴ部２０は、１以上のＩＧＢＴ領域を有する。ただし、ＳＪ‐ＭＯＳＦＥＴ部１０は、超接合型トランジスタ領域のみを有しＩＧＢＴ領域は有しない。また、ＩＧＢＴ部２０は、ＩＧＢＴ領域のみを有し超接合型トランジスタ領域は有しない。
　本明細書において、超接合型トランジスタ領域は、超接合型トランジスタを構成する最小単位の領域を意味する。また、ＩＧＢＴ領域は、ＩＧＢＴを構成する最小単位の領域を意味する。ＩＧＢＴ領域の耐圧は、超接合型トランジスタ領域の耐圧より高い。例えば、ＩＧＢＴ領域の耐圧は約７００Ｖであり、超接合型トランジスタ領域の耐圧は約６５０Ｖである。なお、超接合型トランジスタ領域およびＩＧＢＴ領域の詳細な構成については次図の説明において述べる。
　本明細書において、２以上の超接合型トランジスタ領域を有する超接合型トランジスタ領域の群をＳＪ‐ＭＯＳＦＥＴ部１０とする。また、１つの半導体基板１００における複数のＳＪ‐ＭＯＳＦＥＴ部１０をまとめてＳＪ‐ＭＯＳＦＥＴ素子１１と称する。同様に、２以上のＩＧＢＴ領域を有するＩＧＢＴ領域の群をＩＧＢＴ部２０とする。また、１つの半導体基板１００における複数のＩＧＢＴ部２０をまとめてＩＧＢＴ素子２１と称する。
　本例の半導体装置２００は、ｘ方向に沿ってＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０とを繰り返し有するので、超接合型トランジスタ領域とＩＧＢＴ領域とはそれぞれ、半導体基板１００の異なる場所に設けられる。具体的には、１以上のＩＧＢＴ領域は、２以上の超接合型トランジスタ領域が挟む領域に設けられる。また、半導体基板１００のｘ方向の両端部にはＳＪ‐ＭＯＳＦＥＴ部１０が設けられる。
　半導体装置２００の電源をオンにして、超接合型トランジスタ領域のドレイン‐ソース間電圧（ＶＤＳ）およびＩＧＢＴ領域のコレクタ‐エミッタ間電圧（ＶＣＥ）を徐々に上昇させると、所定の電圧値を境にして、ＩＧＢＴ領域を流れる電流（ＩＣＥ）が超接合型トランジスタ領域を流れる電流（ＩＤＳ）よりも多くなる。超接合型トランジスタ領域およびＩＧＢＴ領域への負荷は、電流（ＩＣＥまたはＩＤＳ）と電圧（ＶＤＳまたはＶＣＥ）との積で決まる。それゆえ、当該所定の電圧値よりも高い電圧をかける場合、超接合型トランジスタ領域の負荷はＩＧＢＴ領域の負荷よりも小さくなる。
　半導体装置２００の電源をオフすると超接合型トランジスタ領域およびＩＧＢＴ領域は逆バイアス状態となる。逆バイアス時において、オン状態での負荷が小さい方が破壊耐量は高くなる。所定の電圧値よりも高い電圧をかけたオン状態では、超接合型トランジスタ領域の負荷はＩＧＢＴ領域の負荷よりも小さい。それゆえ、逆バイアス時において、超接合型トランジスタ領域の破壊耐量はＩＧＢＴ領域の破壊耐量よりも高い。
　半導体基板１００において、超接合型トランジスタ領域とＩＧＢＴ領域とは電気的に並列に接続されている。超接合型トランジスタ領域は、逆回復時にダイオードとして機能する。超接合型トランジスタ領域が少な過ぎると、半導体装置２００は逆回復時にハードリカバリー特性となる。そこで、ある程度のソフトリカバリー特性を得るべく、一定数の超接合型トランジスタ領域が必要となる。また、超接合型トランジスタ領域の数がＩＧＢＴ領域の数よりも多すぎると、半導体装置２００においてＩＧＢＴの特性が失われる。それゆえ、両者のバランスが求められる。
　半導体装置２００は、超接合型トランジスタ領域が挟む領域に、２以上のＩＧＢＴ領域を有するＩＧＢＴ部２０を有する。例えば、ＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０とにおいて、２つの超接合型トランジスタ領域と２つのＩＧＢＴ領域とをそれぞれ設ける。なお、ＩＧＢＴ部２０におけるＩＧＢＴ領域の数とＳＪ‐ＭＯＳＦＥＴ部１０における超接合型トランジスタ領域の数との比は、製品の用途によって異なるが、１：１から３：１となることが好ましい。
　本例では、超接合型トランジスタ領域とＩＧＢＴ領域とを１つおきではなく、超接合型トランジスタ領域とＩＧＢＴ領域とを複数個おきに設ける。これにより、両者を１つおきに設ける場合と比較して境界部１２の割合を減らすことができる。
　半導体基板１００に超接合型トランジスタ領域とＩＧＢＴ領域とを有する半導体装置２００では、低電圧領域では超接合型トランジスタ領域の出力特性が得られ、かつ、高電圧ではＩＧＢＴ領域の出力特性が得られることが好ましい。しかし、超接合型トランジスタ領域とＩＧＢＴ領域とを１つおきに交互に設ける構成では、超接合型トランジスタ領域とＩＧＢＴ領域とが干渉し合うことにより異常な電圧‐電流特性（つまり、特性のとび）が発生し得る。それゆえ、超接合型トランジスタ領域とＩＧＢＴ領域とを１つおきに交互に設ける構成は望ましくない。本例では、２以上の超接合型トランジスタ領域を有するＳＪ‐ＭＯＳＦＥＴ部１０と２以上のＩＧＢＴ領域を有するＩＧＢＴ部２０とを有するので、超接合型トランジスタ領域とＩＧＢＴ領域とを１つおきに交互に設ける構成と比較して、異常な電圧‐電流特性（特性のとび）を抑えることができる。
　図２は、半導体装置２００のＳ１－Ｓ２断面図である。当該断面図における半導体装置２００は、ＳＪ‐ＭＯＳＦＥＴ部１０と、ＩＧＢＴ部２０と、ＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０との間にある境界部１２と、耐圧構造部３０とを有する。なお本例では、第１導電型をｎ型とし、第２導電型をｐ型として記載する。しかし他の例においては、これを反転させて第１導電型をｐ型とし、第２導電型をｎ型としてもよい。なお、特に元素および作成手法を明示しない限り、半導体基板１００のｎ型およびｐ型は、周知の元素および周知の作成手法により形成することができる。
　ＳＪ‐ＭＯＳＦＥＴ部１０は、半導体基板１００の表面側に形成された超接合構造を有する。本明細書において超接合構造とは、超接合型トランジスタ領域１４のｘ方向に隣接して繰り返して設けられるｎ型カラム５４およびｐ型カラム５６を意味する。
　ＳＪ‐ＭＯＳＦＥＴ部１０は、２以上の超接合型トランジスタ領域１４を有する。本例では、ＳＪ‐ＭＯＳＦＥＴ部１０は５つの超接合型トランジスタ領域１４を有する。ただし、図の見やすさを考慮して１つの超接合型トランジスタ領域１４だけに符号を付している。超接合型トランジスタ領域１４は、ｐ型ベース層４２、コンタクト領域４４、ソース領域４５、ゲート電極５０、ゲート絶縁膜５２、および、ｘ方向に隣接するｎ型カラム５４とｐ型カラム５６とを含む。
　本例では、ｐ型ベース層４２はｐ－型不純物を有し、コンタクト領域４４はｐ＋型不純物を有し、ソース領域４５はｎ＋型不純物を有する。また、ｘ方向に隣接するｎ型カラム５４はｎ－型不純物を有し、ｐ型カラム５６はｐ－型不純物を有する。
　２つの隣接する超接合型トランジスタ領域１４は、１つのｎ型カラム５４または１つのｐ型カラム５６を共有する。本例では、２つの隣接する超接合型トランジスタ領域１４は、１つのｎ型カラム５４を共有する。また、２つの隣接する超接合型トランジスタ領域１４は、１つのゲート電極５０およびゲート絶縁膜５２を共有する。
　ＩＧＢＴ部２０は、２以上のＩＧＢＴ領域２４を有する。図２に示す部分においては、ＩＧＢＴ部２０は６つのＩＧＢＴ領域２４を有する。ただし、図の見やすさを考慮して１つのＩＧＢＴ領域２４だけに符号を付している。ＩＧＢＴ領域２４は、ｐ型ベース層４２、コンタクト領域４４、エミッタ領域４６、ゲート電極５０、ゲート絶縁膜５２、および、ｎ型ベース層４０を含む。なお、エミッタ領域４６はｎ＋型不純物を有する。
　隣接する２つのＩＧＢＴ領域２４はｎ型ベース層４０を共有する。また、隣接する２つのＩＧＢＴ領域２４は、１つのゲート電極５０およびゲート絶縁膜５２を共有する。
　なお、逆バイアス時において、超接合型トランジスタ領域１４の耐圧をＩＧＢＴ領域２４の耐圧よりも低くするには、必要に応じて隣接するＩＧＢＴ領域２４のゲート電極５０間の間隔を隣接する超接合型トランジスタ領域１４のゲート電極５０間の間隔より広くする。また、ＩＧＢＴ領域のｎ型ベース層４０の不純物濃度を低くすることでもＩＧＢＴ領域の耐圧を高くすることができる。
　（境界部１２）本例の境界部１２のｎ型ベース層４０は、半導体装置２００に順電圧を印加してオンさせる場合、ＳＪ‐ＭＯＳＦＥＴ部１０のｎ型カラム５４よりもキャリア量が多く、ＩＧＢＴ部２０のｎ型ベース層４０よりもキャリア量が少ない領域である。ＩＧＢＴ領域２４のキャリアは正孔および電子であり、超接合型トランジスタ領域１４のキャリアは電子のみである。それゆえ半導体装置２００を順電圧で動作させる場合、ＩＧＢＴ領域２４のキャリアの量は、超接合型トランジスタ領域１４のキャリア量よりも多い。例えば、ＩＧＢＴ領域２４のキャリア量は、超接合型トランジスタ領域１４のキャリア量よりも一桁多い。
　逆バイアス時において、仮に境界部１２が無くＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０とが接合して連続している場合には、ＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０との境界部分のｎ型ベース層４０は、キャリア量が急峻に変化する部分となる。この場合、境界部分のｎ型ベース層４０には電界が強くかかるので、半導体装置２００はブレークダウンして破壊される可能性がある。
　そこで、境界部１２のｎ型ベース層４０に、順電圧印加時においてｎ型カラム５４のキャリア量とｎ型ベース層４０のキャリア量との中間のキャリア量を有する領域を設ける。本例では、ＩＧＢＴ領域２４と超接合型トランジスタ領域１４との境界部１２におけるドリフト領域としてのｎ型ベース層４０に、ライフタイムキラーが注入されている欠陥領域５８を有する。ライフタイムキラーが注入されているとは、製造工程において半導体基板１００の表面側および／または裏面側から電子線、プロトン（Ｈ＋）またはヘリウム（Ｈｅ）を注入することにより、ｎ型ベース層４０に格子欠陥を有する欠陥領域５８が形成されることを意味してよい。
　境界部１２は、欠陥領域５８を有するので、半導体装置２００の逆バイアス時に、ｎ型カラム５４とｎ型ベース層４０との間におけるキャリア量の変化をなだらかにすることができる。よって、逆バイアス時に境界部１２のｎ型ベース層４０での電界集中を防ぎ、半導体装置２００が破壊されることを防ぐことができる。
　（表面構造）半導体基板１００の表面側の構造は、ＳＪ‐ＭＯＳＦＥＴ部１０とＩＧＢＴ部２０とで同じである。本例のゲート電極５０は、トレンチ型のゲート電極である。ゲート電極５０は、ゲート絶縁膜５２により半導体基板１００から電気的に絶縁される。ｐ型ベース層４２およびコンタクト領域４４は２つのゲート電極５０の間に設けられる。
　超接合型トランジスタ領域１４では、コンタクト領域４４とゲート電極５０との間にソース領域４５が設けられる。ＩＧＢＴ領域２４では、コンタクト領域４４とゲート電極５０との間にエミッタ領域４６が設けられる。
　絶縁層６０はゲート電極５０よりも表面側に設けられる。表面電極６２は、絶縁層６０よりも表面側に設けられる。表面電極６２は、コンタクト領域４４、ソース領域４５およびエミッタ領域４６のうち、少なくともコンタクト領域４４に接する。
　境界部１２の表面側の構造は、ＳＪ‐ＭＯＳＦＥＴ部１０およびＩＧＢＴ部２０とほぼ同じである。ただし、境界部１２とＩＧＢＴ部２０との間には、エミッタ領域４６を設けない。これにより、境界部１２がＩＧＢＴ領域２４として動作することを防止する。
　（裏面構造）ｎ型層７０は、ＩＧＢＴ部２０においては、ｎ型ベース層４０に接して、ｎ型ベース層４０の裏面側に設けられる。また、ｎ型層７０は、ＳＪ‐ＭＯＳＦＥＴ部１０においては、ｎ型カラム５４およびｐ型カラム５６の超接合構造に接して、超接合構造の裏面側に設けられる。
　仮にｎ型層７０を設けない場合、ＳＪ‐ＭＯＳＦＥＴ部１０においてｎ型カラム５４およびｐ型カラム５６とＦＳ層７２とは直接接することとなる。ＦＳ層７２はｎ＋型でありｎ型カラム５４はｎ－型であるので、ｎ型カラム５４とＦＳ層７２とが直接接すると、ｎ型カラム５４のキャリア量が増えることとなる。これにより、ｎ型カラム５４のキャリアである電子の量とｐ型カラム５６とのキャリアである正孔の量のバランスが崩れることとなる。
　ｎ型カラム５４とｐ型カラム５６とのキャリア量のバランスが崩れる場合は、逆電圧印加時にｎ型カラム５４とｐ型カラム５６とを完全空乏化することができない。そこで、ｎ型カラム５４とｐ型カラム５６とのキャリア量のバランスを取るべくｎ型層７０を設ける。本例においてｎ型層７０は、ｎ型カラム５４と同じｎ－型であってよい。
　ｎ型カラム５４とｐ型カラム５６とがそれぞれ同程度のキャリア量を有することにより電荷のプラスマイナス量が略等しくなる。これにより、逆電圧印加時にｎ型カラム５４とｐ型カラム５６とは完全空乏化される。従って、ＳＪ‐ＭＯＳＦＥＴ部１０は逆電圧印加時の耐圧を向上させる。
　ＦＳ層７２は、フィールドストップ（Ｆｉｅｌｄ　Ｓｔｏｐ）層である。ＦＳ層７２はｎ型層７０よりも裏面側に設けられる。ＦＳ層７２は、半導体基板１００の裏面側においてＳＪ‐ＭＯＳＦＥＴ部１０の超接合構造と重なる位置に形成され、且つ、超接合構造の裏面側端部と接しないように形成される。
　ＦＳ層７２は、プロトン（Ｈ＋）またはセレン（Ｓｅ）をドーズして熱処理することにより形成されてよい。本例のＦＳ層７２は、ｎ＋層である。ＦＳ層７２は、半導体装置２００に逆バイアス時に、空乏層がコレクタ層８０に到達するのを防ぐ。なお、ＦＳ層７２には、欠陥領域５８の一部が形成される。
　コレクタ層８０は、ＦＳ層７２よりも裏面側に設けられる。つまり、コレクタ層８０は、ＦＳ層７２よりも裏面側に設けられる。コレクタ層８０は、ＩＧＢＴ部２０のコレクタ層として機能する。本例のコレクタ層８０は、ｐ＋型の層である。
　ドレイン層８２は、ＦＳ層７２よりも裏面側に設けられる。ドレイン層８２は、ＳＪ‐ＭＯＳＦＥＴ部１０のドレイン層として機能する。本例のドレイン層８２は、ｎ＋型の層である。
　図２より明らかであるが、本例の超接合型トランジスタ領域１４は、ｎ型層７０の一部と、ＦＳ層７２の一部と、ドレイン層８２の一部と、裏面電極９０の一部とを含む。また、ＩＧＢＴ領域２４は、ｎ型層７０の一部と、ＦＳ層７２の一部と、コレクタ層８０の一部と、裏面電極９０の一部とをさらに含む。
　（ＳＪ‐ＭＯＳＦＥＴ部１０の動作）ＳＪ‐ＭＯＳＦＥＴ部１０の動作を簡単に説明する。ＳＪ‐ＭＯＳＦＥＴ部１０のゲート電極５０に所定の電圧が印加されると、ゲート絶縁膜５２とｐ型ベース層４２との境界近傍に反転層が形成される。また、半導体装置２００に順電圧が印加されている場合、ソース領域４５には、ドレイン層８２よりも高い所定の電圧が印加される。これにより、コンタクト領域４４、ソース領域４５、ｐ型ベース層４２に形成された反転層、ｎ型カラム５４、ＦＳ層７２およびドレイン層８２を順に通って、電子が表面電極６２から裏面電極９０へ流れる。
　（ＩＧＢＴ部２０の動作）ＩＧＢＴ部２０の動作を簡単に説明する。ＩＧＢＴ部２０のゲート電極５０に所定の電圧が印加される場合、ゲート絶縁膜５２とｐ型ベース層４２との境界近傍に反転層が形成される。また、半導体装置２００に順電圧が印加されている場合、エミッタ領域４６には、コレクタ層８０よりも高い所定の電圧が印加される。これにより、エミッタ領域４６からｎ型ベース層４０に電子が供給され、コレクタ層８０からｎ型ベース層４０に正孔が供給される。これにより、裏面電極９０から表面電極６２へ電流が流れる。
　（耐圧構造部３０）半導体装置２００は、超接合型トランジスタ領域１４のうち、最も外側の超接合型トランジスタ領域１４の外側に設けた耐圧構造部３０を備える。耐圧構造部３０は、ｘ‐ｙ平面における内周部に設けられる第１耐圧部３２と、ｘ‐ｙ平面における外周部に設けられる第２耐圧部３４とを有する。第１耐圧部３２は、ガードリング４７を有する。本例のガードリング４７はｐ＋型である。ガードリング４７は、ｎ型領域４８の表面側に設けられる。第１耐圧部３２は、絶縁層６０に設けられたスリットまたは穴を通じてガードリング４７に接続するフィールドプレート６４を有する。フィールドプレート６４およびガードリング４７は、ｘ‐ｙ平面においてＳＪ‐ＭＯＳＦＥＴ部１０およびＩＧＢＴ部２０を囲んでリング状に設けられる。
　第１耐圧部３２は、ＳＪ‐ＭＯＳＦＥＴ部１０と同様に、ｎ型カラム５４およびｐ型カラム５６の繰り返し構造を有する。ｎ型カラム５４およびｐ型カラム５６は、ｎ型領域４８の裏面側端部からＦＳ層７２の表面側端部までに渡って存在する。ｎ型カラム５４およびｐ型カラム５６の繰り返し構造により、半導体装置２００の逆バイアス時、ｘ‐ｙ平面方向への空乏層の広がりを防ぐことができる。また、フィールドプレート６４は、半導体基板１００の表面に集まってきた表面電荷を収集するので、表面電荷に起因して半導体装置２００の耐圧が変化することを防ぐことができる。
　第２耐圧部３４は、第１導電型領域としてのｎ型領域４８を有する。また第２耐圧部３４は、第２導電型カラムとしてのｐ型領域４９を有する。第２耐圧部３４のｎ型領域４８からＦＳ層７２までの間には、ｎ型ベース層４０が存在する。ｐ型領域４９は、ｎ型ベース層４０中に間隔を置いて設けられる。ｐ型領域４９の端部の深さは、超接合型トランジスタ領域１４のｐ型カラム５６の端部の深さよりも浅く設けられる。
　なお、ｐ型カラム５６の端部の深さとは、ｐ型カラム５６のＦＳ層７２近傍の端部におけるｚ座標を意味する。ｐ型領域４９の端部の深さとは、ｐ型領域４９の裏面側の端部におけるｚ座標を意味する。端部の深さが浅いとは、裏面側に位置する端部のｚ座標を比較した場合に、より表面側に位置することを意味する。
　第１耐圧部３２におけるｐ型カラム５６のピッチ幅Ｐ１と第２耐圧部３４におけるｐ型領域４９のピッチ幅Ｐ１とは、同じピッチ幅である。当該ピッチ幅Ｐ１は、ＳＪ‐ＭＯＳＦＥＴ部１０におけるｐ型カラム５６のピッチ幅Ｐ２よりも小さい。これにより、耐圧構造部３０のピッチ幅Ｐ１をＳＪ‐ＭＯＳＦＥＴ部１０のピッチ幅Ｐ２と同じにする場合よりも、逆バイアス時における半導体基板１００の端部への空乏層の広がりが抑えられるので、半導体装置２００を高耐圧化することができる。
　また、ｐ型領域４９の端部の深さをｐ型カラム５６の端部の深さよりも浅くすることにより、第２耐圧部３４にはｐ型の領域に比べてｎ型の領域が大きくなる。それゆえ、半導体装置２００の逆バイアス時空乏層が第１耐圧部３２から第２耐圧部３４に広がってきた場合に、当該空乏層にはｎ型ベース層４０から電子を主とするキャリアが供給される。これにより、空乏層が半導体基板１００のｘ方向端部に達するのを防ぐことができる。
　図３は、（ａ）ＳＪ‐ＭＯＳＦＥＴ部１０のＡ１‐Ａ２における不純物濃度、および、（ｂ）ＩＧＢＴ部２０のＢ１‐Ｂ２における不純物濃度を示す図である。横軸は厚みとしてのｚ方向の長さ（μｍ）を示し、両端の縦軸はともにｎ型およびｐ型の不純物濃度（ｃｍ－３）を示す。
　Ａ１からＡ２までの長さおよびＢ１からＢ２までの長さは等しく、共に半導体基板１００の厚みである。半導体装置２００の耐圧に応じて、半導体基板１００の厚みは調整される。半導体装置２００の耐圧が６００Ｖから１２００Ｖである場合、半導体基板１００の厚みは６０μｍから１２０μｍとしてよい。
　ＳＪ‐ＭＯＳＦＥＴ部１０のＡ１からＡ２にかけて順に、コンタクト領域４４（ｐ＋＋型）、ｐ型ベース層４２（ｐ－型）、ｐ型カラム５６（ｐ－型）、ｎ型層７０（ｎ－型）、ＦＳ層７２（ｎ＋型）、ドレイン層８２（ｎ＋型）が設けられる。ｎ型カラム５４とＦＳ層７２との間のｎ型層７０は、ＦＳ層７２の形成に用いる不純物の影響がない領域である。つまり、ＦＳ層７２の形成に用いる不純物が拡散しない領域である。
　ＦＳ層７２は、裏面側からの不純物ドーピングにより形成する。本例では、ＦＳ層７２は、セレン（Ｓｅ）を不純物として有する。ＦＳ層７２における不純物濃度分布は、半導体基板１００の裏面側から表面側に向けて徐々に減少するよう形成する。本例では、半導体基板１００の裏面側からドープされたセレンを、ドープ後の熱処理により半導体基板１００の表面側へ熱拡散させる。ドープされたセレンがｎ型カラム５４に到達しないように熱処理温度および熱処理時間を制御する。熱処理は約９００℃であってよく、熱処理時間は約２時間であってよい。これにより、ドープしたセレンが存在しないｎ型層７０を形成する。
　ｎ型層７０の厚みは、ｎ型カラム５４およびｐ型カラム５６の超接合構造とＦＳ層７２との深さ方向における距離である。深さ方向とは、ｚ方向と平行な方向であればよく、超接合構造からＦＳ層７２への方向でもよく、ＦＳ層７２から超接合構造への方向でもよい。ｎ型層７０の厚みは、基板の厚みに依らずに一定の厚みとしてよい。例えば、ｎ型層７０の厚みは２０μｍ以下である。具体的には、ｎ型層７０の厚みは、２０、１５、１０、９、５、‥３または１μｍとしてよい。本例では、ｎ型層７０の厚みは３～５μｍである。
　なお、本例のＦＳ層７２を形成するための不純物として、リン（Ｐ）を用いることはできない。リンは裏面側からドープしても表面側まで深くドープできない。例えば、せいぜい裏面側から１．５μｍまでしかドープすることができない。また、リンは熱処理によっても裏面側から表面側に深くドライブインさせることができない。それゆえ、リンを用いる場合には、ｎ型層７０の厚みが２０μｍよりも大きくなり、相対的にＦＳ層７２の厚みが小さくなる。一方、ＦＳ層７２はｎ型層７０よりも不純物濃度が高いことにより空乏層の拡がりを抑えることができるので、ＦＳ層７２の機能を発揮させるためには可能な限りｎ型層７０に近い位置にまでＦＳ層７２の不純物をドープする方がよい。したがって、ＦＳ層７２の不純物としては、リンではなく前述のセレンまたはプロトンを用いるのが好適である。
　本例において、ＦＳ層７２およびドレイン層８２を合わせた厚みは約２５μｍである。ただし、半導体基板１００の厚みに応じて、ＦＳ層７２およびドレイン層８２を合わせた厚みは適宜調節してよい。ドレイン層８２は、ＦＳ層７２に対してさらにｎ型不純物をドープすることにより形成する。
　ＩＧＢＴ部２０のＢ１からＢ２にかけて順に、コンタクト領域４４（ｐ＋＋型）、ｐ型ベース層４２（ｐ－型）、ｎ型ベース層４０（ｎ－型）、ｎ型層７０（ｎ－型）、ＦＳ層７２（ｎ－型）、コレクタ層８０（ｐ＋型）が設けられる。Ｂ１‐Ｂ２では、ｎ型カラム５４に代えてｎ型ベース層４０を有する点、および、ドレイン層８２に代えてコレクタ層８０を有する点において、Ａ１‐Ａ２と異なる。他の点は、Ａ１‐Ａ２と同じである。ｎ型ベース層４０は、ｎ型カラム５４と同じｎ－型である。本例では、ｎ型ベース層４０の不純物濃度は、ｎ型層７０の不純物濃度と同じ合ってよい。
　図４は、（ａ）ＳＪ‐ＭＯＳＦＥＴ部１０のＡ１‐Ａ２における不純物濃度、および、（ｂ）ＩＧＢＴ部２０のＢ１‐Ｂ２における不純物濃度の他の例を示す図である。本例では、ＦＳ層７２がプロトンを不純物として有する点で、図３の例とは異なる。他の点は、図３の例と同じである。
　ＦＳ層７２は表面側から裏面側に向かって複数のピークを有する様に形成する。ただし、裏面側から表面側に向かって徐々にピーク値が小さくなるように形成する。本例では、ＦＳ層７２における不純物濃度分布は、半導体基板１００の最も裏面側に最大ピークを有する。これにより、ＦＳ層７２は逆電圧印加時に十分なキャリアを供給できるともに、ｎ型層７０の近傍ではキャリア量を抑えることができる。なお本例では、３つの異なるｚ座標位置に不純物濃度のピークを有するが、ピークの数は３に限定されず、４以上としてもよい。
　複数回に分けて、加速電圧およびドープ量を調節することにより、複数のプロトンの不純物濃度ピークを有するＦＳ層７２を形成することができる。例えば、裏面側からドープする場合に、加速電圧をより高くすることによって、より表面側にプロトンをドープすることができる。例えば、加速電圧を１．０ＭｅＶとすると加速電圧を０．５ＭｅＶとする場合よりも表面側にプロトンをドープすることができる。本例における複数のピークを実現するべく、加速電圧は１．４５ＭｅＶから０．４ＭｅＶの範囲で適宜選択してよく、不純物のドープ量は１Ｅ＋１２ｃｍ－２から３Ｅ＋１４ｃｍ－２の範囲で適宜選択してよい。
　図５および図６により、半導体装置２００のＳＪ‐ＭＯＳＦＥＴ部１０、境界部１２およびＩＧＢＴ部２０の製造方法を断面により説明する。図５は、（ａ）エピタキシャル層１２０の形成工程、（ｂ）不純物をドープしたエピタキシャル層１２２を多段形成する工程、ならびに、（ｃ）エピタキシャル層１２４を形成する工程を示す図である。
　（図５（ａ）エピタキシャル層１２０の形成工程）まず、半導体基板１１０の表面側に接してエピタキシャル層１２０を形成する。本例において、半導体基板１１０およびエピタキシャル層１２０は共にｎ－型である。
　（図５（ｂ）不純物をドープしたエピタキシャル層１２２を多段形成する工程）次に、エピタキシャル層１２０の表面側から、ｐ型不純物およびｎ型不純物をそれぞれ異なる場所に局所的にドープする。ｐ型不純物はボロン（Ｂ）であってよく、ｎ型不純物はリン（Ｐ）であってよい。
　その後、エピタキシャル層１２０の表面側にエピタキシャル層１２２を形成する。本例において、エピタキシャル層１２２は、エピタキシャル層１２０と同様にｎ－型である。エピタキシャル層１２２の形成後に、エピタキシャル層１２２の表面側から、ｐ型不純物およびｎ型不純物をそれぞれ異なる場所に局所的にドープする。このとき、エピタキシャル層１２０およびエピタキシャル層１２２において、ｎ型不純物およびｐ型不純物をそれぞれドープする位置のｘおよびｙ座標は略一致させる。なおここで、ドープする位置のｘ座標およびｙ座標を略一致させるとは、不純物のドーピングに用いるマスク位置合わせ精度の誤差の範囲内であることを意味してよい。
　（図５（ｃ）エピタキシャル層１２４を形成する工程）その後、エピタキシャル層１２２の形成ならびにｐ型不純物およびｎ型不純物の局所的ドープを複数回繰り返す。その後、熱処理をすることにより、ｎ型ベース層４０、ｎ型カラム５４およびｐ型カラム５６を有するエピタキシャル層１２４を形成する。これにより、半導体基板１１０にｎ型カラム５４およびｐ型カラム５６を有する超接合構造を形成する。
　図６は、（ｄ）表面構造形成工程および裏面構研磨工程、（ｅ）ＦＳ層７２の形成工程、ならびに、（ｆ）裏面構造形成工程を示す図である。図５の（ｃ）の工程の次が、図６の（ｄ）の工程である。
　（図６（ｄ）表面構造形成工程および裏面研磨工程）まず、表面側（＋ｚ側）および／または裏面側（－ｚ側）からライフタイムキラーを導入して欠陥領域５８を形成する。その後、ゲート電極５０、ゲート絶縁膜５２、ｐ型ベース層４２、コンタクト領域４４、ソース領域４５、エミッタ領域４６、絶縁層６０および表面電極６２を含む表面構造を形成する。次に、半導体基板１１０の裏面側（－ｚ側）を研磨する。なお、半導体基板１１０は当初の厚みの全てを研磨により除去しなくてもよい。つまり、研磨後において半導体基板１１０はその厚みを残してよい。なお、裏面研磨に起因する半導体基板１００の厚みバラつきは、３～５μｍである。
　なお、ＳＪ‐ＭＯＳＦＥＴ部１０を有するＳＪ‐ＭＯＳＦＥＴデバイスを形成する場合、上述の裏面研磨は行われない。ＳＪ‐ＭＯＳＦＥＴデバイスは、ＩＧＢＴデバイスのように半導体基板の厚みにより耐圧を調整するデバイスではないからである。ＳＪ‐ＭＯＳＦＥＴ部１０を有する半導体装置２００を形成する場合に研磨工程を有することは、本明細書における特徴の１つである。
（図６（ｅ）ＦＳ層７２の形成工程）次に、半導体基板１１０の裏面側において、ｎ型カラム５４およびｐ型カラム５６の超接合構造およびｎ型ベース層４０と重なる位置であり、且つ、超接合構造の裏面側端部と接しないように、ＦＳ層７２を形成する。上述の様に、ＦＳ層７２はセレンをドープすることにより、または、プロトンを複数回ドープすることにより形成してよい。
　（図６（ｆ）裏面構造形成工程）次に、ＩＧＢＴ部２０の裏面側からＦＳ層７２にｐ型不純物をカウンタードープすることによりコレクタ層８０を形成する。なお、コレクタ層８０は、境界部１２の裏面側にも設けてよい。また、ＳＪ‐ＭＯＳＦＥＴ部１０の裏面側からＦＳ層７２にｎ型不純物をさらにドープすることによりドレイン層８２を形成する。最後に、裏面電極９０をコレクタ層８０およびドレイン層８２の裏面側に形成する。裏面電極９０は、スパッタリング法により形成されたアルミニウム層であってよい。
　図７は、ＳＪ‐ＭＯＳＦＥＴ部１０の変形例である半導体装置２１０の断面図である。本例では、半導体基板１００は、ＦＳ層７２とドレイン層８２との間に、フローティング領域８４を有する。当該フローティング領域８４は、ＦＳ層７２（ｎ＋型）およびドレイン層８２（ｎ＋型）とは異なる極性であるｐ型不純物を有する。その他の点は、図１の例と同じである。
　ｐ型のフローティング領域８４を裏面電極９０とコンタクトさせるとオン電圧が上昇する。それゆえ、ｐ型のフローティング領域８４は、裏面電極９０とコンタクトさせない。なお、ｐ型のフローティング領域８４を裏面電極９０とコンタクトさせなければ、ｐ型のフローティング領域８４をドレイン層８２中にのみ設けてもよい。ｐ型のフローティング領域８４をＦＳ層７２とドレイン層８２との間に設けることにより、逆回復時に高電圧が加わるとｐ型のフローティング領域８４とドレイン層８２で構成されるダイオードがアバランシェ降伏してホールが注入される。それゆえ、逆電圧印加時におけるＩＧＢＴ部２０のソフトリカバリー特性をさらに向上させることができる。
　以上、本発明を実施の形態を用いて説明したが、本発明の技術的範囲は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変更又は改良を加えることが可能であることが当業者に明らかである。その様な変更又は改良を加えた形態も本発明の技術的範囲に含まれ得ることが、請求の範囲の記載から明らかである。
　請求の範囲、明細書、および図面中において示した装置、システム、プログラム、および方法における動作、手順、ステップ、および段階等の各処理の実行順序は、特段「より前に」、「先立って」等と明示しておらず、また、前の処理の出力を後の処理で用いるのでない限り、任意の順序で実現しうることに留意すべきである。請求の範囲、明細書、および図面中の動作フローに関して、便宜上「まず、」、「次に、」等を用いて説明したとしても、この順序で実施することが必須であることを意味するものではない。
１０　ＳＪ‐ＭＯＳＦＥＴ部、１１　ＳＪ‐ＭＯＳＦＥＴ素子、１２　境界部、１４　超接合型トランジスタ領域、２０　ＩＧＢＴ部、２１　ＩＧＢＴ素子、２４　ＩＧＢＴ領域、３０　耐圧構造部、３２　第１耐圧部、３４　第２耐圧部、４０　ｎ型ベース層、４２　ｐ型ベース層、４４　コンタクト領域、４５　ソース領域、４６　エミッタ領域、４７　ガードリング、４８　ｎ型領域、４９　ｐ型領域、５０　ゲート電極、５２　ゲート絶縁膜、５４　ｎ型カラム、５６　ｐ型カラム、５８　欠陥領域、６０　絶縁層、６２　表面電極、６４　フィールドプレート、７０　ｎ型層、７２　ＦＳ層、８０　コレクタ層、８２　ドレイン層、８４　フローティング領域、９０　裏面電極、１００　半導体基板、１１０　半導体基板、１２０　エピタキシャル層、１２２　エピタキシャル層、１２４　エピタキシャル層、２００　半導体装置、２１０　半導体装置

Claims (10)

  1. 　半導体基板と、
    　前記半導体基板の表面側に形成された超接合構造と、
    　前記半導体基板の裏面側において前記超接合構造と重なる位置に形成され、且つ、前記超接合構造の裏面側端部と接しないように形成されたフィールドストップ層と
    　を備える半導体装置。
  2. 　前記フィールドストップ層における不純物濃度分布は、前記半導体基板の最も裏面側に最大ピークを有する
    　請求項１に記載の半導体装置。
  3. 　前記フィールドストップ層は、プロトンを不純物として有する
    　請求項１または２に記載の半導体装置。
  4. 　前記フィールドストップ層における不純物濃度分布は、前記半導体基板の裏面側から前記半導体基板の表面側に向けて徐々に減少する
    　請求項１に記載の半導体装置。
  5. 　前記フィールドストップ層は、セレンを不純物として有する
    　請求項１または４に記載の半導体装置。
  6. 　前記超接合構造と前記フィールドストップ層との深さ方向における距離が２０μｍ以下である
    　請求項１から５のいずれか一項に記載の半導体装置。
  7. 　前記半導体基板に形成され、前記超接合構造と、前記フィールドストップ層の一部とを含む超接合型トランジスタ素子と、
    　前記半導体基板に形成され、前記フィールドストップ層の一部を含むＩＧＢＴ素子と
    　を有する
    　請求項１から６のいずれか一項に記載の半導体装置。
  8. 　前記半導体基板は、前記フィールドストップ層よりも裏面側にドレイン層を有し、
    　前記半導体基板は、前記フィールドストップ層と前記ドレイン層との間に、前記フィールドストップ層および前記ドレイン層とは異なる極性を有するフローティング領域を有する
    　請求項１から７のいずれか一項に記載の半導体装置。
  9. 　半導体基板に超接合構造を形成する工程と、
    　前記半導体基板の裏面側において前記超接合構造と重なる位置であり、且つ、前記超接合構造の裏面側端部と接しないように、フィールドストップ層を形成する工程と
    　を備える半導体装置の製造方法。
  10. 　前記超接合構造を形成する工程の後に、前記半導体基板の裏面側を研磨する工程をさらに備える
    　請求項９に記載の半導体装置の製造方法。
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