JP7285277B2 - BiMOS半導体装置 - Google Patents
BiMOS半導体装置 Download PDFInfo
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- JP7285277B2 JP7285277B2 JP2021062237A JP2021062237A JP7285277B2 JP 7285277 B2 JP7285277 B2 JP 7285277B2 JP 2021062237 A JP2021062237 A JP 2021062237A JP 2021062237 A JP2021062237 A JP 2021062237A JP 7285277 B2 JP7285277 B2 JP 7285277B2
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 239000002131 composite material Substances 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000005036 potential barrier Methods 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000013598 vector Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Description
NA<ND
を満たす。これにより、n-ドリフト層33aとpピラー層33bとの界面における電位障壁が低くなるため、n-ドリフト層33aからpピラー層33bに、電子電流が流れやすくなる。
WD<WA
を満たす。ここで、耐電圧の観点から、WAを適宜調整することができる。
ND<NA
を満たす。これにより、p-ドリフト層63aとnピラー層63bとの界面における電位障壁が低くなるため、p-ドリフト層63aからnピラー層63bに、ホール電流が流れやすくなる。
WA<WD
を満たす。ここで、耐電圧の観点から、WDを適宜調整することができる。
10A IGBT
11 コレクタ/ドレイン電極(コレクタ電極)
12 n+ドレイン層(n+コレクタ層)
12A p+コレクタ層
13 n-ドリフト層
14 複合層
14a pベース層(pエミッタ層)
14b n+ソース層(n+エミッタ層)
14c 反転層
15 トレンチ
16 ゲート絶縁膜
17 ゲート電極
18 エミッタ/ソース電極
18A エミッタ電極
19 ベース電極
21a、21b、21c、21d 電子電流
22 ホール電流
30 BiMOS半導体装置
31 コレクタ/ドレイン電極
32 n+ドレイン層
33 並列pn層
33a n-ドリフト層
33b pピラー層
34 複合層
34a pベース層
34b n+ソース層
34c 反転層
35 トレンチ
36 ゲート絶縁膜
37 ゲート電極
38 エミッタ/ソース電極
39 ベース電極
41a、41c、41d、41f 電子電流
42 ホール電流
51、52 高抵抗層
60 BiMOS半導体装置
61 コレクタ/ドレイン電極
62 p+ドレイン層
63 並列pn層
63a p-ドリフト層
63b nピラー層
64 複合層
64a nベース層
64b p+ソース層
64c 反転層
65 トレンチ
66 ゲート絶縁膜
67 ゲート電極
68 エミッタ/ソース電極
69 ベース電極
71a、71c、71d、71f ホール電流
72 電子電流
81、82 高抵抗層
Claims (2)
- トレンチゲート構造を有するnチャネル型のBiMOS半導体装置であって、
コレクタ/ドレイン電極と、n+ドレイン層と、n-ドリフト層およびpピラー層が交互に接合されている並列pn層と、pベース層およびn+ソース層からなる複合層とが、この順で形成されており、
前記複合層の表面から前記並列pn層の上部にかけて、トレンチが形成されており、
前記トレンチの内部に、ゲート絶縁膜を介して、ゲート電極が形成されており、
前記n + ソース層は、前記複合層の上部かつ前記トレンチの側部に形成されているとともに、前記n - ドリフト層の上に形成されており、
前記n + ソース層と接合するように、エミッタ/ソース電極が形成されており、
前記pベース層と接合するように、前記エミッタ/ソース電極と所定の間隔を隔てて、ベース電極が形成されており、
前記pピラー層の上に形成されている前記pベース層と、前記n+ソース層との間の一部に、高抵抗層が形成されており、
前記pピラー層と、前記pベース層との間に、高抵抗層が形成されており、
前記pピラー層は、前記n-ドリフト層よりも不純物濃度が低く、前記n - ドリフト層よりも幅が広い、BiMOS半導体装置。 - トレンチゲート構造を有するpチャネル型のBiMOS半導体装置であって、
コレクタ/ドレイン電極と、p+ドレイン層と、p-ドリフト層およびnピラー層が交互に接合されている並列pn層と、nベース層およびp+ソース層からなる複合層とが、この順で形成されており、
前記複合層の表面から前記並列pn層の上部にかけて、トレンチが形成されており、
前記トレンチの内部に、ゲート絶縁膜を介して、ゲート電極が形成されており、
前記p + ソース層は、前記複合層の上部かつ前記トレンチの側部に形成されているとともに、前記p - ドリフト層の上に形成されており、
前記p + ソース層と接合するように、エミッタ/ソース電極が形成されており、
前記nベース層と接合するように、前記エミッタ/ソース電極と所定の間隔を隔てて、ベース電極が形成されており、
前記nピラー層の上に形成されている前記nベース層と、前記p+ソース層との間の一部に、高抵抗層が形成されており、
前記nピラー層と、前記nベース層との間に、高抵抗層が形成されており、
前記nピラー層は、前記p-ドリフト層よりも不純物濃度が低く、前記p - ドリフト層よりも幅が広い、BiMOS半導体装置。
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CN202210113729.4A CN115148805A (zh) | 2021-03-31 | 2022-01-30 | BiMOS半导体装置 |
US17/670,534 US11776953B2 (en) | 2021-03-31 | 2022-02-14 | BiMOS semiconductor device |
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Citations (3)
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JP2015039010A (ja) | 2009-08-27 | 2015-02-26 | ビシェイ−シリコニクス | スーパージャンクショントレンチパワーmosfetデバイス及びその製造方法 |
WO2019069416A1 (ja) | 2017-10-05 | 2019-04-11 | 三菱電機株式会社 | 半導体装置 |
JP2020077800A (ja) | 2018-11-08 | 2020-05-21 | 富士電機株式会社 | 半導体装置 |
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JPS60196974A (ja) | 1984-03-19 | 1985-10-05 | Toshiba Corp | 導電変調型mosfet |
JPS61180472A (ja) | 1985-02-05 | 1986-08-13 | Mitsubishi Electric Corp | 半導体装置 |
JPS61225854A (ja) | 1985-03-29 | 1986-10-07 | Mitsubishi Electric Corp | 半導体装置 |
US20070181927A1 (en) * | 2006-02-03 | 2007-08-09 | Yedinak Joseph A | Charge balance insulated gate bipolar transistor |
WO2016063683A1 (ja) * | 2014-10-24 | 2016-04-28 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
DE102016101647A1 (de) * | 2016-01-29 | 2017-08-17 | Infineon Technologies Austria Ag | Halbleitervorrichtung mit superjunction-struktur und transistorzellen in einem übergangsbereich entlang einem transistorzellenbereich |
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JP2015039010A (ja) | 2009-08-27 | 2015-02-26 | ビシェイ−シリコニクス | スーパージャンクショントレンチパワーmosfetデバイス及びその製造方法 |
WO2019069416A1 (ja) | 2017-10-05 | 2019-04-11 | 三菱電機株式会社 | 半導体装置 |
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