JP6197966B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 138
- 238000004519 manufacturing process Methods 0.000 title claims description 19
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- 238000000034 method Methods 0.000 claims description 17
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- 238000005468 ion implantation Methods 0.000 description 4
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
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Description
[先行技術文献]
[特許文献]
特許文献1 特開2007−324539号公報
特許文献2 特開2011−243946号公報
Claims (15)
- 半導体基板の表面側に形成されたメサ部と、
前記半導体基板の表面側に形成されたフローティング部と、
前記フローティング部を囲んで形成され、前記メサ部と前記フローティング部とを分離するトレンチと、
前記トレンチ内に形成された電極と、
前記トレンチが囲む領域の外側において、前記メサ部と前記フローティング部の配列方向に沿って形成された外側配線部と
を備え、
前記外側配線部の前記メサ部および前記フローティング部側の端辺は、
前記フローティング部に対向する領域の少なくとも一部に形成され、前記トレンチを越えて前記フローティング部側に突出する突出部と、
前記メサ部に対向する領域の少なくとも一部に形成され、前記突出部よりも前記外側配線部側に凹んでいる凹部と
を有する半導体装置。 - 前記半導体基板は第1の導電型を有し、
前記半導体装置は、前記半導体基板の端部と、前記メサ部および前記フローティング部との間に形成された第2の導電型のウェル領域を更に備える
請求項1に記載の半導体装置。 - 前記メサ部は、第2の導電型のベース領域を有し、
前記ベース領域および前記ウェル領域が接続されている
請求項2に記載の半導体装置。 - 前記凹部は、前記ベース領域が前記ウェル領域に接続できる位置まで、前記外側配線部側に凹んでいる
請求項3に記載の半導体装置。 - 前記凹部の先端は、前記ウェル領域の端部から前記メサ部の内部に向かって、前記ベース領域の深さの0.75倍だけ突出した位置よりも、前記外側配線部側に配置される
請求項3または4に記載の半導体装置。 - 前記凹部の先端は、前記トレンチよりも前記外側配線部側に配置される
請求項2から4のいずれか一項に記載の半導体装置。 - 前記フローティング部は、第2の導電型を有し、
前記突出部に覆われた前記フローティング部における前記第2の導電型の領域は、前記トレンチと接続されている
請求項2から4のいずれか一項に記載の半導体装置。 - 前記突出部は、前記フローティング部の前記第2の導電型の領域が、前記突出部の下側において前記トレンチと接続できる長さを有する
請求項7に記載の半導体装置。 - 前記突出部のうち、前記フローティング部と重なる領域の長さは、前記フローティング部の深さの0.75倍以下である
請求項8に記載の半導体装置。 - 前記突出部の幅は、前記フローティング部の幅よりも小さい
請求項1から4のいずれか一項に記載の半導体装置。 - 前記凹部の幅は、前記メサ部の幅よりも大きい
請求項1から4のいずれか一項に記載の半導体装置。 - 半導体装置の製造方法であって、
半導体基板の表面側において予め定められた領域を囲むトレンチを形成して、前記トレンチに囲まれたフローティング部と、前記フローティング部から分離されたメサ部とを形成する段階と、
前記トレンチ内に電極を形成し、且つ、前記トレンチが囲む領域の外側において、前記メサ部と前記フローティング部の配列方向に沿った外側配線部を形成する段階と、
前記外側配線部をマスクとして前記メサ部および前記フローティング部に予め定められた導電型の不純物をドープして拡散させる段階と
を備え、
前記外側配線部を形成する段階において、前記外側配線部の前記メサ部および前記フローティング部側の端辺に、
前記フローティング部に対向する領域の少なくとも一部に配置され、前記トレンチを越えて前記フローティング部側に突出する突出部を形成し、
前記メサ部に対向する領域の少なくとも一部に配置され、前記突出部よりも前記外側配線部側に凹んでいる凹部を形成する
半導体装置の製造方法。 - 前記半導体基板は第1の導電型を有し、
前記トレンチを形成する段階の前に、前記半導体基板の端部と、前記メサ部および前記フローティング部との間に第2の導電型のウェル領域を形成する段階を更に備える
請求項12に記載の半導体装置の製造方法。 - 前記不純物をドープして拡散させる段階において、第2の導電型の不純物をドープして拡散させて、前記メサ部に、前記ウェル領域と接続されたベース領域を形成する
請求項13に記載の半導体装置の製造方法。 - 前記不純物をドープして拡散させる段階において、第2の導電型の不純物をドープして拡散させて、前記突出部に覆われた前記フローティング部における第2の導電型の領域を、前記トレンチと接続させる
請求項13または14に記載の半導体装置の製造方法。
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DE112015002120T5 (de) | 2017-02-23 |
US10109726B2 (en) | 2018-10-23 |
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