JP6365165B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 141
- 238000004519 manufacturing process Methods 0.000 title claims description 51
- 238000005468 ion implantation Methods 0.000 claims description 97
- 239000000758 substrate Substances 0.000 claims description 57
- 239000012535 impurity Substances 0.000 claims description 40
- 238000002513 implantation Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 19
- 239000002344 surface layer Substances 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 23
- 230000015572 biosynthetic process Effects 0.000 description 12
- 229910052785 arsenic Inorganic materials 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 4
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
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- 238000007429 general method Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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Description
実施の形態1にかかる半導体装置の製造方法について、一般的なMOSゲート(金属−酸化膜−半導体からなる絶縁ゲート)構造を備えたトレンチゲート構造の縦型IGBTを例に説明する。図1,3,4,6〜8は、実施の形態1にかかる半導体装置の製造途中の状態を示す断面図である。図2,5は、実施の形態1にかかる半導体装置の製造途中の状態を示す平面図である。図2,5には、それぞれn+型エミッタ領域(第2半導体領域)6およびp+型コンタクト領域(第3半導体領域)7をそれぞれ形成するための第1,2レジストマスク11,15の平面パターンを示す。図3,4には、図2の切断線A−A’における断面構造を示す。図6には、図5の切断線B−B’における断面構造を示す。
次に、実施の形態2にかかる半導体装置の製造方法について説明する。図9,11,12,14〜16は、実施の形態2にかかる半導体装置の製造途中の状態を示す断面図である。図10,13は、実施の形態2にかかる半導体装置の製造途中の状態を示す平面図である。図10,13には、それぞれn+型エミッタ領域26およびp+型コンタクト領域27をそれぞれ形成するための第1,2レジストマスク31,35の平面パターンを示す。図11,12には、図10の切断線C−C’における断面構造を示す。図14には、図13の切断線D−D’における断面構造を示す。
2 p型ベース領域
3 トレンチ
4 ゲート絶縁膜
5 ゲート電極
6 n+型エミッタ領域
7 p+型コンタクト領域
8 層間絶縁膜
9 エミッタ電極
11 第1レジストマスク
12 第1レジストマスクの開口部
13 第1イオン注入(垂直イオン注入)
14 第1イオン注入(斜めイオン注入)
15 第2レジストマスク
16 第2レジストマスクの開口部
17 第2イオン注入
w1 n+型エミッタ領域のトレンチ短手方向の幅
w2 第1レジストマスクの開口部のトレンチ短手方向の幅
θ 斜めイオン注入の注入角度
Claims (6)
- 第1導電型の半導体基板のおもて面の表面層に第2導電型の第1半導体領域を形成する第1工程と、
深さ方向に前記第1半導体領域を貫通するトレンチを所定の間隔で複数形成する第2工程と、
前記トレンチの内部にゲート絶縁膜を介してゲート電極を形成する第3工程と、
前記半導体基板のおもて面に、前記第1半導体領域の、少なくとも前記トレンチ側の部分を選択的に露出した第1マスク膜を形成する第4工程と、
前記第1マスク膜をマスクとして第1導電型不純物を第1イオン注入し、前記ゲート絶縁膜の、前記トレンチの側壁に沿った部分に接するように第1導電型の第2半導体領域を形成する第5工程と、
前記第1マスク膜を除去する第6工程と、
前記半導体基板のおもて面に、前記第1半導体領域の、前記第2半導体領域よりも前記トレンチから離れた部分を選択的に露出した第2マスク膜を形成する第7工程と、
前記第2マスク膜をマスクとして、前記半導体基板のおもて面に垂直な注入角度で第2導電型不純物を第2イオン注入し、前記第2半導体領域に接するように、前記第1半導体領域よりも不純物濃度の高い第2導電型の第3半導体領域を形成する第8工程と、
前記第2マスク膜を除去する第9工程と、
を含み、
前記第5工程では、前記第1マスク膜によって前記ゲート電極の表面を覆った状態で、前記第1イオン注入として、前記半導体基板のおもて面に垂直な方向に対して前記トレンチが複数並ぶ第1方向側に傾いた注入角度で前記第1導電型不純物の斜めイオン注入を行うことを特徴とする半導体装置の製造方法。 - 前記第5工程では、前記第1イオン注入として、前記斜めイオン注入に加えて、前記半導体基板のおもて面に垂直な注入角度で前記第1導電型不純物のイオン注入を行うことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第5工程では、前記半導体基板のおもて面に垂直な方向に対して前記第1方向側に10度以上45度以下傾いた注入角度で前記斜めイオン注入を行うことを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第5工程では、前記第1方向と直交する第2方向の幅を前記トレンチから離れた部分よりも前記トレンチ側の部分で広くしたH状の平面形状を有する前記第2半導体領域を形成することを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。
- 前記第9工程の後、熱処理により、前記第2半導体領域および前記第3半導体領域を拡散させて所定の拡散深さにする第10工程をさらに含むことを特徴とする請求項1〜4のいずれか一つに記載の半導体装置の製造方法。
- 前記第10工程の後、
前記第2半導体領域および前記第3半導体領域に接する第1電極を形成する工程と、
前記半導体基板の裏面の表面層に第2導電型の第4半導体領域を形成する工程と、
前記第4半導体領域に接する第2電極を形成する工程と、をさらに含むことを特徴とする請求項5に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014189991A JP6365165B2 (ja) | 2014-09-18 | 2014-09-18 | 半導体装置の製造方法 |
US14/844,919 US9378959B2 (en) | 2014-09-18 | 2015-09-03 | Method of manufacturing insulated gate transistor semiconductor device |
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CN106952945A (zh) * | 2017-03-24 | 2017-07-14 | 深圳深爱半导体股份有限公司 | 功率半导体器件及其制造方法 |
JP6958093B2 (ja) * | 2017-08-09 | 2021-11-02 | 富士電機株式会社 | 半導体装置 |
CN109980003B (zh) * | 2017-12-27 | 2022-02-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN108831832B (zh) * | 2018-05-07 | 2020-08-14 | 株洲中车时代电气股份有限公司 | 沟槽台阶栅igbt芯片的制作方法 |
DE102018120432B4 (de) * | 2018-08-22 | 2023-03-30 | Infineon Technologies Dresden GmbH & Co. KG | Leistungshalbleitervorrichtung mit zulässig verifizierbarem p-Kontakt und Verfahren |
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WO2022034828A1 (ja) * | 2020-08-11 | 2022-02-17 | ローム株式会社 | 半導体装置 |
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US8058685B2 (en) * | 2009-07-08 | 2011-11-15 | Force Mos Technology Co., Ltd. | Trench MOSFET structures using three masks process |
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