JP4927401B2 - 超接合半導体素子 - Google Patents
超接合半導体素子 Download PDFInfo
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- JP4927401B2 JP4927401B2 JP2005377001A JP2005377001A JP4927401B2 JP 4927401 B2 JP4927401 B2 JP 4927401B2 JP 2005377001 A JP2005377001 A JP 2005377001A JP 2005377001 A JP2005377001 A JP 2005377001A JP 4927401 B2 JP4927401 B2 JP 4927401B2
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- 239000004065 semiconductor Substances 0.000 title claims description 25
- 239000012535 impurity Substances 0.000 claims description 66
- 238000005192 partition Methods 0.000 claims description 58
- 230000015556 catabolic process Effects 0.000 claims description 41
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 description 54
- 238000004519 manufacturing process Methods 0.000 description 12
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
先ず、図3は実験に用いた縦型のnチャネル型の超接合MOSFETの基本的な部分の部分断面図である。他に、主に周縁部分に耐圧を保持するための部分が設けられるが、その部分は、例えばガードリング構造のような一般的な方法で形成される。なお以下でnまたはpを冠記した層や領域は、それぞれ電子、正孔を多数キャリアとする層、領域を意味している。また添字の+は比較的高不純物濃度の、―は比較的低不純物濃度の領域をそれぞれ意味している。
図3の超接合MOSFETの動作は、次のようにおこなわれる。ゲート電極層16に所定の正の電圧が印加されると、ゲート電極層16直下のpウェル領域13aの表面層に反転層が誘起され、n+ソース領域14から反転層を通じてnチャネル領域13dに電子が注入される。その注入された電子がnドリフト領域12aを通じてn+ドレイン層11に達し、ドレイン電極18、ソース電極17間が導通する。
p仕切り領域12bのボロンの不純物量(ドーズ量)を1×1013cm-2に固定して、これに対するnドリフト領域12aのリンの不純物量(ドーズ量)を80〜150%の範囲で変えてnチャネル型MOSFETをシミュレーションし、また実際に試作して確認した。
図6は、L負荷アバランシェ破壊電流(A)の不純物量依存性を示す特性図である。横軸は、 nドリフト領域12aのリンの不純物量(ドーズ量)、縦軸はL負荷アバランシェ破壊電流(A)である。 p仕切り領域12bのボロンの不純物量(ドーズ量)を1×1013cm-2に固定して、これに対するnドリフト領域12aのリンの不純物量(ドーズ量)を80〜150%の範囲で変えた。設定条件は実施例1と同じである。
p仕切り領域12bの不純物濃度CPを変えてnチャネル型MOSFETをシミュレーションし、また実際に試作して確認した。
次に、nドリフト領域12aの幅Lnを5μm一定とし、p仕切り領域12bの幅LPを変えてnチャネル型MOSFETをシミュレーションし、また実際に試作して確認した。
他の製造方法として、エピタキシャル成長の前に部分的に不純物の埋め込み領域を形成しておいてから、高抵抗層をエピタキシャル成長する工程を数回繰り返した後、熱処理により拡散させて並列pn層を形成することもできる。
12、22 ドリフト層
12a、22a nドリフト領域
12b、22b p仕切り領域
13a、23a pウェル領域
13b、23b p+コンタクト領域
14、24 n+ソース領域
15 ゲート絶縁膜
16 ゲート電極層
17 ソース電極
18 ドレイン電極
19 絶縁膜
Claims (7)
- 第一と第二の主面と、主面に設けられた第一と第二の主電極と、その主電極間に、オン状態では電流を流すとともにオフ状態では空乏化する第一導電型ドリフト領域と第二導電型仕切り領域とを交互に配置した並列pn層を備え、第一の主面と第二導電型仕切り領域との間に設けられた第二導電型のウェル、該ウェルの表面に選択的に設けられたソース領域、ソース領域と接するウェルの表面にゲート絶縁膜を介して設けられたゲート電極、第二の主面と並列pn層との間に設けられた第一導電型ドレイン層を備えた縦型のMIS型半導体素子において、第一導電型ドリフト領域の不純物量が第二導電型仕切り領域の不純物量の110〜150%の範囲内であり、L負荷アバランシェ破壊電流が定格電流の2倍以上であることを特徴とする超接合半導体素子。
- 前記第一導電型ドリフト領域の不純物がリンで、前記第二導電型仕切り領域の不純物がボロンであることを特徴とする請求項1に記載の超接合半導体素子。
- 前記第一導電型ドリフト領域と前記第二導電型仕切り領域とがそれぞれストライプ状であることを特徴とする請求項1または請求項2に記載の超接合半導体素子。
- 前記ウェルの幅が前記第二導電型仕切り領域の幅より大きいことを特徴とする請求項1に記載の超接合半導体素子。
- 前記ウェルと前記ソース領域とが第一の主面に設けられた第一の電極と電気的に接続されていることを特徴とする請求項1に記載の超接合半導体素子。
- 前記ウェルが前記第一の主面に設けられた第一の電極と電気的に接続される部分に高濃度の第二導電型のコンタクト領域を設けたことを特徴とする請求項5に記載の超接合半導体素子。
- 前記ウェルと前記第一の主面に設けられた第一の電極との電気的接続が少なくとも2箇所あり、該2箇所の間のゲート電極の上に絶縁膜を介して前記第一の電極が配置されていることを特徴とする請求項5または請求項6に記載の超接合半導体素子。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005377001A JP4927401B2 (ja) | 1998-11-12 | 2005-12-28 | 超接合半導体素子 |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1998321567 | 1998-11-12 | ||
JP32156798 | 1998-11-12 | ||
JP22186199 | 1999-08-05 | ||
JP1999221861 | 1999-08-05 | ||
JP2005377001A JP4927401B2 (ja) | 1998-11-12 | 2005-12-28 | 超接合半導体素子 |
Related Parent Applications (1)
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JP23728699A Division JP3799888B2 (ja) | 1998-11-12 | 1999-08-24 | 超接合半導体素子およびその製造方法 |
Publications (2)
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JP2006100862A JP2006100862A (ja) | 2006-04-13 |
JP4927401B2 true JP4927401B2 (ja) | 2012-05-09 |
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JP2005377001A Expired - Lifetime JP4927401B2 (ja) | 1998-11-12 | 2005-12-28 | 超接合半導体素子 |
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Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5985789B2 (ja) * | 2010-03-15 | 2016-09-06 | 富士電機株式会社 | 超接合半導体装置の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH09266311A (ja) * | 1996-01-22 | 1997-10-07 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
JP3938964B2 (ja) * | 1997-02-10 | 2007-06-27 | 三菱電機株式会社 | 高耐圧半導体装置およびその製造方法 |
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