CN108091567B - 半超结fs iegt结构及其制造方法 - Google Patents

半超结fs iegt结构及其制造方法 Download PDF

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CN108091567B
CN108091567B CN201711328973.8A CN201711328973A CN108091567B CN 108091567 B CN108091567 B CN 108091567B CN 201711328973 A CN201711328973 A CN 201711328973A CN 108091567 B CN108091567 B CN 108091567B
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iegt
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CN108091567A (zh
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周宏伟
闫宏丽
刘鹏飞
杜忠鹏
徐西昌
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Longteng Semiconductor Co ltd
Xi'an Longxiang Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side

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Abstract

本发明涉及半超结FS IEGT结构及其制造方法，器件原胞设计采用半超结FS IEGT结构，可以更好的折衷动静态参数，提高器件的综合性能。本发明的IEGT结构采用Dummy沟槽的结构，Dummy沟槽没有连接到发射极，降低了沟道密度，可以提高器件短路能力；同时，Dummy沟槽区没有空穴通道，使空穴在此区域积累，产生IE效应，电导调制效应增强，导通压降降低；且由于集电极侧的空穴注入并没有增强，故关断时间不会明显增大；本发明的IEGT结构，可以实现低的导通压降和开关损耗，且具有较高的短路能力。

Description

半超结FS IEGT结构及其制造方法
技术领域
本发明涉及半导体功率器件技术领域，具体涉及一种半超结FS IEGT结构及其制造方法。
背景技术
绝缘栅双极晶体管（Insulate Gate Bipolar Transistor，IGBT）由于具有耐高压、低导通电阻、驱动简单以及相对较快的开关速度等特点，使其成为高压、中等开关速度应用领域功率开关器件中非常理想的选择。按照不同的器件结构，IGBT有穿通型IGBT（Punch Through IGBT）、非穿通型IGBT（Non Punch Through IGBT）和场截止型IGBT（Field-Stop IGBT，FS IGBT）。采用沟槽栅结构的FS IGBT可以更好的改善导通压降和开关损耗之间的折衷关系。沟槽栅结构由于较高的原胞密度，可以降低正向导通压降，但其短路电流大，导致短路能力较差。
IGBT可以和现有的超结工艺兼容，将超结理论应用于IGBT，可以降低漂移区厚度，从而进一步降低导通压降和开关损耗，提高器件性能。
发明内容
本发明的目的是提供一种半超结FS IEGT结构及其制造方法,更好的折衷动静态参数，提高器件的综合性能。
本发明所采用的技术方案为：
半超结FS IEGT结构的制造方法，其特征在于：
器件原胞设计采用半超结FS IEGT结构。
所述的半超结FS IEGT结构的制造方法，其特征在于：
具体包括以下步骤：
步骤一：选取 N型FZ衬底；
步骤二：沟槽刻蚀并进行P型外延层的回填，并进行CMP工艺，形成间隔的P-和N-漂移区；
步骤三：沟槽刻蚀，生长栅氧及多晶硅并回刻；
步骤四：P-body注入并推阱及N+注入并推阱；
步骤五：层间介质淀积，并光刻形成接触孔；
步骤六：正面金属淀积和光刻，形成Emitter和Gate电极；
步骤七：背面减薄，进行FS层和P+注入，并激光退火；
步骤八：背面金属淀积，形成Collector电极，形成最终器件结构。
如所述的半超结FS IEGT结构的制造方法制造的半超结FS IEGT结构。
本发明具有以下优点：
本发明的IEGT结构采用Dummy沟槽的结构，Dummy沟槽没有连接到发射极，降低了沟道密度，可以提高器件短路能力；同时，Dummy沟槽区没有空穴通道，使空穴在此区域积累，产生IE（Injection Enhancement）效应，电导调制效应增强，导通压降降低；且由于集电极侧的空穴注入并没有增强，故关断时间不会明显增大。本发明的IEGT结构，可以实现低的导通压降和开关损耗，且具有较高的短路能力。
附图说明
图1为本发明步骤一的示意图。
图2为本发明步骤二的示意图。
图3为本发明步骤三的示意图。
图4为本发明步骤四的示意图。
图5为本发明步骤五的示意图。
图6为本发明步骤六的示意图。
图7为本发明步骤七的示意图。
图8为本发明步骤八的示意图。
具体实施方式
下面结合具体实施方式对本发明进行详细的说明。
场截止型IGBT（Field-Stop IGBT，FS IGBT）能实现通态损耗与器件耐压以及通态损耗与开关损耗之间的良好折衷。电子注入增强型栅极晶体管（Injection EnhancementGate Transistor，IEGT）采用Dummy沟槽结构，产生电子注入增强效应，减小器件导通压降，且降低了沟道密度，可以提高器件短路能力。半超结IEGT将超结理论应用于IGBT芯片设计，可以减薄漂移区厚度，同时降低导通压降和开关损耗。
现有的FS IGBT或IEGT结构，是在击穿电压、导通压降、开关损耗和短路能力等部分参数得到优化，本发明涉及半超结FS IEGT结构的制造方法，半超结电子注入增强型栅极晶体管可以更好的折衷上述动静态参数，提高器件的综合性能。具体包括以下步骤：
步骤一：选取N型FZ衬底；
步骤二：沟槽刻蚀并进行P型外延层的回填，并进行CMP工艺，形成间隔的P-和N-漂移区；
步骤三：沟槽刻蚀，生长栅氧及多晶硅并回刻；
步骤四：P-body注入并推阱及N+注入并推阱；
步骤五：进行1-3μm厚度层间介质的淀积，并光刻形成接触孔；
步骤六：正面金属淀积和光刻，形成Emitter和Gate电极；
步骤七：背面减薄，进行FS层和P+注入，并激光退火；
步骤八：背面金属淀积，形成Collector电极，形成最终器件结构。
本发明的内容不限于实施例所列举，本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换，均为本发明的权利要求所涵盖。

Claims (2)

1.半超结FS IEGT结构的制造方法，其特征在于：
器件原胞设计采用半超结FS IEGT结构；
具体包括以下步骤：
步骤一：选取 N型FZ衬底；
步骤二：沟槽刻蚀并进行P型外延层的回填，并进行CMP工艺，形成间隔的P-和N-漂移区；
步骤三：沟槽刻蚀，生长栅氧及多晶硅并回刻；
步骤四：P-body注入并推阱及N+注入并推阱，两个Gate中间的P-body上无N+注入；
步骤五：层间介质淀积，并光刻形成接触孔；
步骤六：正面金属淀积和光刻，形成Emitter和Gate电极；
步骤七：背面减薄，进行FS层和P+注入，并激光退火；
步骤八：背面金属淀积，形成Collector电极，形成最终器件结构。
2.如权利要求1所述的半超结FS IEGT结构的制造方法制造的半超结FS IEGT结构。
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