WO2012124784A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2012124784A1 WO2012124784A1 PCT/JP2012/056775 JP2012056775W WO2012124784A1 WO 2012124784 A1 WO2012124784 A1 WO 2012124784A1 JP 2012056775 W JP2012056775 W JP 2012056775W WO 2012124784 A1 WO2012124784 A1 WO 2012124784A1
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Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as an insulated gate semiconductor device used in a power conversion device such as an inverter for driving a motor and a manufacturing method thereof.
- insulated gate transistors MOSFETs
- IGBT Insulated Gate Bipolar Transistors
- MOSFETs and IGBTs incorporate a parasitic structure. That is, the MOSFET is a parasitic bipolar transistor (NPN structure), and the IGBT is a parasitic thyristor (PNPN structure).
- the IGBT includes a parasitic thyristor. Therefore, when the parasitic thyristor operates, even if the injection of electrons from the inversion layer of the MOS gate is terminated by setting the gate voltage below the threshold, the n-type source layer is another path. To the p-type base layer continues to inject electrons. This phenomenon is called latch-up. When this latch-up occurs when the gate is on and turned off, controllability by the gate voltage is lost, and in the worst case, destruction occurs.
- FIG. 26 is a cross-sectional view for explaining the operation of a conventional semiconductor device. 26 shows a cross section in which only the gate structure portion of the IGBT or MOSFET is extracted and drawn, and FIG. 26A is a cross sectional view when the p-type layer is only the p-type base layer 64. FIG. (B) shows a cross section when the p-type contact layer 66 having a higher concentration than the same layer is formed on the surface of the p-type base layer 64.
- holes that have flowed into the p-type base layer 64 at the time of turn-off or in the on-state pass between the n-type source layers 65 as shown by a hole flow 17 to form an emitter electrode (not shown).
- the hole flow 17 is shown in a rectangular shape for the sake of convenience, but the actual holes flow in a curve according to the acceptor concentration distribution and electrostatic potential distribution.
- a p-type contact layer 66 having a higher concentration than the p-type base layer 64 is formed inside the p-type base layer 64.
- the size of the resistance component 16 inside the base layer 64 is reduced. For this reason, even when a large current flows, the voltage drop due to the current can be suppressed to be equal to or less than the built-in potential of the pn junction between the n-type source layer 65 and the p-type base layer 64.
- reference numeral 9 denotes an interlayer insulating film
- reference numeral 10 denotes a gate oxide film
- reference numeral 11 denotes a polysilicon electrode
- reference numeral 61 denotes an n-type drift layer.
- FIG. 25 is a cross-sectional view of a main part of a conventional semiconductor device.
- FIG. 25 shows a cross section of a planar gate IGBT in which a p-type high concentration layer is formed.
- Patent Document 1 describes a method of forming the p-type high concentration layer 28 by an ion implantation method and a heat treatment with a high acceleration voltage.
- FIG. 27 is a cross-sectional view of a main part of a conventional semiconductor device.
- FIG. 27 shows a cross section of the IGBT described above.
- a deep p-well layer 26 is provided inside the p-type base layer 64 including the p-type contact layer 66.
- this deep p-well layer 26 also has the same role as the p-type high concentration layer 28, that is, the effect of reducing the resistance component of the path through which holes flow.
- Manufacturing of IGBTs and MOSFETs requires a number of processing steps such as photolithography and etching.
- ion implantation is performed using the resist patterned by the photolithography process as a mask.
- a local pattern defect may be formed in the resist serving as a mask.
- the resist at unscheduled locations is missing, or conversely, the resist remains.
- Defects may be formed.
- the formation of the p-type contact layer 66 or the n-type source layer 65 occurs in the defective part, and the latch-up is caused by this. The possibility of destruction will increase.
- pattern defect (1) Defect caused by an unnecessary n-type source layer entering a p-type contact layer
- pattern defect (2) Defect caused by missing p-type contact layer at a place where the n-type source layer does not originally enter
- pattern defect (3) A defect due to the simultaneous occurrence of pattern defects (1) and (2) (hereinafter referred to as pattern defect (3)).
- FIG. 28 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
- FIG. 28 shows a cross section of the element in each step during the formation of the element.
- FIG. 28A shows a state in which the gate oxide film 10, the gate control polysilicon electrode 11, and the p-type base layer 64 are formed on the surface of the n-type drift layer 61.
- a screen thermal oxide film (not shown) having the same thickness as the gate oxide film 10 may be formed on the surface of the p-type base layer 64.
- arsenic ion implantation (see arrow 19 in FIG. 28A) is performed using the polysilicon electrode 11 and the resist 8 patterned by the photolithography process as a mask.
- the resist 8 is not formed on the p-type base layer 64 on the left side of FIG. 28A due to particles or the like.
- the resist 8 is patterned again as shown in FIG. 28B, and boron ion implantation is performed using the resist 8 as a mask (see arrow 18 in FIG. 28B). Further, after the resist 8 is removed, heat treatment is performed. As a result, the p-type contact layer 66 is formed as shown in FIG.
- the n-type source layer 65 is formed on the entire surface of the portion opened by the polysilicon electrode 11 on the left p-type base layer 64, and more than the n-type source layer 65.
- a p-type contact layer 66 is formed deep. Therefore, as shown in FIG. 28C, the n-type source layer 65 slightly remains on the p-type base layer 64.
- the n-type source layer 65 is formed at a place (part) that is not originally formed, a defect occurs in characteristics.
- FIG. 31 is a cross-sectional view for explaining the operation of a conventional semiconductor device.
- FIG. 31 shows the flow of holes and the resistance component of the p-type base layer in an on state or turn-off in a conventional semiconductor device.
- FIG. 31A shows the operation of the semiconductor device in the case of the pattern defect (1) described here.
- a p-type contact layer 66 is formed on the surface of the p-type base layer 64.
- the hole flow 17 in the on state or turn-off passes through a region where the resistance component 16 has a small resistance.
- the hole flow 17 is It is blocked by the n-type source layer 65 and cannot flow out to the emitter electrode (not shown). If holes cannot flow out to the emitter electrode, the voltage applied to the pn junction composed of the p-type contact layer 66 and the n-type source layer 65 exceeds the built-in potential (about 0.7 V) in the on state or turn-off. Apart from the MOS gate, electrons are injected from the n-type source layer 65 into the p-type base layer 64 via the p-type contact layer 66. As a result, the parasitic thyristor or the parasitic bipolar transistor operates, latch-up occurs, and the MOS gate can no longer control the on / off of the current.
- FIG. 29 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
- FIG. 29 shows a cross section of the element in each step during the formation of the element.
- FIG. 29A shows a state in which the gate oxide film 10, the gate control polysilicon electrode 11, and the p-type base layer 64 are formed on the surface of the n-type drift layer 61.
- arsenic ion implantation (see arrow 19 in FIG. 29A) is performed using the polysilicon electrode 11 and the resist 8 patterned by the photolithography process as a mask.
- the resist 8 is patterned again as shown in FIG. 29B, and boron ion implantation (see arrow 18 in FIG. 29B) is performed using the resist 8 as a mask. .
- the resist 8 is not exposed due to particles or the like existing on the surface of the p-type base layer 64 on the left side of the paper in FIG. 29B, and the resist 8 remains after development. Then, boron is not introduced into the left p-type base layer 64, and the p-type contact layer 66 (but before heat treatment) is not formed.
- the resist 8 is removed and then heat treatment is performed. As a result, a final p-type contact layer 66 is formed on the p-type base layer 64 shown on the right side of FIG. 29C. On the other hand, the p-type contact layer 66 is not formed on the p-type base layer 64 shown on the left side of FIG. 29C.
- FIG. 31B shows the operation of the semiconductor device in the case of the pattern defect (2) described here.
- FIG. 30 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
- the cross section of the element in each process during the formation of the element is shown.
- the pattern defect (1) and the pattern defect (2) occur simultaneously, in the p-type base layer 64 on the left side of FIG.
- an extra n-type source layer 65 that should not be formed is formed.
- the resist 8 remains, so that the p-type contact layer 66 to be originally introduced is missing.
- the p-type contact layer to be originally formed on the p-type base layer 64 here, the p-type base layer 64 on the left side of the paper.
- 66 is not formed, and an extra n-type source layer 65 is introduced over the entire opening of the polysilicon electrode 11.
- the pattern defect (3) occurs, the p-type contact layer 66 that should be originally formed is not formed, and an extra n-type source layer 65 is introduced over the entire opening of the polysilicon electrode 11, FIG. As shown in (), all the holes flow into the n-type source layer 65 as in the case of the pattern defect (1), and latch-up is more likely to occur.
- This pattern defect (3) is a defect that can occur, although the probability is smaller than in the cases (1) and (2) described above.
- the diffusion depth of the p-well layer 26 is formed deeper than the p-type base layer 64.
- the laterally diffused portion of the p-well layer 26 at this depth must not reach the channel formation region, so that the p-well layer 26 does not affect the gate threshold.
- the manufacturing process of the p-well layer 26 needs to be processed before the gate oxide film 10 and the polysilicon electrode 11 or the p-type base layer 64 to increase the diffusion depth.
- the p-type base layer is formed on the surface layer of the n-type drift layer 61. Boron had to be implanted into a region extremely narrower than the region where 64 is formed, which was difficult. Therefore, in the p-well layer 26 formed in such a thin region, there is a problem that it is difficult to secure a region capable of offsetting the n source layer in the pattern defect (1).
- the present invention has been made in view of the above-described problems, and provides an insulated gate semiconductor device such as an IGBT or a MOSFET in which switching breakdown caused by a process defect is reduced and a method for manufacturing the same. Objective.
- the present invention selectively forms a drift layer made of a semiconductor substrate of a first conductivity type and a surface of a first main surface of the semiconductor substrate.
- a second conductive type base layer formed, a first conductive type source layer selectively formed on a surface of the base layer, and the first main surface side of the base layer in contact with the source layer
- a second conductivity type contact layer having a higher concentration than the base layer, and a gate electrode formed so as to face the drift layer, the base layer, and the source layer with an insulating film interposed therebetween,
- the semiconductor substrate In the semiconductor device having the interlayer insulating film formed on the main surface of the second conductive layer, the second conductive layer is connected to the source layer, overlaps the contact layer, and is shallower than the base layer and formed at a high
- the total doping amount per unit area of the counter layer is preferably larger than the total doping amount per unit area of the contact layer.
- the total doping amount per unit area of the counter layer and the contact layer may be larger than the total doping amount per unit area of the source layer.
- the total doping amount per unit area of the counter layer is preferably larger than the total doping amount per unit area of the source layer.
- the counter layer may be formed so as to be self-aligned with the position of the opening of the interlayer insulating film.
- a plurality of the counter layers may be provided in the above invention.
- the semiconductor device may be an IGBT in the above invention.
- the semiconductor device may be a trench gate type IGBT.
- the cross-sectional shape of the pn junction between the counter layer and the source layer may have a convex portion toward the inside of the source layer.
- a method for manufacturing a semiconductor device wherein the contact layer has a range such that the contact layer is shallower than a base layer provided in the semiconductor device.
- the range is deeper than the source layer and shallower than the base layer, and the dose of ion implantation in the first step At least 10% of the dose, characterized in that it comprises a third step of ion-implanting a dopant of a second conductivity type in the first principal surface, a.
- the dose amount of the ion implantation in the third step is preferably larger than the dose amount of the ion implantation in the first step.
- the sum of the dose amount of ion implantation in the first step and the dose amount of ion implantation in the third step is the second invention. It may be larger than the dose amount of ion implantation in this step.
- the dose amount of the ion implantation in the third step is preferably larger than the dose amount of the ion implantation in the second step.
- the ion implantation in the third step may be performed using the interlayer insulating film in which openings are selectively formed as a mask.
- the present invention it is possible to provide a semiconductor device in which switching breakdown caused by a process defect is reduced in an insulated gate semiconductor device such as an IGBT or a MOSFET, and a manufacturing method thereof.
- FIG. 1 is a cross-sectional view of main parts of a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 6 is a cross-sectional view showing a semiconductor device manufacturing method and operating principle according to the embodiment of the present invention.
- FIG. 7 is a concentration distribution diagram showing the net doping concentration of the semiconductor device according to the embodiment of the present invention.
- FIG. 8 is a concentration distribution diagram showing the net doping concentration of the semiconductor device according to the embodiment of the present invention.
- FIG. 9 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 10 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 11 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.
- FIG. 12 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 13 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 14 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 15 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 16 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 17 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 18 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention.
- FIG. 19 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.
- FIG. 20 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 21 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 22 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 23 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 24 is a cross-sectional view illustrating the operation of the semiconductor device according to the embodiment of the present invention and the conventional semiconductor device.
- FIG. 25 is a cross-sectional view of a main part of a conventional semiconductor device.
- FIG. 26 is a cross-sectional view for explaining the operation of a conventional semiconductor device.
- FIG. 27 is a cross-sectional view of main parts of a conventional semiconductor device.
- FIG. 28 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
- FIG. 29 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
- FIG. 30 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
- FIG. 31 is a cross-sectional view for explaining the operation of a conventional semiconductor device.
- the first conductivity type is n-type and the second conductivity type is p-type.
- the first conductivity type is n-type and the second conductivity type is not limited to the p-type, but the n-type and the p-type are interchanged so that the first conductivity type is the p-type and the second conductivity type is There are parts that can operate in the same way even when the n-type is used.
- the expression “device”, “element”, “chip”, or “semiconductor chip” is also used for the semiconductor device, but all indicate the same object.
- the surface of the silicon substrate may be written as the upper surface, and the back surface as the lower surface.
- a region where an emitter electrode is formed and a current can flow is referred to as an “active region”.
- a structure portion that is a region from an end portion of the active region to an outer peripheral side end portion of the chip and that reduces the electric field strength of the chip surface generated when a voltage is applied to the element This is called a “termination structure region”.
- the display of 1.0E12 / cm 2 is used in the sense of 1.0 ⁇ 10 12 / cm 2 .
- the + ( ⁇ ) sign to the right of each region (p region, n region) shown in each figure means that the impurity concentration is relatively higher (lower) than other regions. ing.
- the concentration obtained by integrating the impurity doping concentration distribution per unit volume serving as a donor or acceptor in the depth direction of the semiconductor substrate is referred to as the total doping amount or simply the total amount per unit area.
- FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention.
- FIG. 1 shows a cross-sectional view of an IGBT which is a semiconductor device according to the first embodiment.
- a p-type base layer 4 having a higher concentration than that of the n-type drift layer 1 is selectively formed on the surface of the semiconductor substrate including the n-type drift layer 1.
- An n-type source layer 5 having a higher concentration than the p-type base layer 4 is selectively formed on the surface of the p-type base layer 4.
- a p-type contact layer 6 is formed on the p-type base layer 4 so as to be in contact with the selectively formed n-type source layer 5.
- polysilicon for the gate electrode is provided on the surface of the semiconductor substrate so as to face the surfaces of the n-type source layer 5, the p-type base layer 4, and the n-type drift layer 1 through the gate oxide film 10. Electrode 11 is selectively formed. The polysilicon electrode 11 is gathered on the chip and connected to a gate electrode pad (portion connected to the gate terminal of the package) (not shown).
- a p-type counter layer 7 having a higher concentration than the p-type base layer 4 is formed on the surface of the semiconductor substrate made of the n-type drift layer 1.
- the p-type counter layer 7 is in contact with the n-type source layer 5, overlaps the p-type contact layer 6, and does not exceed the end of the n-type source layer 5 on the side facing the polysilicon electrode 11, that is, the p-type base
- the p-type base layer 4 is formed shallower than the interface where the layer 4 and the gate oxide film 10 are in contact with each other.
- the p-type base layer 4 is connected to the emitter electrode 12. In this way, a MOS gate structure is formed.
- the interlayer insulating film 9 is formed so as to cover the polysilicon electrode 11.
- the interlayer insulating film 9 is opened at the upper surface portion of the p-type base layer 4 so that the n-type source layer 5 and the p-type counter layer 7 are exposed.
- the aforementioned emitter electrode 12 made of aluminum or the like is formed on the surface of the chip.
- the emitter electrode 12 is electrically connected to the n-type source layer 5 and the p-type counter layer 7 through the opening of the interlayer insulating film 9.
- the emitter electrode 12 and the polysilicon electrode 11 serving as a gate are insulated by an interlayer insulating film 9.
- an n-type field stop layer 2 is formed on the lower surface of the semiconductor substrate so as to be in contact with the n-type drift layer 1, and a p-type collector layer 3 is further formed so as to be in contact with the n-type field stop layer 2.
- the collector electrode 13 formed on the surface layer on the lower surface is connected.
- FIG. 1 shows a finished structure when the above-described three types of pattern defects do not occur. The case where three types of pattern defects occur will be described later.
- the p-type counter layer 7 has the following three relationships with the p-type contact layer 6, the n-type source layer 5, and the p-type base layer 4.
- the first relationship is that the p-type counter layer 7 is formed in contact with the n-type source layer 5 and deeper than the n-type source layer 5. By forming in this way, the hole current passes through the p-type counter layer 7 and flows to the emitter electrode 12, and the voltage drop immediately below the n-type source layer 5 can be reduced.
- the second relationship is that the p-type counter layer 7 overlaps the p-type contact layer 6.
- the purpose of forming the p-type counter layer 7 is to provide an effect similar to that of the same layer for preventing latch-up even if a formation failure (missing or the like) occurs in the p-type contact layer 6.
- the formation region of the p-type counter layer 7 (planar distribution on the chip surface and the concentration distribution in the depth direction) is the same as or at least overlaps with the p-type contact layer 6. The resistance of the part must be lowered.
- the third relationship is that the p-type counter layer 7 is separated from the interface between the p-type base layer 4 and the gate oxide film 10 and needs to be formed shallower than the p-type base layer 4. It is.
- the gate threshold is determined by the concentration of the p-type base layer 4. Therefore, a p-type counter layer 7 having a higher concentration than the p-type base layer 4 is formed in the electron channel (inversion layer) portion formed on the surface of the p-type base layer 4 when the MOS gate is on. Then, the threshold value changes.
- the p-type counter layer 7 is provided with a p-type base layer. 4 and the gate oxide film 10 are formed so as to be separated from the interface.
- the p-type counter layer 7 is formed deeper than the p-type base layer 4, the depletion layer extends from the p-type counter layer 7.
- the electric field strength becomes extremely high and the breakdown voltage is lowered.
- the p-type counter layer 7 only needs to be formed shallower than the p-type base layer 4.
- FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 2 shows only the flow of the process related to the formation of the p-type counter layer 7 in the manufacturing process of the IGBT of the first embodiment. First, the process proceeds through a standard IGBT or MOSFET manufacturing process until just before FIG.
- an initial oxide film having a thickness of 8000 mm is formed by thermal oxidation on the surface of an n-type FZ (float zone) type semiconductor substrate of about 60 ⁇ cm.
- the initial oxide film is patterned by a photolithographic method, then boron is ion-implanted, thermal diffusion is performed, and a termination structure region that relaxes the electric field of the depletion layer that spreads when off, for example, a well-known guard ring structure is formed ( Not shown).
- the initial oxide film in the active region is removed by the photolithographic method, the gate oxide film 10 is formed by thermal oxidation, and the polysilicon film is formed by the deposition method. Then, the polysilicon film is patterned by the photolithographic method to form polysilicon.
- the electrode 11 is formed.
- boron ion implantation is performed and heat treatment is performed to form the p-type base layer 4.
- the dose of boron ion implantation 18 is 2E14 / cm 2 and the acceleration energy is 150 keV.
- the temperature of the heat treatment and the temperature maintenance time are 1150 ° C. and 60 minutes.
- the resist 8 is patterned by a photolithographic method and baked (the resist is stabilized by a heat treatment at a temperature of about 150 ° C.) to form the upper surface of the p-type base layer 4.
- a mask of the resist 8 having a part thereof opened is formed.
- boron ion implantation 18 is performed using the patterned resist 8 as a mask.
- the dose at this time is, for example, 1E15 / cm 2 and the acceleration energy is 60 keV.
- the boron ion range (Rp) is about 0.20 ⁇ m.
- boron is introduced into a region that will later become the p-type contact layer 6.
- a thin oxide film may be formed as long as it does not affect the ion implantation range as follows. .
- the gate oxide film may be left.
- the gate oxide film may be removed once using the polysilicon electrode 11 as a mask before the resist 8 is applied, and then a screening oxide film having a thickness of about 300 mm may be formed by thermal oxidation.
- a resist 8 is applied, and the resist 8 is patterned and baked in a part of the opening on the surface of the p-type base layer 4 so as not to contact the polysilicon electrode 11.
- arsenic ion implantation 19 (phosphorous is also possible) serving as a donor is performed, and heat treatment is performed.
- the dose of the arsenic ion implantation 19 is, for example, 4E15 / cm 2 and the acceleration energy is 120 keV.
- the range of arsenic ions at this time is about 0.08 ⁇ m. For the same acceleration energy, arsenic has a shallower range than boron.
- the n-type source layer 5 is formed. The heat treatment at this time may be omitted.
- a resist 8 is applied, and patterning and baking are performed so that a part of the surface of the p-type base layer 4 is opened.
- boron ion implantation 18 is performed using the resist 8 as a mask, and after the resist 8 is removed, heat treatment is performed.
- the dose of boron ion implantation is, for example, 5E15 / cm 2 and the acceleration energy is 50 keV.
- the range of boron ions at this time is 0.17 ⁇ m.
- the temperature and temperature maintenance time of heat processing are 30 minutes at 950 degreeC, for example. In this way, the p-type counter layer 7 is formed as shown in FIG.
- the first condition is that in the patterning of the resist 8 in FIG. 2C, at least a part of the opening for performing boron ions is a region where the n-type source layer 5 is formed, that is, when arsenic is ion-implanted. It overlaps with the opening of the resist. Further, the end of the opening of the resist 8 for the p-type counter layer 7 is separated from the end of the interface where the p-type base layer 4 and the gate oxide film 10 are in contact, or the n-type source layer 5 and the p-type. Patterning is performed so as not to exceed the position where the base layer 4 contacts (inside). This condition may be adjusted by the layout of the photomask and reticle.
- the second condition is that the boron ion range in forming the p-type counter layer 7 is deeper than the n-type source layer 5. Further, a part of the p-type counter layer 7 has a range that overlaps the p-type contact layer 6 and a part shallower than the p-type base layer 4. That is, if the boron ion implantation range when forming the p-type counter layer 7 is Rp7 and the arsenic ion implantation range when forming the n-type source layer 5 is Rp5, then Rp7> Rp5. The acceleration energy of each ion implantation may be adjusted.
- the acceleration energy of boron ion implantation for the p-type counter layer 7 is preferably the same as or lower than the acceleration energy for ion implantation for the p-type contact layer 6.
- the acceleration energy is 60 keV (range is 0.20 ⁇ m)
- the acceleration energy is 120 keV (range is 0.08 ⁇ m)
- the acceleration energy of the boron ion implantation 18 for the p-type counter layer 7 is 50 keV (range is 0.17 ⁇ m).
- Embodiment 1 of the present invention it will be described how the semiconductor device and the manufacturing method of the present invention prevent the aforementioned three pattern defects under specific formation conditions.
- FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 3A to FIG. 3D are cross-sectional views showing process transitions when this pattern defect (2) occurs in the manufacturing method of the first embodiment.
- FIG. 3A to FIG. 3D of the process transition (flow) are the same as those in FIG. 2 described above, so only the differences will be described.
- the resist 8 is patterned to form the p-type contact layer 6, and boron ion implantation 18 is performed using the resist 8 as a mask. Subsequently, as shown in FIG. 3B, arsenic ion implantation 19 is performed using the resist 8 as a mask. At this time, it is assumed that the resist 8 is exposed with respect to the p-type base layer 4 on the left side of the figure, and the resist 8 does not remain where it should remain.
- the cause of such extra exposure may be a missing portion in a light shielding layer such as chrome on the mask.
- a light shielding layer such as chrome on the mask.
- foreign matter particles, dust, etc.
- arsenic ions are introduced into the entire opening of the polysilicon electrode 11 in the left p-type base layer 4. Since arsenic has a higher mass than boron and has a short range (shallow), the n-type source layer 5 is formed on the entire surface layer after the heat treatment (see FIG. 3C).
- the resist 8 is patterned, and boron ion implantation 18 is performed in a predetermined region of the p-type base layer 4 described above.
- the implanted boron cancels out the n-type source layer 5 formed in the entire opening of the polysilicon electrode 11 of the left-side p-type base layer 4, and the right-side p-type base as shown in FIG.
- a p-type counter layer 7 is formed in substantially the same manner as the layer 4.
- the p-type counter layer 7 The n-type source layer 5 can be canceled out.
- FIG. 6 is used to explain how the resistance of the hole current path is reduced by the p-type counter layer canceling out the unnecessary n-type source.
- FIG. 6 is a cross-sectional view showing a semiconductor device manufacturing method and operating principle according to the embodiment of the present invention.
- FIG. 6 shows the flow of holes and the resistance component of the p-type base layer in the on state or turn-off in the IGBT according to the first embodiment of the present invention.
- FIG. 6 is a case where a p-type counter layer is introduced into this pattern defect (1).
- the n-type source layer 5 formed unnecessarily becomes the polysilicon electrode 11 on the surface of the p-type base layer 4. Slightly remains in the opening.
- the p-type counter layer 7 is also formed in the left p-type base layer 4.
- the n-type source layer 5 introduced excessively cancels out and disappears, and in addition, a p-type high-concentration layer can be formed.
- the p-type base layer 4 on the left side of FIG. 6A is similar to the normal p-type base layer 4 in which no extra n-type source layer 5 is introduced (the right side of FIG. 6A).
- the structure can be as follows.
- the condition for offsetting the extra n-type source layer 5 by the p-type counter layer 7 is It is as follows. That is, the total doping amount per unit area of the p-type contact layer 6 and the p-type counter layer 7 may be larger than the total doping amount per unit area of the n-type source layer 5. More preferably, it may be twice or more.
- FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 4A to FIG. 4D show process transitions when this pattern defect (2) occurs in the manufacturing method of the first embodiment.
- a resist 8 is applied and patterned in order to form the p-type contact layer 6.
- the resist 8 is not exposed and removed from the p-type base layer 4 on the left side of FIG.
- the reason why the exposure is not performed is, for example, a case where a light shielding layer such as chrome on the mask is missing or a foreign matter (particle, dust, etc.) is placed on the resist 8 of the p-type base layer 4 during exposure to block the light. is there.
- boron ion implantation 18 is performed using the resist 8 after baking as a mask. Then, as shown in FIG. 4 (b), boron is introduced only into the p-type base layer 4 on the right side of FIG. 4 (b) to form the p-type contact layer 6, which is also the left side of FIG. 4 (b). The p-type contact layer 6 is not formed on the p-type base layer 4.
- arsenic ion implantation 19 is performed using the resist 8 as a mask.
- a p-type layer having a higher concentration than the same layer is not formed on the left p-type base layer.
- a resist 8 is applied and patterned, boron ion implantation 18 is performed using the resist 8 as a mask, and heat treatment is performed after the resist is removed, so that the left side as shown in FIG.
- a p-type counter layer 7 is formed on both the p-type base layers 4 on the right side and the right side. That is, in the stage of FIG.
- boron in the p-type contact layer 6 is not introduced into the left-side p-type base layer 4, but boron is introduced in this step and is higher than in the p-type base layer 4.
- a p-type counter layer 7 having a concentration can also be formed in the p-type base layer 4 on the left side in FIG.
- the acceptor concentration on the path of the hole flow 17 is equal to that of the p-type base layer 4. Since only these are formed, the resistance component 16 becomes extremely large.
- the p-type contact layer 6 is also missing (the surface of the left p-type base layer 4). Boron is introduced by ion implantation to form the p-type counter layer 7. Therefore, as shown in FIG. 6B, the resistance component 16 on the path of the hole flow 17 becomes small, and latch-up can be prevented.
- the p-type contact layer 6 needs to have a sufficiently small sheet resistance per unit area when a hole current flows.
- a hole current may flow, for example, about 1000 A / cm 2 immediately below the n-type source layer 5.
- the length (the horizontal length on the paper surface) of the n-type source layer 5 is 1 ⁇ m and the width (the vertical length on the paper surface) is 300 ⁇ m. 01 cm 2 .
- this sheet resistance is converted into an acceptor concentration per unit area, it must be 4.596E15 / 42 ⁇ 1.1E14 / cm 2 or more. That is, the concentration (total amount) per unit area of the p-type counter layer must be at least this value (1.1E14 / cm 2 ) or more.
- the margin is set so that the total amount per unit area of the p-type contact layer 6 is higher than this calculated value, for example, it is set to 1.0E15 / cm 2 or more corresponding to about 10 times this value.
- the total amount thereof is at least 10% (1/10) of the total amount of the p-type contact layer 6; That is, it is necessary to make it larger than the aforementioned 1.1E14 / cm 2 . More preferably, the total amount of the p-type counter layer 7 is 1.0E15 / cm 2 or more, that is, larger than the total amount of the p-type contact layer 6.
- FIG. 7 is a concentration distribution diagram showing the net doping concentration of the semiconductor device according to the embodiment of the present invention.
- FIG. 7 shows a net doping concentration distribution when the cross section is cut along the cutting line A1-A2 shown in FIG.
- the net doping concentration on the vertical axis is a logarithmic scale.
- the total amount of the p-type counter layer 7 is about 0.1 (10%) of the total amount of the p-type contact layer 6, as shown in FIG. It is shallower than the layer and the maximum concentration is lower. Therefore, the entire p-type counter layer 7 is included in the p-type contact layer 6 in the depth direction.
- the concentration of the p-type counter layer 7 preferably has a concentration that is at least equal to or higher than this concentration distribution. More preferably, the total amount of the p-type counter layer 7 is not less than the total amount of the p-type contact layer 6. Although not shown, the concentration distribution of the p-type counter layer 7 at this time is substantially the same as that of the p-type contact layer 6 and has a slightly shallow distribution shape. More preferably, the total amount of the p-type counter layer 7 should be twice or more the total amount of the p-type contact layer 6.
- the net doping concentration distribution of the p-type counter layer 7 is shallower and higher than the concentration distribution of the p-type contact layer 6.
- the depth may be slightly deeper.
- the object of the present invention can be achieved if the missing portion of the p-type contact layer 6 is compensated or the concentration of the extra n-type source layer 5 is offset.
- a manufacturing method for actually realizing the total amount of the p-type counter layer 7 associated with such a relationship with the p-type contact layer 6 may be as follows.
- the total amount of each p-type layer at the time of manufacturing is almost the same as the dose amount in boron ion implantation.
- the dose of the boron ion implantation 18 for forming the p-type counter layer 7 in FIG. 4C is changed to the dose of the boron ion implantation 18 in forming the p-type contact layer 6 in FIG.
- it may be larger than 0.1 times.
- the dose of boron ion implantation for forming the p-type counter layer 7 in FIG. 4C is set to the boron ion implantation at the time of forming the p-type contact layer 6. What is necessary is just to make it larger than the dose of (refer the arrow 18 in Fig.4 (a)). More preferably, the dose of boron ion implantation (see arrow 18 in FIG. 4C) for forming the p-type counter layer 7 in FIG. 4C is set to the boron ion at the time of forming the p-type contact layer 6. What is necessary is just to make it larger than twice the dose of implantation (see arrow 18 in FIG. 4A).
- FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- This pattern defect (3) is a defect that can occur sufficiently, although the frequency of occurrence is very low compared to the pattern defects (1) and (2).
- FIG. 5A to FIG. 5D are cross-sectional views showing process transitions when this pattern defect (3) occurs in the manufacturing method of the first embodiment.
- a resist 8 is applied and patterned in order to form the p-type contact layer 6. At this time, it is assumed that the resist 8 is not exposed and removed from the p-type base layer 4 on the left side of FIG. The reason why this exposure is not performed is as described above.
- arsenic ion implantation 19 is performed using the resist 8 as a mask.
- the resist 8 is exposed with respect to the p-type base layer 4 on the left side of FIG. 5B, and the resist 8 does not remain where it should remain. The reason for such extra exposure is as described above.
- arsenic ions are introduced into the entire opening of the polysilicon electrode 11 in the left p-type base layer 4.
- an n-type source layer is formed on the entire surface layer.
- the p-type base layer 4 on the left side of FIG. 5C is not formed with a p-type layer having a higher concentration than the same layer.
- the resist 8 is applied and patterned, and boron ion implantation (see the arrow 18 in FIG. 5C) is performed using the resist 8 as a mask, and heat treatment is performed.
- a p-type counter layer 7 is formed on the mold base layer 4. That is, in the stage of FIG. 5A, boron in the p-type contact layer 6 is not introduced into the left-side p-type base layer 4, but boron is introduced in this step and is higher than the p-type base layer 4.
- a p-type counter layer 7 having a concentration is formed.
- the total amount of the p-type counter layer 7 may be larger than the total amount of the n-type source layer 5.
- the p-type counter layer compensates for the concentration with respect to the n-type source layer 5 to cancel out the p-type counter layer at the outermost layer of the p-type base layer 4.
- the concentration must be higher than that of the n-type source layer 5.
- the n-type source layer 5 must be offset not only in the outermost layer but also in the depth direction.
- the total amount of the p-type counter layer 7 is preferably larger than the total amount of the n-type source layer 5.
- the region where the p-type counter layer 7 is formed on the surface of the p-type base layer 4 is preferably narrowed so as to overlap with a part of the region where the n-type source layer 5 is formed. The reason is that the n-type source layer 5 disappears when the p-type counter layer 7 having a larger total amount is formed in the region where the n-type source layer 5 is originally formed.
- FIG. 8 is a concentration distribution diagram showing the net doping concentration of the semiconductor device according to the embodiment of the present invention.
- FIG. 8 shows a schematic diagram of the net doping concentration distribution when the IGBT which is the semiconductor device according to the first embodiment is cut along the cutting line B1-B2 shown in FIG.
- the surface of the n-type source layer 5 should not be canceled out by the p-type counter layer 7 at the position of the cutting line B1-B2 that originally forms the n-type source layer 5.
- the p-type counter layer 7 in this region may not be an ion implantation region but a lateral diffusion portion slightly protruding from the implantation region.
- the depth obtained by subtracting the standard deviation ⁇ Rp from Rp is deeper than the arsenic range Rp of the n-type source layer 5. It may be.
- the net doping concentration of the n-type source layer 5 is offset by the boron of the p-type counter layer 7. Can be suppressed.
- the p-type counter layer of the present invention is formed so as to be in contact with the n-type source layer 5 and partially overlap the p-type contact layer. Therefore, the effect of preventing the p-type contact layer 6 from being lost and the formation of an extra n-type source layer 5 can also be achieved.
- a sheet resistance sufficiently low as described above is formed immediately below the n-type source layer 5.
- the step of deeply diffusing the p-type high concentration layer is contrary to the miniaturization purpose of reducing the size of the MOS gate and shallowing the diffusion layer such as the p-type base layer. Therefore, boron must be implanted into a region that is extremely narrower than the region where the p-type base layer 64 is formed, and the effect of preventing latch-up cannot be expected so much.
- FIG. 9 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 9A shows a cross-sectional view of an IGBT showing the second embodiment of the semiconductor device of the present invention
- FIG. 9B shows a cutting line A1-A2 described inside FIG. 9A.
- the solid line in FIG. 9B indicates the concentration distribution along the cutting line A1-A2, and the broken line indicates the concentration distribution along B1-B2.
- the feature of the second embodiment is that the p-type counter layer 7 is formed to be shallower than the p-type contact layer 6 in the horizontal direction of the paper in the horizontal direction.
- the first method for forming the IGBT of the second embodiment is to make the photomask for boron ion implantation resist pattern for forming the p-type contact layer 6 and the photomask for the p-type counter layer 7 the same. .
- the second method of forming the IGBT according to the second embodiment is to reduce the acceleration voltage for boron ion implantation of the p-type counter layer 7.
- the acceleration voltage may be the same, and heat treatment (for example, holding at 1000 ° C. for 30 minutes) may be performed between the boron ion implantation of the p-type contact layer 6 and the boron ion implantation of the p-type counter layer 7.
- the p-type counter layer 7 intentionally shallower than the p-type contact layer 6, there is an effect of preventing the pattern defects (1), (2), and (3).
- the effect of offsetting the extra n-type source layer 5 formed on the surface layer of the p-type base layer such as pattern defects (1) and (3) can be enhanced. Therefore, it is possible to prevent the p-type contact layer 6 from being lost or the formation of an extra n-type source layer 5 to prevent the occurrence of latch-up.
- FIG. 10 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 10A shows a cross-sectional view of the IGBT according to the third embodiment of the present invention
- FIG. 10B shows the cutting lines A1-A2 and B1- shown in FIG. 10A.
- the net doping concentration distribution along B2 is shown.
- the solid line in FIG. 10B shows the concentration distribution along the cutting line A1-A2, and the broken line in FIG. 10B shows the concentration distribution along B1-B2.
- the third embodiment There are two features of the third embodiment.
- the first feature of the third embodiment is that the p-type counter layer 7 is formed to have a substantially equal depth while narrowing the width in the horizontal direction of the paper surface with respect to the p-type contact layer 6.
- the second feature of the third embodiment is that the pattern shapes of the resist mask for ion implantation of the p-type contact layer 6 and the p-type counter layer 7 are different in the planar distribution on the upper surface of the element.
- FIG. 11 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.
- FIG. 11 is a plan view showing the flow of the manufacturing process of the IGBT according to the third embodiment, and shows a part of the active region in an enlarged manner.
- the processing performed in (a) to (d) of the flowchart shown in FIG. 11 is almost the same processing as (a) to (d) of FIG. I will explain in detail.
- boron is ion-implanted into the polysilicon electrode 11 for gate and the p-type base layer 4 using a resist mask, and the p-type contact layer 6 as shown in FIG. 11B. Form. At this time, the opening of the resist mask is separated from the longitudinal end of the polysilicon electrode 11.
- n-type source layer 5 is also formed in the lateral direction of the polysilicon electrode 11 (vertical direction in the drawing) so as to connect the n-type source layer 5 in contact with the adjacent polysilicon electrodes 11.
- the resist mask for the p-type counter layer 7 is also formed in a ladder shape so that the ladder-shaped n-type source layer 5 does not disappear due to compensation in the p-type counter layer 7, and boron is added to the n-type source layer 5. Do not enter the ladder. Further, the opening of the resist mask at this time is slightly wider than the opening of the n-type source layer 5.
- the shape of the resist mask pattern for ion implantation of the p-type contact layer 6 and the p-type counter layer 7 is changed to provide a place where the n-type source layer 5 is not erased by the p-type counter layer 7. .
- a high-concentration n-type source layer 5 can be additionally formed.
- the contact resistance between the n-type source layer 5 and an emitter electrode to be formed later can be reduced.
- FIG. 12 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 12A shows a cross-sectional view of an IGBT according to the fourth embodiment of the present invention
- FIG. 12B shows cutting lines A1-A2 and B1- shown in FIG. 12A. The net doping concentration distribution along B2 is shown.
- the solid line in FIG. 12B indicates the concentration distribution along the cutting line A1-A2, and the broken line in FIG. 12B indicates the concentration distribution along B1-B2.
- the feature of the fourth embodiment is that the depths of the p-type contact layer 6 and the p-type counter layer 7 are different from those of the third embodiment.
- the p-type contact layer 6 is formed deeper. This has the advantages of adding a new function to the p-type contact layer 6 and enhancing the effect of preventing latch-up, as will be described below.
- the p-type contact layer 6 having a higher concentration than the p-type base layer 4 is formed deeper while taking care not to reach the inversion layer channel formed immediately below the gate oxide film 10. There is a way.
- the p-type contact layer 6 stops the depletion layer extending in the p-type base layer 4.
- the p-type contact layer 6 when there is no p-type counter layer 7 as in the conventional IGBT, the p-type contact layer 6 must have a function of a high concentration layer for preventing latch-up.
- the concentration of the p-type contact layer 6 immediately below the n-type source layer 5 must be secured to the above-described concentration (or sheet resistance).
- the p-type contact layer 6 As a result, it is necessary to form the p-type contact layer 6 at a depth shallower than 1 ⁇ m from the bottom of the n-type source layer 5, and the end (depletion layer end) of the depletion layer is also at the last of the n-type source layer 5. It will stop.
- the distance of the charge neutral region (here, less than 1 ⁇ m) between the end of the depletion layer and the n-type source layer 5 determines the injection efficiency of electrons injected from the n-type source layer 5, so that it is as long as possible. Want to secure.
- the p-type counter layer 7 is introduced as in the present invention, and the p-type counter layer 7 has a high acceptor concentration at a depth shallower than 1 ⁇ m from the bottom of the n-type source layer 5 and is in contact with the n-type source layer 5.
- the p-type contact layer 6 is formed so as to be slightly deeper than the p-type counter layer 7 (for example, 1 to 2 ⁇ m from the chip surface) and wide in the lateral direction so as not to reach the inversion layer channel.
- FIG. 13 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 13 shows a cross-sectional view of an IGBT according to the fifth embodiment of the present invention.
- the feature of the fifth embodiment is that the p-type counter layer 7 is formed to be self-aligned with the contact opening 14 of the interlayer insulating film 9 as a difference from the first embodiment.
- FIG. 14 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 14 is a plan view showing the flow of the manufacturing process of the IGBT according to the fifth embodiment, and shows a part of the active region in an enlarged manner.
- FIG. 14 is a cross-sectional view of the portion corresponding to C1-C2 (the ladder portion of the n-type source layer 5) shown in FIG.
- the processing performed in (a) to (d) of the flowchart shown in FIG. 14 is similar to (a) to (d) of FIG. 2 described above, but the main difference is that p Boron ion implantation for the mold counter layer 7 (see arrow 18 in FIG. 14D) is not a resist mask but a patterned interlayer insulating film.
- boron ion implantation (see arrow 18 in FIG. 14A) is performed on the polysilicon electrode 11 for gate and the p-type base layer 4 using the resist 8 as a mask. Then, the p-type contact layer 6 is formed. Heat treatment may be performed after the resist removal after the boron ion implantation.
- arsenic ion implantation 19 is performed using the resist 8 and the polysilicon electrode 11 as a mask.
- a mask of the resist 8 is formed again, and arsenic ion implantation 19 is performed.
- a region where arsenic ions are implanted is only the ladder portion of the n-type source layer 5 in FIG. 11D described in the third embodiment. This process is an important point in the fifth embodiment, and the reason will be described at the stage when other processes are completed.
- the resist 8 is removed and heat treatment is performed to form the n-type source layer 5.
- an interlayer insulating film 9 is formed by an LP-CVD method using an oxide film such as PSG or BPSG, and a contact opening is formed in the interlayer insulating film 9 by dry etching or the like by a photolithography method. 14 is formed. This opening becomes a connection region between an emitter electrode (not shown) to be formed later, the n-type source layer 5 and the p-type counter layer 7.
- boron ion implantation is performed using the already formed interlayer insulating film 9 as a mask without performing a new photolithography method (see arrow 18 in FIG. 14D). I do.
- boron ions are implanted only into the contact opening 14 of the interlayer insulating film 9.
- heat treatment for example, holding 950 ° C. for 1 hour is performed to form the p-type counter layer 7 self-aligned with the contact opening 14 of the interlayer insulating film 9 as shown in FIG.
- the feature of the fifth embodiment is that the n-type source layer 5 formed in the contact opening 14 of the interlayer insulating film 9 is devised so as not to disappear completely by the compensation of the p-type counter layer 7. is there.
- boron ion implantation (see arrow 18 in FIG. 14D) of the p-type counter layer 7 is performed using the interlayer insulating film 9 as a mask. Therefore, when the p-type counter layer 7 is formed to prevent the pattern defects (1) to (3), concentration compensation by the p-type layer occurs in some cases, and the p-type counter layer 7 is formed in the contact opening 14 of the interlayer insulating film 9.
- the n-type source layer 5 disappears, and the contact (electrical connection) between the n-type source layer 5 and the emitter electrode becomes impossible.
- the emitter electrode and the n-type source layer 5 are brought into contact at the ladder portion of the n-type source layer 5 described above.
- Only the n-type source layer 5 in the above-mentioned ladder portion has a donor concentration (total amount) so as not to cancel even if boron ion implantation for the p-type counter layer 7 (see the arrow 18 in FIG. 14D) is performed. Is made larger than the total of the total amount of the p-type counter layer 7 and the p-type contact layer 6.
- arsenic may be ion-implanted only into the ladder portion.
- the p-type counter layer 7 is formed so as to be self-aligned with the contact opening 14 of the interlayer insulating film 9. it can. As a result, not only does the p-type counter layer 7 reliably contact the emitter electrode in the opening, but the n-type source layer 5 exposed in the opening disappears except for the ladder portion, leading to the inversion layer channel. The n-type source layer 5 is formed only below the interlayer insulating film.
- the width of the n-type source layer 5 (width in the short direction of the polysilicon electrode) can be further shortened, and the resistance component around the n-type source layer 5 can be reduced, thereby further enhancing the latch-up suppressing effect.
- FIG. 15 is a cross-sectional view of the main part of the semiconductor device according to the embodiment of the present invention and a concentration distribution diagram showing the net doping concentration.
- FIG. 15A shows a cross-sectional view of the IGBT according to the sixth embodiment of the present invention
- FIG. 15B shows the cutting lines A1-A2 and B1- shown in FIG. 15A.
- the net doping concentration distribution along B2 is shown.
- the solid line in FIG. 15B indicates the concentration distribution along the cutting line A1-A2, and the broken line in FIG. 15B indicates the concentration distribution along B1-B2.
- the feature of the sixth embodiment is that a plurality of p-type counter layers are formed as a difference from the first embodiment.
- a plurality of p-type counter layers are formed as a difference from the first embodiment.
- three p-type counter layers 7a, 7b, 7c are formed. It is that.
- the formation depth of the p-type contact layer 6 is increased.
- a plurality of p-type counter layers 7 are formed.
- the total amount of each of the plurality of p-type counter layers 7a, 7b, 7c may be the same or different. The same applies to the formation depth of these layers (Rp for ion implantation). Further, the total value (dose amount) of the individual p-type counter layers 7a, 7b, and 7c and the depth (Rp) may satisfy the conditions described in the first embodiment.
- FIG. 16 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 16 is a cross-sectional view of an IGBT according to the seventh embodiment of the present invention.
- the feature of the seventh embodiment is that the MOS gate structure is changed from a planar gate type to a trench gate type as a difference from the first embodiment.
- a p-type base layer 4 having a higher concentration than the n-type drift layer 1 is formed on the surface of the semiconductor substrate made of the n-type drift layer 1.
- An n-type source layer 5 having a higher concentration than the p-type base layer 4 is selectively formed on the surface of the p-type base layer 4.
- a p-type contact layer 6 is formed on the p-type base layer 4 so as to be in contact with the selectively formed n-type source layer 5.
- grooves are regularly formed on the surface of the semiconductor substrate, and a gate oxide film 10 is formed on the inner wall of the trench.
- a polysilicon electrode 11 is embedded via the gate oxide film 10 so as to face the surfaces of the n-type source layer 5, the p-type base layer 4, and the n-type drift layer 1.
- the polysilicon electrode 11 is collected on a chip (not shown) and connected to the gate electrode.
- a trench gate type MOS gate structure as described above is formed. Then, the p-type counter layer 7 having a higher concentration than the p-type base layer 4 is in contact with the n-type source layer 5, and most of the p-type counter layer 7 overlaps with the p-type contact layer 6, and the n-type source layer on the side facing the gate electrode 5 so as to be included in the p-type base layer 4 within a range not exceeding the end of 5.
- the p-type base layer 4 is connected to the emitter electrode 12.
- an interlayer insulating film 9 is formed so as to cover the upper portion of the polysilicon electrode 11, and the interlayer insulating film 9 is formed so that the n-type source layer 5 and the p-type counter layer 7 are exposed on the upper surface portion of the p-type base layer 4. It is open.
- the aforementioned emitter electrode 12 made of aluminum or the like is formed on the surface of the chip, and is electrically connected to the n-type source layer 5 and the p-type counter layer 7 through the opening of the interlayer insulating film 9.
- an n-type field stop layer 2 is formed on the lower surface of the semiconductor substrate so as to be in contact with the n-type drift layer 1, and a p-type collector layer 3 is further formed so as to be in contact with the n-type field stop layer 2.
- the collector electrode 13 formed on the surface layer on the lower surface is connected.
- FIG. 17 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- FIG. 17 the top view which shows the flow of the manufacturing process of IGBT of Embodiment 7 of this invention is shown, and a part of active region is expanded and shown.
- the processing performed in (a) to (d) of the flowchart of FIG. 17 is similar to (a) to (d) of FIG. To do.
- boron ion implantation (see arrow 18 in FIG. 17A) is performed on the polysilicon electrode 11 for gate and the p-type base layer 4 using the resist 8 as a mask.
- a p-type contact layer 6 is formed.
- the p-type contact layer 6 is disposed so as to be separated from the trench.
- Heat treatment may be performed after the resist removal after this boron ion implantation (see arrow 18 in FIG. 17A).
- arsenic ion implantation 19 is performed using the resist 8 and the polysilicon electrode 11 as a mask. Then, the resist 8 is removed and heat treatment is performed to form the n-type source layer 5. Subsequently, as shown in FIG. 17C, a mask of a resist 8 is newly formed and boron ion implantation (see arrow 18 in FIG. 17C) is performed to form the p-type counter layer 7. Thereafter, as shown in FIG. 17 (d), an interlayer insulating film 9 is deposited and selectively etched by photolithography to form a p-type base layer in which an n-type source layer 5 and a p-type counter layer 7 are formed. The surface of 4 is opened.
- the size thereof becomes relatively smaller than the impurities such as particles and dust, and the influence given to the pattern given by these becomes smaller. It gets bigger. In other words, the likelihood for such impurities is reduced in the characteristics of the IGBT chip. For this reason, the occurrence frequency of the above-described pattern defects (1) to (3) is also greatly increased.
- the IGBT module having a large current capacity after the IGBT is chipped from the wafer, a plurality of IGBT chips (multichip) are further connected in parallel. Therefore, the latch-up due to the above pattern failure and the occurrence rate of the switching failure due thereto are doubled by the number of IGBT chips used.
- the p-type counter layer of the present invention when the p-type counter layer of the present invention is also applied to a trench gate type IGBT, the above-mentioned pattern defect occurrence probability per chip is remarkably reduced, and at least the defect rate can be reduced to a fraction. As a result, the switching failure rate in the multi-chip high current capacity IGBT module as described above is similarly reduced. That is, the effect of the p-type counter layer 7 increases as the MOS gate structure on the chip surface becomes finer.
- FIG. 18 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention.
- FIG. 18 shows a cross-sectional view of an IGBT according to the eighth embodiment of the present invention.
- a feature of the eighth embodiment is that, as a difference from the seventh embodiment, the p-type counter layer 7 is formed narrower than the same layer by using a resist mask different from the p-type contact layer 6.
- the eighth embodiment corresponds to a case where the planar gate type IGBT of the third example is applied to a trench gate type.
- FIG. 19 is a plan view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.
- FIG. 19 is a plan view showing the flow of the manufacturing process of the IGBT according to the third embodiment, and shows a part of the active region in an enlarged manner.
- the processing performed in (a) to (d) of the flowchart of FIG. 19 is almost the same processing as (a) to (d) of FIG. 11 already described.
- boron is ion-implanted with a resist mask to form the p-type contact layer 6 as shown in FIG. 19B.
- the opening of the resist mask is separated from the longitudinal end of the trench including the polysilicon electrode 11 and the gate oxide film 10.
- arsenic ions are implanted using a resist mask to form an n-type source layer 5 as shown in FIG.
- arsenic is introduced into the above-mentioned separated portions.
- the n-type source layer 5 is also formed in the lateral direction of the polysilicon electrode 11 (vertical direction in the drawing) so as to connect the n-type source layer 5 in contact with the adjacent polysilicon electrodes 11 respectively.
- the resist mask for the p-type counter layer 7 is also formed in a ladder shape so that the ladder-shaped n-type source layer 5 does not disappear due to compensation in the p-type counter layer 7, and boron is added to the n-type source layer 5. Do not enter the ladder. Further, the opening of the resist mask at this time is slightly wider than the opening of the n-type source layer 5.
- the shape of the resist mask pattern for ion implantation of the p-type contact layer 6 and the p-type counter layer 7 is changed to provide a place where the n-type source layer 5 is not erased by the p-type counter layer 7. .
- a high-concentration n-type source layer 5 can be additionally formed.
- the contact resistance between the n-type source layer 5 and an emitter electrode to be formed later can be reduced.
- FIG. 20 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 20 shows a cross-sectional view of an IGBT according to the ninth embodiment of the present invention.
- the feature of the ninth embodiment of the present invention is that the p-type counter layer 7 is formed so as to be self-aligned with the contact opening 14 of the interlayer insulating film 9 as a difference from the eighth embodiment. It is that.
- FIGS. 21 and 22 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
- 21 and 22 are cross-sectional views showing a flow of manufacturing steps of the IGBT according to the ninth embodiment, and an enlarged view of a part of the active region.
- 21 and 22 are cross-sectional views taken along a cutting line corresponding to C1-C2 shown in (d) of FIG.
- the processing performed in (a) to (c) of the flowchart of FIG. 21 and (a) to (b) of the flowchart of FIG. 22 is similar to (a) to (d) of FIG.
- the main difference is that a boron ion implantation mask for the p-type counter layer 7 is not a resist mask but a patterned interlayer insulating film 9.
- boron ion implantation (see the arrow 18 in FIG. 21A) is performed using the resist 8 as a mask to form the p-type contact layer 6 as shown in FIG. 21B.
- Heat treatment may be performed after removing the resist 8 of this boron ion implantation (see reference numeral 18 in FIG. 21A).
- arsenic ion implantation (see an arrow 19 in FIG. 21B) is performed using the resist 8 as a mask.
- a mask of the resist 8 is formed again, and arsenic ion implantation (see an arrow 19 in FIG. 21C) is performed.
- the arsenic ion implantation region is only the ladder portion (for example, the line C1-C2) of the n-type source layer 5 in FIG. 19D described in the eighth embodiment.
- the resist 8 is removed and heat treatment is performed to form the n-type source layer 5.
- an interlayer insulating film 9 is formed by depositing a deposited oxide film such as PSG or BPSG by LP-CVD, and a contact opening is formed in the interlayer insulating film 9 by dry etching or the like by photolithography. Part 14 is formed. This contact opening 14 becomes a connection region between an emitter electrode (not shown) to be formed later, the n-type source layer 5 and the p-type counter layer 7.
- boron ion implantation is performed using the already formed interlayer insulating film 9 as a mask without performing a new photolithographic method (see arrow 18 in FIG. 22A). I do. Then, boron ions are implanted only into the contact opening 14 of the interlayer insulating film 9. Subsequently, heat treatment (for example, holding at 950 ° C. for 1 hour) is performed to form a p-type counter layer 7 that is self-aligned with the contact opening 14 of the interlayer insulating film 9 as shown in FIG. .
- the feature of the ninth embodiment is advantageous for miniaturization of the design like the trench gate structure.
- the p-type counter layer must be formed so as to be surely in contact with the n-type source layer 5 and deeper than the same layer, and at least partially overlap the p-type contact layer 6.
- the allowable range of alignment error between the layers becomes narrow. Therefore, if the contact opening 14 between the p-type counter layer 7 and the emitter electrode of the interlayer insulating film 9 is shifted, the hole current hardly flows to the emitter electrode, the resistance component increases, the voltage drop increases, and the latch-up increases. Leads to outbreak.
- the p-type counter layer 7 self-aligned with the contact opening 14 of the interlayer insulating film 9, the p-type counter layer 7 can be reliably brought into contact with the emitter electrode even under miniaturization of the design. As a result, the latch-up suppressing effect can be further enhanced.
- FIG. 23 is a fragmentary cross-sectional view of the semiconductor device according to the embodiment of the present invention.
- FIG. 23 is a sectional view showing a MOSFET according to the tenth embodiment of the present invention.
- Embodiment 1 The difference from Embodiment 1 is that there is no p-type layer on the back surface and the n-type drain layer 21 is in contact with the electrode (drain electrode 23). That is, only electrons that are majority carriers contribute to the current. Even in a MOSFET in which majority carriers carry current, there exists a parasitic bipolar transistor composed of an n-type source layer 5, a p-type base layer 4, an n-type drift layer 1 and an n-type drain layer 21. When the high voltage is turned off, the depletion layer spreads almost in the interior of the p-type base layer 4, so that the parasitic bipolar transistor is easily operated.
- the MOS gate structure according to any of the above-described embodiments is not limited to the structure shown in FIG.
- FIG. 24 is a cross-sectional view illustrating the operation of the semiconductor device according to the embodiment of the present invention and the conventional semiconductor device.
- FIG. 24 is a sectional view showing a MOS gate structure according to an eleventh embodiment of the present invention and a conventional structure.
- FIG. 24A shows a cross-sectional view of the MOS gate structure according to the eleventh embodiment of the present invention
- FIG. 24B further shows an enlarged cross-sectional view of one arbitrary p-type base layer 4.
- FIG. 24C further shows an enlarged cross-sectional view of the vicinity of the pn junction between the n-type source layer 5 and the p-type counter layer 7, and FIG. 24D shows a conventional semiconductor device. A cross-sectional view of a MOS gate structure is shown.
- it becomes convex toward the inside of the n-type source layer 5.
- the reason why the pn junction is convex toward the inside of the n-type source layer 5 in this way is that the total value of the concentration (total amount) per unit area of the p-type counter layer 7 and the p-type contact layer 6 is expressed as n-type. This is to make it higher than the total amount of the source layer 5.
- the resistance component 16 on the path of the hole flow 17 in the p-type counter layer is particularly a pn junction.
- the resistance component along the line becomes smaller. Therefore, since the hole passes through the portion having the lowest resistance, it flows out to the emitter electrode through the shortest path.
- a conventional MOS gate only the p-type contact layer 6 is present, and its concentration is lower than that of the present invention.
- the n-type source layer 5 has a convex shape toward the inside of the p-type contact layer 6 as shown in FIG. Therefore, the hole flow 17 of the p-type contact layer 6 is narrowed by the n-type source layers 5 on both sides, and the size of the resistance component 16 increases accordingly.
- the voltage drop due to the hole flow 17 is sufficiently smaller than the built-in potential of the pn junction due to the n-type source layer 5 and the p-type counter layer 7, and latch-up Occurrence can be suppressed.
- the pattern defects (1) to (3) can be prevented.
- the semiconductor device and the manufacturing method thereof according to the present invention are useful for the semiconductor device and the manufacturing method thereof in which switching breakdown due to process defects is reduced, and in particular, the semiconductor device such as an insulated gate semiconductor device. And suitable for its manufacturing method.
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Abstract
Description
(1)p型コンタクト層が形成されている箇所に不要なn型ソース層が入ったことによる不良(以下、パターン不良(1)と呼ぶ)。
(2)n型ソース層が元々入らない箇所においてp型コンタクト層が欠落したことによる不良(以下、パターン不良(2)と呼ぶ)。
(3)パターン不良(1)と(2)が同時に生じたことによる不良(以下、パターン不良(3)と呼ぶ)。
以下に、上記パターン不良(1)~(3)に示したそれぞれのパターン不良について説明する。
図28は、従来の半導体装置の製造方法を示す断面図である。図28においては、素子の形成途中の各工程における素子の断面を示している。図28(a)は、ゲート酸化膜10とゲート制御用のポリシリコン電極11およびp型ベース層64が、n型ドリフト層61の表面に形成された状態を示している。図28(a)に示した状態においては、ゲート酸化膜10と同じ程度の厚さのスクリーン熱酸化膜(図示を省略する)が、p型ベース層64の表面に形成されていてもよい。
図29は、従来の半導体装置の製造方法を示す断面図である。図29においては、素子の形成途中の各工程における素子の断面を示している。図29(a)は、ゲート酸化膜10とゲート制御用のポリシリコン電極11およびp型ベース層64が、n型ドリフト層61の表面に形成された状態を示している。
図30は、従来の半導体装置の製造方法を示す断面図である。図30においては、素子の形成途中の各工程における素子の断面を示している。図30に示すように、パターン不良(1)とパターン不良(2)とが同時に生じる場合、図30(a)の紙面左側のp型ベース層64では、レジスト8が欠落し、開口部全面に渡り、本来形成されるべきでない余計なn型ソース層65が形成される。
実施の形態1においては、p型ベース層の表面に形成されるp型コンタクト層のパターン不良を抑えてラッチアップを防止するために、新たにp型カウンター層を形成するMOSゲート型の半導体装置およびその製造方法について、説明する。
まず、前述のパターン不良(1)、p型コンタクト層6が形成されているかあるいはされた箇所に、不要なn型ソース層5が形成された場合について、図3を用いて説明する。図3は、本発明の実施の形態にかかる半導体装置の製造方法を示す断面図である。図3(a)から図3(d)は、実施の形態1の製造方法において、このパターン不良(2)が生じたときの工程推移を示した断面図である。ここで、工程推移(フロー)の図3(a)から図3(d)は、前述の図2と同じであるので、相違点のみに絞って説明する。
次に、前述のパターン不良(2)、n型ソース層が元々入らない箇所において、p型コンタクト層6が欠落した場合について、図4を用いて説明する。図4は、本発明の実施の形態にかかる半導体装置の製造方法を示す断面図である。図4(a)から図4(d)は、実施の形態1の製造方法において、このパターン不良(2)が生じたときの工程推移を示している。
次に、上述のパターン不良(3)、つまりパターン不良(1)と(2)が、局所的に同時に生じる場合について、図5を用いて説明する。図5は、本発明の実施の形態にかかる半導体装置の製造方法を示す断面図である。このパターン不良(3)は、上記のパターン不良(1)、(2)と比べると、発生頻度は極めて低くなるものの、十分起こりうる不良である。図5(a)から図5(d)は、実施の形態1の製造方法において、このパターン不良(3)が生じたときの工程推移を示した断面図である。
次に、図9を用いて、本発明の実施の形態2について説明する。図9は、本発明の実施の形態にかかる半導体装置の要部断面図とネットドーピング濃度を示す濃度分布図である。図9(a)においては本発明の半導体装置の実施の形態2を示すIGBTの断面図を示しており、図9(b)においては図9(a)の内部に記載した切断線A1-A2およびB1-B2に沿ったネットドーピング濃度分布を示している。図9(b)内の実線は切断線A1-A2に沿った濃度分布を示し、破線は同B1-B2に沿った濃度分布を示している。
次に、図10を用いて、本発明の実施の形態3について説明する。図10は、本発明の実施の形態にかかる半導体装置の要部断面図とネットドーピング濃度を示す濃度分布図である。図10(a)においては本発明の実施の形態3にかかるIGBTの断面図を示しており、図10(b)においては図10(a)の内部に記載した切断線A1-A2およびB1-B2に沿ったネットドーピング濃度分布を示している。図10(b)内の実線は切断線A1-A2に沿った濃度分布を示し、図10(b)内の破線は同B1-B2に沿った濃度分布を示している。
次に、図12を用いて、本発明の実施の形態4について説明する。図12は、本発明の実施の形態にかかる半導体装置の要部断面図とネットドーピング濃度を示す濃度分布図である。図12(a)においては本発明の実施の形態4にかかるIGBTの断面図を示しており、図12(b)においては図12(a)の内部に記載した切断線A1-A2およびB1-B2に沿ったネットドーピング濃度分布を示している。図12(b)内の実線は切断線A1-A2に沿った濃度分布を示し、図12(b)内の破線は同B1-B2に沿った濃度分布である。
次に、図13を用いて、本発明の実施の形態5のIGBTの構造について説明する。図13は、本発明の実施の形態にかかる半導体装置の要部断面図である。図13においては、本発明の実施の形態5にかかるIGBTの断面図を示している。実施の形態5の特徴は、実施の形態1に対する相違点として、p型カウンター層7を層間絶縁膜9のコンタクト開口部14に自己整合となるように形成したことである。
次に、図15を用いて、本発明の実施の形態6のIGBTの構造について説明する。図15は、本発明の実施の形態にかかる半導体装置の要部断面図とネットドーピング濃度を示す濃度分布図である。図15(a)においては本発明の実施の形態6にかかるIGBTの断面図を示しており、図15(b)においては図15(a)の内部に記載した切断線A1-A2およびB1-B2に沿ったネットドーピング濃度分布を示している。図15(b)内の実線は切断線A1-A2に沿った濃度分布を示し、図15(b)内の破線は同B1-B2に沿った濃度分布である。
次に、図16を用いて、本発明の実施の形態7のIGBTの構造について説明する。図16は、本発明の実施の形態にかかる半導体装置の要部断面図である。図16においては、本発明の実施の形態7にかかるIGBTの断面図を示している。
次に、図18を用いて、本発明の実施の形態8のIGBTの構造について説明する。図18は、本発明の実施の形態にかかる半導体装置の要部断面図である。図18においては、本発明の実施の形態8にかかるIGBTの断面図を示している。
次に、図20を用いて、本発明の実施の形態9のIGBTの構造について説明する。図20は、本発明の実施の形態にかかる半導体装置の要部断面図である。図20においては、本発明の実施の形態9にかかるIGBTの断面図を示している。図20に示すように、本発明の実施の形態9の特徴は、実施の形態8に対する相違点として、p型カウンター層7を層間絶縁膜9のコンタクト開口部14に自己整合となるように形成したことである。
次に、図23を用いて、本発明の実施の形態10のMOSFETの構造について説明する。図23は、本発明の実施の形態にかかる半導体装置の要部断面図である。図23においては、本発明の実施の形態10にかかるMOSFETを示した断面図を示している。
次に、図24を用いて、本発明の実施の形態11のMOSゲート構造について説明する。図24は、本発明の実施の形態にかかる半導体装置と従来の半導体装置の動作を説明した断面図である。図24においては、本発明の実施の形態11にかかるMOSゲート構造および従来の構造を示した断面図を示している。図24(a)においては本発明の実施の形態11のMOSゲート構造の断面図を示しており、図24(b)においてはさらに任意の1つのp型ベース層4の断面を拡大した断面図を示しており、図24(c)においてはさらにn型ソース層5とp型カウンター層7のpn接合近傍を拡大した断面図を示しており、図24(d)においては従来の半導体装置のMOSゲート構造の断面図を示している。
2 n型フィールドストップ層
3 p型コレクタ層
4,64 p型ベース層
5,65 n型ソース層
6,66 p型コンタクト層
7,7a,7b,7c p型カウンター層
8 レジスト
9 層間絶縁膜
10 ゲート酸化膜
11 ポリシリコン電極
12,72 エミッタ電極
13 コレクタ電極
14 コンタクト開口部
16 抵抗成分
17 ホールの流れ
18 ボロンイオン注入
19 砒素イオン注入
21 n型ドレイン層
23 ドレイン電極
24 ソース電極
26 pウェル層
28 p型高濃度層
Claims (14)
- 第1導電型の半導体基体からなるドリフト層と、
前記半導体基体の第一の主面の表面に選択的に形成された第2導電型のベース層と、
前記ベース層の表面に選択的に形成された第1導電型のソース層と、
前記ベース層の前記第一の主面側にて前記ソース層と接するように形成され、前記ベース層よりも高濃度である第2導電型のコンタクト層と、
絶縁膜を介して前記ドリフト層と前記ベース層および前記ソース層と対峙するように形成されたゲート電極と、
前記ソース層と電気的に接続されるように前記第一の主面上に形成されたエミッタ電極と、
前記ゲート電極と前記エミッタ電極の間に挟まれ、前記ゲート電極と前記エミッタ電極を絶縁するように前記半導体基体の第一の主面上に形成された層間絶縁膜と、を有する半導体装置において、
前記ソース層に接するとともに前記コンタクト層に重なっており、且つ前記ベース層よりも浅くて高濃度に形成された第2導電型のカウンター層を有し、該カウンター層の単位面積あたりのドーピング総量が、前記コンタクト層の単位面積あたりのドーピング総量の10%よりも大きいことを特徴とする半導体装置。 - 前記カウンター層の単位面積あたりのドーピング総量が、前記コンタクト層の単位面積あたりのドーピング総量よりも大きいことを特徴とする請求項1に記載の半導体装置。
- 前記カウンター層と前記コンタクト層の単位面積あたりのドーピング総量の合計値が、前記ソース層の単位面積あたりのドーピング総量よりも大きいことを特徴とする請求項1または2に記載の半導体装置。
- 前記カウンター層の単位面積あたりのドーピング総量が、前記ソース層の単位面積あたりのドーピング総量よりも大きいことを特徴とする請求項3に記載の半導体装置。
- 前記カウンター層が前記層間絶縁膜の開口部の位置に対して自己整合となるように形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記カウンター層が複数設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置がIGBTであることを特徴とする請求項1に記載の半導体装置。
- 前記半導体装置がトレンチゲート型IGBTであることを特徴とする請求項1に記載の半導体装置。
- 前記カウンター層と前記ソース層のpn接合の断面形状が、前記ソース層の内部に向って凸状の部分を有することを特徴とする請求項1に記載の半導体装置。
- 請求項1に記載の半導体装置の製造方法において、
前記半導体装置が備えるコンタクト層の形成のために、前記コンタクト層が前記半導体装置が備えるベース層よりも浅くなるような飛程にて、第2導電型を示すドーパントを前記半導体装置が備える半導体基体の第一の主面にイオン注入する第一の工程と、
前記第一の工程よりも後に、前記半導体装置が備えるソース層の形成のために、前記ソース層が前記コンタクト層よりも浅くなるような飛程にて、第1導電型を示すドーパントを前記第一の主面にイオン注入する第二の工程と、
前記第二の工程よりも後に、前記半導体装置が備えるカウンター層の形成のために、前記ソース層よりも深く且つ前記ベース層よりも浅くなるような飛程であり、且つ前記第一の工程のイオン注入のドーズ量の10%以上のドーズ量にて、第2導電型を示すドーパントを前記第一の主面にイオン注入する第三の工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第三の工程のイオン注入のドーズ量が、前記第一の工程のイオン注入のドーズ量よりも大きいことを特徴とする請求項10に記載の半導体装置の製造方法。
- 前記第一の工程におけるイオン注入のドーズ量と、前記第三の工程におけるイオン注入のドーズ量との合計は、前記第二の工程におけるイオン注入のドーズ量よりも大きいことを特徴とする請求項10または11に記載の半導体装置の製造方法。
- 前記第三の工程のイオン注入のドーズ量が、前記第二の工程のイオン注入のドーズ量よりも大きいことを特徴とする請求項12に記載の半導体装置の製造方法。
- 前記第三の工程のイオン注入が、選択的に開口部が形成された前記層間絶縁膜をマスクとして行われることを特徴とする請求項10に記載の半導体装置の製造方法。
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US10629685B2 (en) | 2016-09-14 | 2020-04-21 | Fuji Electric Co., Ltd. | RC-IGBT and manufacturing method thereof |
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Also Published As
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US9461140B2 (en) | 2016-10-04 |
JP5708788B2 (ja) | 2015-04-30 |
JP2015039030A (ja) | 2015-02-26 |
US20130082301A1 (en) | 2013-04-04 |
JPWO2012124784A1 (ja) | 2014-07-24 |
US9082812B2 (en) | 2015-07-14 |
US20150333146A1 (en) | 2015-11-19 |
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