JP2009277839A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2009277839A JP2009277839A JP2008126894A JP2008126894A JP2009277839A JP 2009277839 A JP2009277839 A JP 2009277839A JP 2008126894 A JP2008126894 A JP 2008126894A JP 2008126894 A JP2008126894 A JP 2008126894A JP 2009277839 A JP2009277839 A JP 2009277839A
- Authority
- JP
- Japan
- Prior art keywords
- region
- concentration
- type well
- well region
- implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000000034 method Methods 0.000 title claims description 17
- 238000002513 implantation Methods 0.000 claims abstract description 80
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 35
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 46
- 239000012535 impurity Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 abstract description 31
- 230000015556 catabolic process Effects 0.000 abstract description 19
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000003892 spreading Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】幅Lpの開口部を有する第1注入マスク4を利用してイオン注入を行うことで、高濃度p型ウエル領域6を形成する。次に、幅Lpよりも大きな幅Ln(望ましくは領域6のイオンの横方向の拡がり範囲の2倍値を幅Lpに加えた値)の開口部を有する第2注入マスク8を用いたイオン注入を行うことで、n型ソース領域7を形成する。その上で、マスク10を用いたイオン注入により、n型ソース領域7の端部周辺部でありチャネルとなる領域2内に低濃度p型ウエル領域9を形成する。
【選択図】図1
Description
図1は、本実施の形態に係る炭化珪素を用いたMOSFETの製造方法を示す縦断面図である。尚、説明の簡単化のために、図1は、単位セルの作製方法を示す。
図5は、本実施の形態に係るMOSFETの製造方法を示す縦断面図である。ここでは説明を簡単にするため、単位セルの作製方法を示す。尚、図5中、図1と同一又は対応する構成要素には同一の参照符号が付されている。
尚、n型を第1導電型と定義するときには、p型が第2導電型となり、逆にp型を第1導電型と定義するときには、n型が第2導電型となる。
Claims (3)
- 第1導電型の炭化珪素基板の主表面上に第一の幅で開口されて形成された第1注入マスクを介して第2導電型のイオンを注入することにより、前記炭化珪素基板の内部に高濃度第2導電型ウエル領域を形成する第1工程と、
前記炭化珪素基板の前記主表面上に前記第1注入マスクの開口部よりも大きな全体幅を有して形成された第2注入マスクを介して第1導電型のイオンを注入することにより、前記炭化珪素基板の前記高濃度第2導電型ウエル領域の前記主表面側に第1導電型半導体領域を形成する第2工程と、
前記炭化珪素基板の前記主表面上に形成された第3注入マスクを介して第2導電型のイオンを注入することにより、前記第1導電型半導体領域の断面横方向の周囲に前記第1導電型半導体領域に接する、前記高濃度第2導電型ウエル領域より第2導電型不純物濃度が低い、低濃度第2導電型ウエル領域を形成する第3工程とを備えたことを特徴とする、
半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法であって、
前記第1工程は、
前記第1注入マスクを介して第2導電型のイオンを注入することにより、前記高濃度第2導電型ウエル領域と前記炭化珪素基板の前記主表面とを結ぶ第2導電型コンタクト領域を形成する工程を含むことを特徴とする、
半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法であって、
前記第2工程に於ける前記第2注入マスクの一部は、前記第2導電型コンタクト領域の上面を被覆していることを特徴とする、
半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008126894A JP5213520B2 (ja) | 2008-05-14 | 2008-05-14 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008126894A JP5213520B2 (ja) | 2008-05-14 | 2008-05-14 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009277839A true JP2009277839A (ja) | 2009-11-26 |
JP5213520B2 JP5213520B2 (ja) | 2013-06-19 |
Family
ID=41443005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008126894A Active JP5213520B2 (ja) | 2008-05-14 | 2008-05-14 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5213520B2 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011165856A (ja) * | 2010-02-09 | 2011-08-25 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
WO2012124784A1 (ja) * | 2011-03-16 | 2012-09-20 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US8653535B2 (en) | 2010-09-06 | 2014-02-18 | Panasonic Corporation | Silicon carbide semiconductor device having a contact region that includes a first region and a second region, and process for production thereof |
US9142612B2 (en) | 2013-03-22 | 2015-09-22 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
JP2020107703A (ja) * | 2018-12-27 | 2020-07-09 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP7424428B2 (ja) | 2017-06-07 | 2024-01-30 | 富士電機株式会社 | 半導体装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5936970A (ja) * | 1982-07-08 | 1984-02-29 | ゼネラル・エレクトリツク・カンパニイ | 半導体素子製造法 |
JP2000082812A (ja) * | 1998-06-22 | 2000-03-21 | Denso Corp | 炭化珪素半導体装置及びその製造方法 |
JP2000277734A (ja) * | 1999-03-29 | 2000-10-06 | Sharp Corp | 絶縁ゲート型半導体装置及びその製造方法 |
JP2001512291A (ja) * | 1997-07-31 | 2001-08-21 | シーメンス アクチエンゲゼルシヤフト | 高い精度、良好な均一性及び再現性を有する半導体装置の製造方法 |
JP2007173379A (ja) * | 2005-12-20 | 2007-07-05 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP2009054765A (ja) * | 2007-08-27 | 2009-03-12 | Mitsubishi Electric Corp | 炭化珪素半導体装置およびその製造方法 |
-
2008
- 2008-05-14 JP JP2008126894A patent/JP5213520B2/ja active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5936970A (ja) * | 1982-07-08 | 1984-02-29 | ゼネラル・エレクトリツク・カンパニイ | 半導体素子製造法 |
JP2001512291A (ja) * | 1997-07-31 | 2001-08-21 | シーメンス アクチエンゲゼルシヤフト | 高い精度、良好な均一性及び再現性を有する半導体装置の製造方法 |
JP2000082812A (ja) * | 1998-06-22 | 2000-03-21 | Denso Corp | 炭化珪素半導体装置及びその製造方法 |
JP2000277734A (ja) * | 1999-03-29 | 2000-10-06 | Sharp Corp | 絶縁ゲート型半導体装置及びその製造方法 |
JP2007173379A (ja) * | 2005-12-20 | 2007-07-05 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP2009054765A (ja) * | 2007-08-27 | 2009-03-12 | Mitsubishi Electric Corp | 炭化珪素半導体装置およびその製造方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011165856A (ja) * | 2010-02-09 | 2011-08-25 | Mitsubishi Electric Corp | 炭化珪素半導体装置の製造方法 |
US8653535B2 (en) | 2010-09-06 | 2014-02-18 | Panasonic Corporation | Silicon carbide semiconductor device having a contact region that includes a first region and a second region, and process for production thereof |
WO2012124784A1 (ja) * | 2011-03-16 | 2012-09-20 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP5708788B2 (ja) * | 2011-03-16 | 2015-04-30 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US9082812B2 (en) | 2011-03-16 | 2015-07-14 | Fuji Electric Co., Ltd. | Semiconductor device including a counter layer, for power conversion and method of manufacturing the same |
US9461140B2 (en) | 2011-03-16 | 2016-10-04 | Fuji Electric Co., Ltd. | Semiconductor device manufacturing method including a counter layer for power conversion |
US9142612B2 (en) | 2013-03-22 | 2015-09-22 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
JP7424428B2 (ja) | 2017-06-07 | 2024-01-30 | 富士電機株式会社 | 半導体装置 |
JP2020107703A (ja) * | 2018-12-27 | 2020-07-09 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP7275573B2 (ja) | 2018-12-27 | 2023-05-18 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5213520B2 (ja) | 2013-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6266975B2 (ja) | 絶縁ゲート型半導体装置の製造方法及び絶縁ゲート型半導体装置 | |
JP2007123887A (ja) | レトログレード領域を備える横型dmosトランジスタ及びその製造方法 | |
KR20120035699A (ko) | 급경사 접합 프로파일을 갖는 소스/드레인 영역들을 구비하는 반도체 소자 및 그 제조방법 | |
WO2014013618A1 (ja) | 半導体装置及びその製造方法 | |
JP5213520B2 (ja) | 半導体装置の製造方法 | |
JP2010135800A (ja) | 半導体素子及びその製造方法 | |
JP2013125763A (ja) | スイッチング素子とその製造方法 | |
JP2007184434A (ja) | 半導体装置および半導体装置の製造方法 | |
US9331194B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
JP2007088334A (ja) | 半導体装置およびその製造方法 | |
JP2006287127A (ja) | 半導体装置およびその製造方法 | |
US8928045B2 (en) | Semiconductor device | |
JP2007227747A (ja) | 半導体装置及びその製造方法 | |
JP2010118622A (ja) | 半導体装置及びその製造方法 | |
JP2009043923A (ja) | 半導体装置及びその製造方法 | |
JP4676708B2 (ja) | 半導体装置の製造方法 | |
JP2008124362A (ja) | 半導体装置とその製造方法 | |
JP2005175297A (ja) | 半導体装置 | |
CN108133894B (zh) | 沟槽型垂直双扩散金属氧化物晶体管及其制作方法 | |
JP2006332232A (ja) | 半導体装置およびその製造方法 | |
JP2009194292A (ja) | 半導体装置及びその製造方法 | |
JP2010219109A (ja) | トレンチゲート型半導体装置とその製造方法 | |
CN108155239B (zh) | 垂直双扩散金属氧化物晶体管及其制作方法 | |
JP2007103564A (ja) | 半導体装置 | |
JP2011210905A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100121 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120905 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120911 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121109 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130129 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130226 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5213520 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160308 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |