JP6266975B2 - 絶縁ゲート型半導体装置の製造方法及び絶縁ゲート型半導体装置 - Google Patents
絶縁ゲート型半導体装置の製造方法及び絶縁ゲート型半導体装置 Download PDFInfo
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- JP6266975B2 JP6266975B2 JP2013269264A JP2013269264A JP6266975B2 JP 6266975 B2 JP6266975 B2 JP 6266975B2 JP 2013269264 A JP2013269264 A JP 2013269264A JP 2013269264 A JP2013269264 A JP 2013269264A JP 6266975 B2 JP6266975 B2 JP 6266975B2
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- 239000004065 semiconductor Substances 0.000 title claims description 119
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 230000002093 peripheral effect Effects 0.000 claims description 121
- 239000012535 impurity Substances 0.000 claims description 81
- 239000000758 substrate Substances 0.000 claims description 71
- 238000009792 diffusion process Methods 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 27
- 229910052796 boron Inorganic materials 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 210000000746 body region Anatomy 0.000 description 16
- 230000015556 catabolic process Effects 0.000 description 15
- 238000002513 implantation Methods 0.000 description 13
- 238000000137 annealing Methods 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 8
- 230000004913 activation Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
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Description
次に、図6に示すように、半導体基板12に向けてAl(アルミニウム)を照射する。照射されたAlは、ゲートトレンチ34の底面の保護膜66を貫通して、ゲートトレンチ34の底面に注入される。また、保護膜66によって、ゲートトレンチ34の側面にAlが注入されることが防止される。したがって、Alは、ゲートトレンチ34の底面にのみ注入される。その後、マスク60と保護膜66を除去する。
次に、図9に示すように、半導体基板12に向けてB(ボロン)を照射する。照射されたBは、外周トレンチ54の底面の保護膜67を貫通して、外周トレンチ54の底面に注入される。また、保護膜67によって、外周トレンチ54の側面にBが注入されることが防止される。したがって、Bは、外周トレンチ54の底面にのみ注入される。その後、マスク61と保護膜67を除去する。
次に、1600℃以上の温度で半導体基板12をアニールする。これによって、半導体基板12に注入されたAlとBを活性化させる。これによって、図10に示すように、ゲートトレンチ34の底面の周囲にp型フローティング領域32を形成するとともに、外周トレンチ54の底面の周囲に底面領域56を形成する。ここで、半導体基板12(すなわち、SiC)の中においては、Bの拡散係数はAlの拡散係数よりも遥かに大きい。このため、活性化アニール工程においては、Bの拡散距離がAlの拡散距離よりも大きくなる。このため、図10に示すように、底面領域56(すなわち、Bの拡散範囲)のサイズが、p型フローティング領域32(すなわち、Alの拡散範囲)のサイズよりも大きくなる。したがって、底面領域56の幅W1がp型フローティング領域32の幅W2よりも広くなり、2つの底面領域56の間の間隔W3が2つのp型フローティング領域32の間の間隔W4よりも狭くなる。その後、必要な構造(図1に示すトレンチゲート構造、絶縁層16、表面電極14、ドレイン領域30及び裏面電極18)を形成することで、図1に示す半導体装置10が完成する。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
12:半導体基板
14:表面電極
16:絶縁層
18:裏面電極
20:セル領域
22:ソース領域
24:ボディコンタクト領域
26:ボディ領域
28:ドリフト領域
30:ドレイン領域
32:p型フローティング領域
34:ゲートトレンチ
34a:ボトム絶縁層
34b:ゲート絶縁膜
34c:ゲート電極
34d:絶縁層
50:外周領域
51:表面領域
53:絶縁層
54:外周トレンチ
56:底面領域
Claims (9)
- 半導体基板と、前記半導体基板の表面に形成されている表面電極と、前記半導体基板の裏面に形成されている裏面電極を有し、前記表面電極と前記裏面電極の間をスイッチングする絶縁ゲート型半導体装置を製造する方法であって、
前記絶縁ゲート型半導体装置が、
前記表面電極に接続されている第1導電型の第1領域と、
前記第1領域に接している第2導電型の第2領域と、
前記第2領域によって前記第1領域から分離されている第1導電型の第3領域と、
前記半導体基板の前記表面に形成されており、前記第2領域を貫通して前記第3領域に達する複数のゲートトレンチと、
前記ゲートトレンチ内に配置されているゲート絶縁膜及びゲート電極と、
前記ゲートトレンチの底面に露出する範囲に形成されている第2導電型の第4領域と、
前記第2領域の外側の領域において前記半導体基板の前記表面に形成されている複数の外周トレンチと、
前記外周トレンチ内に配置されている絶縁層と、
前記外周トレンチの底面に露出する範囲に形成されている第2導電型の第5領域、
を有し、
前記方法が、
前記ゲートトレンチを形成する工程と、
前記外周トレンチを形成する工程と、
前記ゲートトレンチの底面に第1の第2導電型不純物を注入し、注入した前記第1の第2導電型不純物を拡散させることで前記第4領域を形成する工程と、
前記外周トレンチの底面に第2の第2導電型不純物を注入し、注入した前記第2の第2導電型不純物を拡散させることで前記第5領域を形成する工程、
を有し、
前記第5領域を形成する工程における前記第2の第2導電型不純物の拡散係数が、前記第4領域を形成する工程における前記第1の第2導電型不純物の拡散係数よりも大きく、
前記第1の第2導電型不純物と前記第2の第2導電型不純物がボロンであり、
前記第4領域を形成する前記工程では、前記ゲートトレンチの底面にボロンとカーボンを注入する、
方法。 - 半導体基板と、前記半導体基板の表面に形成されている表面電極と、前記半導体基板の裏面に形成されている裏面電極を有し、前記表面電極と前記裏面電極の間をスイッチングする絶縁ゲート型半導体装置を製造する方法であって、
前記絶縁ゲート型半導体装置が、
前記表面電極に接続されている第1導電型の第1領域と、
前記第1領域に接している第2導電型の第2領域と、
前記第2領域によって前記第1領域から分離されている第1導電型の第3領域と、
前記半導体基板の前記表面に形成されており、前記第2領域を貫通して前記第3領域に達する複数のゲートトレンチと、
前記ゲートトレンチ内に配置されているゲート絶縁膜及びゲート電極と、
前記ゲートトレンチの底面に露出する範囲に形成されている第2導電型の第4領域と、
前記第2領域の外側の領域において前記半導体基板の前記表面に形成されている複数の外周トレンチと、
前記外周トレンチ内に配置されている絶縁層と、
前記外周トレンチの底面に露出する範囲に形成されている第2導電型の第5領域、
を有し、
前記方法が、
前記ゲートトレンチを形成する工程と、
前記外周トレンチを形成する工程と、
前記ゲートトレンチの底面に第1の第2導電型不純物を注入し、注入した前記第1の第2導電型不純物を拡散させることで前記第4領域を形成する工程と、
前記外周トレンチの底面に第2の第2導電型不純物を注入し、注入した前記第2の第2導電型不純物を拡散させることで前記第5領域を形成する工程、
を有し、
前記第5領域を形成する工程における前記第2の第2導電型不純物の拡散係数が、前記第4領域を形成する工程における前記第1の第2導電型不純物の拡散係数よりも大きく、
前記第5領域を形成する前記工程では、前記外周トレンチの底面に、前記第2の第2導電型不純物と、前記第2の第2導電型不純物よりも前記第5領域を形成する工程における拡散係数が小さい第3の第2導電型不純物を注入する、
方法。 - 前記第5領域を形成する前記工程では、前記外周トレンチの底面を構成する半導体層の少なくとも一部がアモルファス化する濃度で前記第2の第2導電型不純物を注入する、請求項1または2の方法。
- 前記第5領域を形成する前記工程では、前記外周トレンチの底面に1×1018atoms/cm3以上の濃度で前記第2の第2導電型不純物を注入する、請求項1〜3のいずれか一項の方法。
- 前記各第5領域の間の間隔が、前記各第4領域の間の間隔の1/2未満である請求項1〜4のいずれか一項の方法。
- 半導体基板と、前記半導体基板の表面に形成されている表面電極と、前記半導体基板の裏面に形成されている裏面電極を有し、前記表面電極と前記裏面電極の間をスイッチングする絶縁ゲート型半導体装置であって、
前記表面電極に接続されている第1導電型の第1領域と、
前記第1領域に接している第2導電型の第2領域と、
前記第2領域によって前記第1領域から分離されている第1導電型の第3領域と、
前記半導体基板の前記表面に形成されており、前記第1領域と前記第2領域を貫通して前記第3領域に達する複数のゲートトレンチと、
前記ゲートトレンチ内に配置されているゲート絶縁膜及びゲート電極と、
前記ゲートトレンチの底面に露出する範囲に形成されている第2導電型の第4領域と、
前記第2領域と接しない位置において前記半導体基板の前記表面に形成されている複数の外周トレンチと、
前記外周トレンチ内に配置されている絶縁層と、
前記外周トレンチの底面に露出する範囲に形成されている第2導電型の第5領域、
を有し、
前記第5領域の幅が、前記第4領域の幅よりも広く、
前記第4領域に、第1の第2導電型不純物が含まれ、
前記第5領域に、第2の第2導電型不純物と、前記第2の第2導電型不純物よりも前記半導体基板内における拡散係数が小さい第3の第2導電型不純物が含まれ、
前記第1の第2導電型不純物の前記半導体基板内における拡散係数が、前記第2の第2導電型不純物の前記半導体基板内における拡散係数よりも小さい、
絶縁ゲート型半導体装置。 - 前記外周トレンチの底面の少なくとも一部がアモルファス層である請求項6の絶縁ゲート型半導体装置。
- 前記外周トレンチの底面の少なくとも一部が、1×1018atoms/cm3以上の濃度で第2導電型不純物を含有する請求項6または7の絶縁ゲート型半導体装置。
- 前記各第5領域の間の間隔が、前記各第4領域の間の間隔の1/2未満である請求項6〜8のいずれか一項の絶縁ゲート型半導体装置。
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