JP5213520B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5213520B2 JP5213520B2 JP2008126894A JP2008126894A JP5213520B2 JP 5213520 B2 JP5213520 B2 JP 5213520B2 JP 2008126894 A JP2008126894 A JP 2008126894A JP 2008126894 A JP2008126894 A JP 2008126894A JP 5213520 B2 JP5213520 B2 JP 5213520B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000002513 implantation Methods 0.000 claims description 83
- 239000000758 substrate Substances 0.000 claims description 55
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 43
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 description 27
- 230000015556 catabolic process Effects 0.000 description 18
- 239000010410 layer Substances 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
図1は、本実施の形態に係る炭化珪素を用いたMOSFETの製造方法を示す縦断面図である。尚、説明の簡単化のために、図1は、単位セルの作製方法を示す。
図5は、本実施の形態に係るMOSFETの製造方法を示す縦断面図である。ここでは説明を簡単にするため、単位セルの作製方法を示す。尚、図5中、図1と同一又は対応する構成要素には同一の参照符号が付されている。
尚、n型を第1導電型と定義するときには、p型が第2導電型となり、逆にp型を第1導電型と定義するときには、n型が第2導電型となる。
Claims (4)
- 第1導電型の炭化珪素基板の主表面上に第一の幅で開口されて形成された第1注入マスクを介して第2導電型のイオンを注入することにより、前記炭化珪素基板の内部に高濃度第2導電型ウエル領域を形成する第1工程を備え、
前記第1工程において、前記炭化珪素基板の前記主表面と前記高濃度第2導電型ウエル領域の上面との間に前記第1導電型の領域が残るように前記高濃度第2導電型ウエル領域を形成し、
前記炭化珪素基板の前記主表面上に前記第1注入マスクの開口部よりも大きな全体幅を有して形成された第2注入マスクを介して第1導電型のイオンを注入することにより、前記炭化珪素基板の前記高濃度第2導電型ウエル領域の前記主表面側に残った前記第1導電型の領域に電極領域となる第1導電型半導体領域を形成する第2工程と、
前記炭化珪素基板の前記主表面上に形成された第3注入マスクを介して第2導電型のイオンを注入することにより、前記第1導電型半導体領域の断面横方向の周囲に前記第1導電型半導体領域に接する、前記高濃度第2導電型ウエル領域より第2導電型不純物濃度が低い、低濃度第2導電型ウエル領域を形成する第3工程とを備えたことを特徴とする、
半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法であって、
前記第1工程は、
前記第1注入マスクを介して第2導電型のイオンを注入することにより、前記高濃度第2導電型ウエル領域と前記炭化珪素基板の前記主表面とを結ぶ第2導電型コンタクト領域を形成する工程を含むことを特徴とする、
半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法であって、
前記第2工程に於ける前記第2注入マスクの前記全体幅の中の各開口部の幅は、前記第1工程に於いて形成された前記高濃度第2導電型ウエル領域の幅よりも小さいことを特徴とする、
半導体装置の製造方法。 - 第1導電型の炭化珪素基板の主表面上に第一の幅で開口されて形成された第1注入マスクを介して第2導電型のイオンを注入することにより、前記炭化珪素基板の内部に高濃度第2導電型ウエル領域を形成する第1工程と、
前記炭化珪素基板の前記主表面上に前記第1注入マスクの開口部よりも大きな全体幅を有して形成された第2注入マスクを介して第1導電型のイオンを注入することにより、前記炭化珪素基板の前記高濃度第2導電型ウエル領域の前記主表面側に第1導電型半導体領域を形成する第2工程と、
前記炭化珪素基板の前記主表面上に形成された第3注入マスクを介して第2導電型のイオンを注入することにより、前記第1導電型半導体領域の断面横方向の周囲に前記第1導電型半導体領域に接する、前記高濃度第2導電型ウエル領域より第2導電型不純物濃度が低い、低濃度第2導電型ウエル領域を形成する第3工程とを備え、
前記第1工程は、前記第1注入マスクを介して第2導電型のイオンを注入することにより、前記高濃度第2導電型ウエル領域と前記炭化珪素基板の前記主表面とを結ぶ第2導電型コンタクト領域を形成する工程を含み、
前記第2工程に於ける前記第2注入マスクの一部は、前記第2導電型コンタクト領域の上面を被覆していることを特徴とする、
半導体装置の製造方法。
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JP5601849B2 (ja) * | 2010-02-09 | 2014-10-08 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
US8653535B2 (en) | 2010-09-06 | 2014-02-18 | Panasonic Corporation | Silicon carbide semiconductor device having a contact region that includes a first region and a second region, and process for production thereof |
JP5708788B2 (ja) | 2011-03-16 | 2015-04-30 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP5802231B2 (ja) | 2013-03-22 | 2015-10-28 | 株式会社東芝 | 半導体装置及びその製造方法 |
US10468509B2 (en) | 2017-06-07 | 2019-11-05 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
JP7275573B2 (ja) * | 2018-12-27 | 2023-05-18 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
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DE3322669C2 (de) * | 1982-07-08 | 1986-04-24 | General Electric Co., Schenectady, N.Y. | Verfahren zum Herstellen einer Halbleitervorrichtung mit isolierten Gateelektroden |
DE19832329A1 (de) * | 1997-07-31 | 1999-02-04 | Siemens Ag | Verfahren zur Strukturierung von Halbleitern mit hoher Präzision, guter Homogenität und Reproduzierbarkeit |
JP4123636B2 (ja) * | 1998-06-22 | 2008-07-23 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
JP3485491B2 (ja) * | 1999-03-29 | 2004-01-13 | シャープ株式会社 | 絶縁ゲート型半導体装置及びその製造方法 |
JP2007173379A (ja) * | 2005-12-20 | 2007-07-05 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP5119806B2 (ja) * | 2007-08-27 | 2013-01-16 | 三菱電機株式会社 | 炭化珪素半導体装置およびその製造方法 |
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