TWI781289B - 製造高電壓半導體裝置的方法 - Google Patents

製造高電壓半導體裝置的方法 Download PDF

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TWI781289B
TWI781289B TW108104950A TW108104950A TWI781289B TW I781289 B TWI781289 B TW I781289B TW 108104950 A TW108104950 A TW 108104950A TW 108104950 A TW108104950 A TW 108104950A TW I781289 B TWI781289 B TW I781289B
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pattern
region
conductivity type
barrier
barrier pattern
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TW202001990A (zh
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朴淳烈
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南韓商Ｓｋ海力士系統集成電路有限公司
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Abstract

一種方法包括：在緩衝絕緣層上形成阻擋圖案，所述緩衝絕緣層設置在第二導電類型的半導體區域中的第一區域上方；在緩衝絕緣層上方形成具有開口的離子植入遮罩圖案，以通過離子植入遮罩圖案的開口暴露出阻擋圖案，以及使用離子植入遮罩圖案，將用於形成第一導電類型的主體區的第一導電類型的雜質離子植入到第一區域中。

Description

製造高電壓半導體裝置的方法
本公開的各種實施例涉及高電壓半導體裝置，以及更具體地，涉及製造用於抑制井鄰近效應的高電壓半導體裝置的方法。 相關申請的交叉引用
本申請案主張2018年6月11日提交的申請號為10-2018-0066708的韓國專利申請的優先權，其公開內容通過引用整體合併於此。
能夠執行控制器和驅動器兩種功能的積體電路可以用在智慧功率裝置中。而且，智慧功率裝置的輸出電路可以被設計為包括在高電壓下工作的橫向雙擴散MOS（LDMOS）電晶體，如所謂的“高電壓半導體裝置”。因此，LDMOS電晶體的崩潰電壓（例如，汲極接面崩潰電壓和閘極介質崩潰電壓）是可能直接影響LDMOS電晶體的穩定操作的重要因素。另外，LDMOS電晶體的導通電阻（Ron）值也可以是可能影響LDMOS電晶體的電特性（例如，LDMOS電晶體的電流驅動能力）的重要因素。
根據一個實施例，提供了一種製造高電壓半導體裝置的方法。該方法包括：在緩衝絕緣層上方形成用於阻擋雜質離子的阻擋圖案，所述緩衝絕緣層設置在第二導電類型的半導體區域中的第一區域上方；在所述緩衝絕緣層上方形成具有開口的離子植入遮罩圖案，以通過離子植入遮罩圖案的開口暴露出所述阻擋圖案，以及使用所述離子植入遮罩圖案，將用於形成第一導電類型的主體區的第一導電類型的雜質離子植入第一區域。
根據另一實施例，提供了一種製造高電壓半導體裝置的方法。該方法包括：在緩衝絕緣層上方形成第一阻擋圖案和第二阻擋圖案，所述第一阻擋圖案與第二阻擋圖案被定位成彼此間隔開以阻擋雜質離子，所述緩衝絕緣層設置在第二導電類型的半導體區域中的第一區域上方。在所述緩衝絕緣層上方形成具有開口的離子植入遮罩圖案，以通過離子植入遮罩圖案的開口暴露出第一阻擋圖案和第二阻擋圖案。使用所述離子植入遮罩圖案，將用於形成第一導電類型的主體區的雜質離子植入到第一區域中。在將第一導電類型的雜質離子植入第一區域之後，去除第一阻擋圖案和第二阻擋圖案。
在以下實施方案的描述中，應理解術語“第一”和“第二”旨在標識元件，而不用於僅定義元件本身或表示特定序列。另外，當一個元件被稱為位於另一個元件“上”、“上方”、“之上”、“下”或“下方”時，它意味著相對位置關係，但不用於限制該元件直接接觸該另一元件或者在它們之間存在至少一個中間元件的某些情況。因此，本文使用的諸如“上”、“上方”、“之上”、“下”、“下方”、“之下”等術語僅用於描述特定實施例的目的，並非旨在限制本公開的範圍。此外，當一個元件被稱為“連接”或“耦接”到另一個元件時，該元件可以直接電性地或機械地連接或耦接到另一個元件，或者可以通過替換其間的另一個元件以形成連接關係或耦接關係。
各種實施例涉及製造高電壓半導體裝置的方法。
用於改善高電壓半導體裝置的導通電阻（Ron）特性的各種方法之一是在高電壓半導體裝置的通道長度方向上減小高電壓半導體裝置的間距尺寸。在這種情況下，也可以減小高電壓半導體裝置的主體區的寬度。就N通道LDMOS電晶體而言，與閘極電極重疊的主體區可以用作通道區。由於通道區的摻雜濃度可能直接影響N通道LDMOS電晶體的閾值電壓，因此可能需要精確地控制通道區的摻雜濃度。在主體區中通道區的摻雜濃度可能主要受用於形成主體區的離子植入製程的影響。由於在用於形成主體區的離子植入製程期間發生的井鄰近效應（WPE），在主體區中通道區的摻雜濃度可能不期望地增大。井鄰近效應（WPE）是指由於當朝向晶圓行進的雜質離子被用作離子植入遮罩的光阻圖案的側表面和閘極的側表面散射以被植入不需要的區域時在奈米級別上發生的現象引起的效應。本公開的各種實施例將提供製造高電壓半導體裝置的方法，所述高電壓半導體裝置能夠抑制由於井鄰近效應（WPE）而導致在主體區中的通道區的摻雜濃度不期望地增大的現象。
圖1至圖7是示出根據本公開的實施例的製造高電壓半導體裝置的方法的截面圖。儘管本實施例結合製造N通道高電壓半導體裝置的方法進行描述，但是本公開也可以同樣適用於利用將每個摻雜區域的導電類型都改變成相反的導電類型來製造P通道高電壓半導體裝置的方法。參考圖1，具有第二導電類型的掩埋層104（例如，N型掩埋層）可以形成在第一導電類型的基板102（例如，P型基板）的一部分上。在一個實施例中，基板102可以是矽基板。P型磊晶層106可以形成在基板102上以覆蓋掩埋層104。掩埋層104和磊晶層106可以使用本領域公知的方法和材料來形成，因此，不需要進一步描述。
參考圖2，P型掩埋層108可以形成在P型磊晶層（圖1中的106）的下部。N型半導體區域（即，N型漂移區110）可以形成在P型磊晶層（圖1中的106）的上部。接下來，可以形成穿透N型漂移區110和P型掩埋層108的P型井區112。在一個實施例中，P型井區112可以被形成為使得P型井區112的底表面與基板102的頂表面接觸。P型井區112可以用作隔離區域，其使根據本實施例製造的高電壓半導體裝置和與高電壓半導體裝置相鄰的其他裝置電性地和實體地隔離。然後可以在P型井區112中形成裝置隔離層114。在一個實施例中，可以使用溝槽隔離製程來形成裝置隔離層114。
參考圖3，可以在N型漂移區110的表面、P型井區112的表面和裝置隔離層114的表面上形成絕緣層113。絕緣層113可以在離子植入製程期間用作緩衝層。另外，絕緣層113也可以用作閘極絕緣層。在一個實施例中，絕緣層113可以由氧化物層形成。場板絕緣圖案115和阻擋圖案116可以形成在絕緣層113上。阻擋圖案116可以被形成為位於第一區域202（在後續製程中在其中形成主體區）上。第一區域202可以位於由裝置隔離層114限定的區域的中央。場板絕緣圖案115可以被形成為位於第一區域202與裝置隔離層114之間的區域上。場板絕緣圖案115和阻擋圖案116兩者可以被形成為具有平面結構。也就是說，場板絕緣圖案115的底表面可以與阻擋圖案116的底表面共平面，並且還可以與絕緣層113的頂表面共平面。場板絕緣圖案115的頂表面可以與阻擋圖案116的頂表面共平面。在一個實施例中，場板絕緣圖案115和阻擋圖案116可以由相同的材料層（例如，氧化物層）來形成。在一個實施例中，場板絕緣圖案115和阻擋圖案116可以通過相同的沉積製程和相同的圖案化製程來形成。更具體地，可以在絕緣層113上沉積絕緣材料層，並且可以在絕緣材料層上形成遮罩圖案。可以通過圖案化製程將絕緣材料層圖案化，該圖案化製程包括使用遮罩圖案作為蝕刻遮罩而執行的蝕刻製程，從而同時形成場板絕緣圖案115和阻擋圖案116。在另一個實施例中，場板絕緣圖案115和阻擋圖案116可以單獨地形成。在這種情況下，在形成場板絕緣圖案115之後，可以使用另一沉積製程和另一圖案化製程來形成阻擋圖案116。
參考圖4，閘極電極118和光阻圖案120可以形成在場板絕緣圖案115和絕緣層113上。例如，導電層可以形成在絕緣層113上以覆蓋場板絕緣圖案115和阻擋圖案116，以及導電層可以被圖案化以形成閘極圖案117，該閘極圖案117覆蓋場板絕緣圖案115、阻擋圖案116以及在場板絕緣圖案115與阻擋圖案116之間的絕緣層113。在一個實施例中，當從平面圖觀察時，場板絕緣圖案115可以被形成為具有閉環形狀（諸如環形圖案）。在這種情況下，阻擋圖案116可以被場板絕緣圖案115圍繞並與場板絕緣圖案115間隔開。隨後，光阻圖案120可以形成在絕緣層113上以暴露出閘極圖案117的中央區域並且覆蓋閘極圖案的邊緣。然後閘極圖案117的中央部分可以使用光阻圖案120作為蝕刻遮罩來蝕刻以形成閘極電極118，所述閘極電極118提供暴露出阻擋圖案116和與阻擋圖案116相鄰的絕緣層113的一部分的開口119。與閘極電極118垂直重疊的絕緣層113和場板絕緣圖案115可以用作閘極絕緣層。在一個實施例中，閘極電極118可以由摻雜的多晶矽層來形成。光阻圖案120可以被形成為提供開口119，該開口119暴露出第一區域202（在後續製程中在其中形成主體區）上的絕緣層113的一部分。通過開口119暴露出的光阻圖案120的側表面可以具有正傾斜輪廓(positive sloped profile)。由於開口119的側表面的正傾斜輪廓，開口119的寬度（例如，平面圖中的直徑）可以朝向基板102逐漸減小。
光阻圖案120的限定開口119的側表面可以與閘極電極118的內側表面對齊。因此，閘極電極118的內側表面和光阻圖案120的側表面可以通過開口119來暴露。如上所述，可以通過使用光阻圖案120作為蝕刻遮罩而執行的蝕刻製程來蝕刻閘極圖案117的中央部分（覆蓋第一區域202上的絕緣層113和阻擋圖案116）以形成閘極電極118來提供開口119。在這種情況下，閘極電極118的內側表面也可以具有正傾斜輪廓。雖然未在圖中示出，但是薄絕緣層可以設置在閘極電極118的由開口119暴露出的內側表面上。如圖4中的箭頭所示，可以使用閘極電極118和光阻圖案120作為植入遮罩來將P型雜質離子植入到第一區域202中，以形成P型主體區。在一個實施例中，P型雜質離子可以在垂直於基板102的表面的方向上植入。在一個實施例中，P型雜質離子可以是硼（B）離子。作為P型雜質離子的離子植入的結果，可以在N型漂移區110的第一區域202中形成摻雜區域。
如圖5中更具體地示出，阻擋圖案116可以抑制在用於形成P型主體區的離子植入製程期間由於井鄰近效應（WPE）導致的第二區域152的摻雜濃度增大的現象。第二區域152表示位於P型主體區中以與閘極電極118垂直重疊的通道區域。具體地，如圖5所示，朝向閘極電極118的傾斜內側表面或光阻圖案120的傾斜側表面行進的P型雜質離子302可以在閘極電極118的傾斜內側表面或光阻圖案120的傾斜側表面上反射，以朝向第二區域152散射（參見箭頭304）。在本實施例中，阻擋圖案116可以位於散射的P型雜質離子朝向第二區域152行進的路徑304中，從而防止散射的P型雜質離子被植入到第二區域152中。在將P型雜質離子植入到第一區域202中之後，可以去除光阻圖案120和阻擋圖案116。儘管未在附圖中示出，但是在植入用於形成P型主體區的P型雜質離子之後，可以另外將N型雜質離子植入第二區域152中，以更精確地調節高電壓半導體裝置的閾值電壓。
參考圖6，植入到第一區域202中的P型雜質離子可以使用擴散製程擴散以形成P型主體區111。在形成P型主體區111之後，可以在閘極電極118的側表面上形成閘極側壁間隔件122。隨後，可以利用適當的離子植入遮罩來植入N型雜質離子，並且可以利用另一種適當的離子植入遮罩來植入P型雜質離子。此後，可以執行擴散製程以同時在N型漂移區110中形成N型汲極區132以及在P型主體區111中形成P型源極接觸區136和N型源極區134。另外，在擴散製程期間，也可以在P型井區112中形成P型井接觸區138。在另一個實施例中，用於形成N型汲極區132和N型源極區134的N型雜質離子可以通過第一擴散製程來擴散，並且用於形成P型源極接觸區136和P型井接觸區138的P型雜質離子可以通過與第一擴散製程不同的第二擴散製程來擴散。
參考圖7，層間絕緣層124可以形成在基板的包括N型汲極區132、N型源極區134、P型源極接觸區136和P型井接觸區138的整個表面上。可以將層間絕緣層124圖案化以形成暴露N型汲極區132、P型源極接觸區136、P型井接觸區138和閘極電極118的接觸孔。隨後，可以用導電層填充接觸孔以形成汲極接觸126、源極接觸127、井接觸128和閘極接觸129。雖然圖中未示出，但是在形成層間絕緣層124之前，可以在N型汲極區132、P型源極接觸區136、P型井接觸區138和閘極電極118上形成矽化物層。
圖8和圖9是示出根據本公開的另一個實施例的製造高電壓半導體裝置的方法的截面圖。在圖8和圖9中，與圖1至圖7中使用的附圖標記相同的附圖標記表示相同的元件。因此，以下省略與參考圖1至圖7闡述的元件相同的元件的詳細描述，以避免重複描述。參考圖8和圖9，根據本實施例，第一阻擋圖案416和第二阻擋圖案417可以形成在第一區域202（在後續製程中在其中形成P型主體區111）上的絕緣層113上。也就是說，第一阻擋圖案416和第二阻擋圖案417而不是圖3中所示的阻擋圖案116，可以形成在第一區域202上的絕緣層113上。因此，在阻擋圖案的數量方面，本實施例與圖1至圖7中所示的先前實施例不同。第一阻擋圖案416和第二阻擋圖案417可以被形成為在通道長度方向上（即，在圖8和圖9中的水平方向上）彼此間隔開。第一阻擋圖案416和第二阻擋圖案417也可以被形成為與閘極電極118間隔開。如圖9所示，在植入用於形成P型主體區（圖6和圖7的111）的P型雜質離子時，朝向閘極電極118的傾斜內側表面或者光阻圖案120的傾斜側表面行進的P型雜質離子502可以由閘極電極118的傾斜內側表面或光阻圖案120的傾斜側表面來散射，以朝向第二區域152行進（參見虛線箭頭504）。在本實施例中，第一阻擋圖案416和第二阻擋圖案417可以位於散射的P型雜質離子朝向第二區域152行進的路徑504中，從而防止散射的P型雜質離子被植入到第二區域152中。這樣就防止了形成P型雜質濃度增大的區域。
根據上述實施例，在執行用於形成主體區的離子植入製程之前，可以在待通過後續製程形成的主體區上方形成至少一個阻擋圖案，從而在執行用於形成主體區的離子植入製程時，防止在主體區中的通道區的摻雜濃度由於井鄰近效應（WPE）而不期望地增大。
以上為了說明的目的公開了本公開的實施例。本領域普通技術人員將理解，在不脫離如所附請求項中公開的本公開的範圍和精神的情況下，可以進行各種修改、添加和替換。
102‧‧‧基板 104‧‧‧掩埋層 106‧‧‧磊晶層 108‧‧‧掩埋層 110‧‧‧漂移區 111‧‧‧主體區 112‧‧‧井區 113‧‧‧絕緣層 114‧‧‧裝置隔離層 115‧‧‧場板絕緣圖案 116‧‧‧阻擋圖案 117‧‧‧閘極圖案 118‧‧‧閘極電極 119‧‧‧開口 120‧‧‧光阻圖案 122‧‧‧閘極側壁間隔件 124‧‧‧層間絕緣層 126‧‧‧汲極接觸 127‧‧‧源極接觸 128‧‧‧井接觸 129‧‧‧閘極接觸 132‧‧‧汲極區 134‧‧‧源極區 136‧‧‧源極接觸區 138‧‧‧井接觸區 152‧‧‧區域 202‧‧‧區域 302‧‧‧雜質離子 304‧‧‧箭頭/路徑 416‧‧‧阻擋圖案 417‧‧‧阻擋圖案 502‧‧‧雜質離子 504‧‧‧箭頭/路徑
鑒於附圖和隨附的詳細描述，本公開的各種實施例將變得更加明顯，其中：
圖1至圖7是示出根據本公開的實施例的製造高電壓半導體裝置的方法的截面圖；以及
圖8和圖9是示出根據本公開的實施例的製造高電壓半導體裝置的方法的截面圖。
102‧‧‧基板
104‧‧‧掩埋層
108‧‧‧掩埋層
110‧‧‧漂移區
112‧‧‧井區
113‧‧‧絕緣層
114‧‧‧裝置隔離層
115‧‧‧場板絕緣圖案
116‧‧‧阻擋圖案
118‧‧‧閘極電極
119‧‧‧開口
120‧‧‧光阻圖案
152‧‧‧區域
202‧‧‧區域
302‧‧‧雜質離子
304‧‧‧箭頭/路徑

Claims (23)

  1. 一種製造高電壓半導體裝置的方法，所述方法包括：在緩衝絕緣層上方形成用於阻擋雜質離子的阻擋圖案，所述緩衝絕緣層設置在第二導電類型的半導體區域中的第一區域上方；在所述緩衝絕緣層上方形成具有開口的離子植入遮罩圖案，以通過所述離子植入遮罩圖案的所述開口暴露出所述阻擋圖案的所有上表面和側表面；以及使用所述離子植入遮罩圖案，將用於形成第一導電類型的主體區的所述第一導電類型的雜質離子植入到所述第一區域中。
  2. 根據請求項1所述的方法，其中，所述離子植入遮罩圖案包括閘極電極和覆蓋所述閘極電極的光阻圖案。
  3. 根據請求項2所述的方法，其中，由所述開口暴露出的所述閘極電極的側表面和所述光阻圖案的側表面具有傾斜輪廓。
  4. 根據請求項3所述的方法，還包括：在所述半導體區域上形成與所述閘極電極垂直重疊的場板絕緣圖案；以及在將所述第一導電類型的所述雜質離子植入所述第一區域之後，去除所述阻擋圖案。
  5. 根據請求項4所述的方法，其中，使用相同的沉積製程和相同的圖案化製程來形成所述場板絕緣圖案和所述阻擋圖案。
  6. 根據請求項4所述的方法，其中，所述場板絕緣圖案和所述阻擋圖案由相同的材料層形成。
  7. 根據請求項6所述的方法，其中，所述場板絕緣圖案和所述阻擋圖案由氧化物層形成。
  8. 根據請求項4所述的方法，其中，所述場板絕緣圖案和所述阻擋圖案被形成為具有平面結構。
  9. 根據請求項1所述的方法，其中，所述阻擋圖案被定位成阻擋雜質離子，所述雜質離子被所述離子植入遮罩圖案的由所述開口暴露出的側表面散射而朝向與所述第一區域的邊緣相對應的第二區域行進。
  10. 根據請求項1所述的方法，其中，所述阻擋圖案由氧化物層形成。
  11. 根據請求項1所述的方法，其中，所述阻擋圖案被形成為具有平面結構。
  12. 根據請求項1所述的方法，其中，在形成所述阻擋圖案之前：在所述第一導電類型的基板上方依次形成所述第二導電類型的掩埋層和所述第一導電類型的磊晶層；在所述第一導電類型的所述磊晶層的上部和下部分別形成所述第二導電類型的所述半導體區域和所述第一導電類型的掩埋層；形成所述第一導電類型的井區，所述井區穿透所述第二導電類型的所述半導體區域和所述第一導電類型的所述掩埋層；以及在所述第一導電類型的所述井區與所述第二導電類型的所述半導體區域之間的邊界區域處形成裝置隔離層。
  13. 根據請求項1所述的方法，其中，所述第二導電類型的所述半導體區域用作漂移區。
  14. 一種製造高電壓半導體裝置的方法，所述方法包括：在緩衝絕緣層上方形成第一阻擋圖案和第二阻擋圖案，所述第一阻擋圖案和所述第二阻擋圖案被定位成彼此間隔開以阻擋雜質離子，所述緩衝絕緣層設置在第二導電類型的半導體區域中的第一區域上方；在所述緩衝絕緣層上方形成具有開口的離子植入遮罩圖案，以通過所述離子植入遮罩圖案的所述開口暴露出所述第一阻擋圖案和第二阻擋圖案的所有上 表面和側表面；使用所述離子植入遮罩圖案，將用於形成第一導電類型的主體區的所述第一導電類型的雜質離子植入到所述第一區域中；以及在將所述第一導電類型的所述雜質離子植入所述第一區域之後，去除所述第一阻擋圖案和第二阻擋圖案。
  15. 根據請求項14所述的方法，其中，所述離子植入遮罩圖案包括閘極電極和覆蓋所述閘極電極的光阻圖案。
  16. 根據請求項15所述的方法，其中，由所述開口暴露出的所述閘極電極的側表面和所述光阻圖案的側表面具有傾斜輪廓。
  17. 根據請求項16所述的方法，還包括在所述半導體區域上方形成與所述閘極電極垂直重疊的場板絕緣圖案。
  18. 根據請求項17所述的方法，其中，使用相同的沉積製程和相同的圖案化製程來形成所述場板絕緣圖案、所述第一阻擋圖案和所述第二阻擋圖案。
  19. 根據請求項17所述的方法，其中，所述場板絕緣圖案、所述第一阻擋圖案和所述第二阻擋圖案由相同的材料層形成。
  20. 根據請求項19所述的方法，其中，所述場板絕緣圖案、所述第一阻擋圖案和所述第二阻擋圖案由氧化物層形成。
  21. 根據請求項17所述的方法，其中，所述場板絕緣圖案、所述第一阻擋圖案和所述第二阻擋圖案被形成為具有平面結構。
  22. 根據請求項14所述的方法，其中，所述第一阻擋圖案和第二阻擋圖案被定位成阻擋雜質離子，所述雜質離子被所述離子植入遮罩圖案的由所述開口暴露出的側表面散射而朝向與所述第一區域的邊緣相對應的第二區域行進。
  23. 根據請求項14所述的方法，其中，所述第二導電類型的所述半導體區域用作漂移區。
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