TWI792495B - 功率元件及其製造方法 - Google Patents

功率元件及其製造方法 Download PDF

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TWI792495B
TWI792495B TW110130069A TW110130069A TWI792495B TW I792495 B TWI792495 B TW I792495B TW 110130069 A TW110130069 A TW 110130069A TW 110130069 A TW110130069 A TW 110130069A TW I792495 B TWI792495 B TW I792495B
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葉昱廷
羅國軒
黃建豪
陳巨峰
翁武得
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立錡科技股份有限公司
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Abstract

本發明提出一種功率元件及其製造方法。功率元件包含:半導體層、井區、本體區、閘極、源極與汲極、場氧化區以及自動對準漂移區。其中,場氧化區形成於半導體層之上表面上,且場氧化區介於閘極與汲極之間。場氧化區由化學機械研磨(chemical mechanical polish, CMP)製程步驟所形成。自動對準漂移區形成於半導體層中,且自動對準漂移區完全位於並連接於場氧化區正下方。

Description

功率元件及其製造方法
本發明有關於一種功率元件及其製造方法,特別是指一種具有場氧化區與自動對準漂移區的功率元件及其製造方法。
圖1A及圖1B分別顯示一種習知功率元件100的上視示意圖與剖視示意圖。圖1B顯示圖1A的AA’剖線之剖視示意圖。所謂的功率元件,係指於正常操作時,施加於汲極的電壓高於5V。一般而言,功率元件的汲極與閘極間,具有漂移區12a(如圖1B中虛線框範圍所示意),將汲極19與本體區16分隔,且漂移區12a之橫向長度根據正常操作時所承受的操作電壓而調整。如圖1A與圖1B所示,功率元件100包含:井區12、絕緣結構13、本體區16、閘極17、源極18與汲極19。其中,井區12的導電型為N型,形成於基板11上,絕緣結構13為區域氧化(local oxidation of silicon,LOCOS)結構,以定義操作區13a,作為功率元件100操作時主要的作用區。操作區13a的範圍由圖1A中,粗黑虛線框所示意。為提高功率元件100的崩潰電壓,可延長漂移區12a在通道方向上的長度,但會使導通電阻提高,使得操作速度降低;此外,漂移區12a與汲極19的N型雜質濃度差異較大,且分別耦接的電壓之電壓差超過5V至數百伏的高壓,限制了功率元件100的崩潰電壓,而限制了功率元件100的應用範圍,降低元件的性能。
有鑑於此,本發明提出一種能夠提高不導通操作時之崩潰電壓使功率元件100的耐壓(withstand voltage)提高,並降低導通電阻的功率元件及其製造方法。
於一觀點中,本發明提供一種功率元件,包含:一半導體層,形成於一基板上,該半導體層具有一上表面;一井區,具有一第一導電型,形成於該半導體層中,且該井區位於該上表面下並連接於該上表面;一本體區,具有一第二導電型,形成於該半導體層中,且該本體區位於該上表面下並連接於該上表面,該本體區於一通道方向上,與該井區鄰接;一閘極,形成於該上表面上,部分該本體區位於該閘極正下方並連接於該閘極,以提供該功率元件在一導通操作中之一反轉電流通道,且部分該井區位於該閘極正下方,以提供該功率元件在該導通操作中之一漂移電流通道;一源極與一汲極,具有該第一導電型,且該源極與該汲極形成於該上表面下並連接於該上表面,且該源極與該汲極分別位於該閘極之外部下方之該本體區中與遠離該本體區側之該井區中;一場氧化區,形成於該上表面上,且該場氧化區介於該閘極與該汲極之間,且該場氧化區由一化學機械研磨(chemical mechanical polish,CMP)製程步驟所形成;以及一自動對準漂移區,具有該第一導電型,形成於該半導體層中,且該自動對準漂移區完全位於並連接於該場氧化區正下方。
於另一觀點中,本發明提供一種功率元件製造方法包含:形成一半導體層於一基板上,該半導體層具有一上表面;形成一井區於該半導體層中,且該井區具有第一導電型,且該井區位於該上表面下並連接於該上表面;形成一本體區於該半導體層中,且該本體區具有一第二導電型,且該本體區位於該上表面下並連接於該上表面,該本體區於一通道方向上,與該井區鄰接;形成一閘極 於該上表面上,部分該本體區位於該閘極正下方並連接於該閘極,以提供該功率元件在一導通操作中之一反轉電流通道,且部分該井區位於該閘極正下方,以提供該功率元件在該導通操作中之一漂移電流通道;形成一源極與一汲極於該上表面下並連接於該上表面,且該源極與該汲極具有該第一導電型,且該源極與該汲極分別位於該閘極之外部下方之該本體區中與遠離該本體區側之該井區中;以一化學機械研磨(chemical mechanical polish,CMP)製程步驟形成一場氧化區於該上表面上,且該場氧化區介於該閘極與該汲極之間;以及形成一自動對準漂移區於該半導體層中,該自動對準漂移區具有該第一導電型,且該自動對準漂移區完全位於並連接於該場氧化區正下方。
於一實施例中,該功率元件更包含一場極板,具有導電性,且該場極板形成於該場氧化區上且連接於該場氧化區,該場極板用以電連接於一預設電位,以緩和該功率元件操作時的電場分布。
於一實施例中,該自動對準漂移區之第一導電型雜質濃度低於該汲極之第一導電型雜質濃度,且該自動對準漂移區之第一導電型雜質濃度高於該井區之第一導電型雜質濃度。
於一實施例中,該自動對準漂移區與該場氧化區由同一個微影製程步驟所定義。
於一實施例中,該場極板電連接於該源極。
於一實施例中,該功率元件製造方法,更包含:以一微影製程步驟形成一遮罩於該上表面上且連接於該上表面,且該遮罩定義該場氧化區與該自動對準漂移區;以一離子植入製程步驟,將該第一導電型雜質,以加速離子的形式,植入該遮罩所定義的區域中,以形成該自動對準漂移區;以一沉積製程步驟,沉積一氧化層,且該CMP製程步驟將該遮罩所定義的區域之外的該氧化層移除;以及移除該遮罩。
本發明之優點係為本發明藉由遮罩覆蓋整個低壓區域並只暴露高壓區域之上表面可保護低壓區域,藉由遮罩可防止絕緣結構被蝕刻,僅用單一遮罩就可同時形成自動對準漂移區及場氧化區,藉由CMP製程步驟取代加熱製程步驟可減少加熱製程對低壓區域的影響,且藉由自動對準漂移區可使高壓區域具有漸進式的第一導電形雜質濃度。
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
11,21,31:基板
12,22,32:井區
12a,22a,32a:漂移區
13:絕緣結構
13a:操作區
16,26,36:本體區
17,27,37:閘極
18,28,38:源極
19,29,39:汲極
21’,31’:半導體層
21a,31a:上表面
21b,31b:下表面
23,33:場氧化區
25,35:自動對準漂移區
33’:氧化層
34:遮罩
34’:遮罩材料
36’,38’:光阻層
37’:場極板
100,200,300:功率元件
271,371,371’:介電層
272,372,372’:導電層
273,373,373’:間隔層
圖1A與1B分別顯示一種習知功率元件的上視示意圖與剖視示意圖。
圖2A與2B係分別根據本發明之一實施例顯示功率元件之上視示意圖與剖視示意圖。
圖3A與3B係分別根據本發明之另一實施例顯示功率元件之上視示意圖與剖視示意圖。
圖4A-4L係根據本發明之一實施例顯示功率元件製造方法的剖視示意圖。
有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之較佳實施例的詳細說明中,將可清楚的呈現。本發明中的圖式均屬示意,主要意在表示製程步驟以及各層之間之上下次序關係,至於形狀、厚度與寬度則並未依照比例繪製。
請參考圖2A與2B,其係分別根據本發明之一實施例顯示功率元件200之上視示意圖與剖視示意圖。圖2B顯示圖2A的BB’剖線之剖視示意圖。如圖2A與圖2B所示,功率元件200包含:半導體層21’、井區22、場氧化區23、自動對準漂移區25、本體區26、閘極27、源極28以及汲極29。半導體層21’形成於基板21上;井區22、自動對準漂移區25、源極28與汲極29具有第一導電型;本體區26具有第二導電型。功率元件200例如為如圖2A與2B所示之橫向雙擴散金屬氧化物半導體場效電晶體(lateral double-diffused metal oxide semiconductor field effect transistor,LDMOS)元件。根據本發明之功率元件例如應用於切換式電源供應電路中的功率級電路中,切換式電源供應電路為本領域中具有通常知識者所熟知,在此不予贅述。
半導體層21’形成於基板21上,半導體層21’於垂直方向(如圖2B中之虛線箭號方向所示意,下同)上,具有相對之上表面21a與下表面21b。基板21例如但不限於為一P型或N型的半導體矽基板。半導體層21’例如以磊晶的步驟,形成於基板21上,或是以基板21的部分,作為半導體層21’。形成半導體層21’的方式,為本領域中具有通常知識者所熟知,在此不予贅述。
請繼續參閱圖2A與圖2B,井區22具有第一導電型,形成於半導體層21’中,且井區22位於上表面21a下並連接於上表面21a。本體區26具有第二導電型,形成於半導體層21’中,且本體區26位於上表面21a下並連接於上表面21a,本體區26於通道方向(如圖2B中之實線箭號方向所示意,下同)上,與井區22鄰接。閘極27形成於上表面21a上,部分本體區26位於閘極27正下方並連接於閘極27,以提供功率元件200在導通操作中之反轉電流通道,且部分井區22位於閘極27正下方,以提供功率元件200在導通操作中之漂移電流通道(如圖2B中粗虛線框所示意)。源極28與汲極29具有第一導電型,且源極28與汲極29形成於上 表面21a下並連接於上表面21a,且源極28與汲極29分別位於閘極27之外部下方之本體區26中與遠離本體區26側之井區22中。
場氧化區23形成於上表面21a上,且場氧化區23介於閘極27與汲極29之間。於一實施例中,場氧化區23係由化學機械研磨(chemical mechanical polish,CMP)製程步驟所形成。自動對準漂移區25具有第一導電型,且形成於半導體層21’中。自動對準漂移區25完全位於並連接於場氧化區23正下方。
自動對準漂移區25與場氧化區23係由利用同一個光罩於同一個微影製程步驟所定義。於一實施例中,自動對準漂移區25之第一導電型雜質濃度低於汲極29之第一導電型雜質濃度,且自動對準漂移區25之第一導電型雜質濃度高於井區22之第一導電型雜質濃度。
閘極27包括與上表面21a連接的介電層271、具有導電性的導電層272以及具有電絕緣特性之間隔層273。閘極27用以接受控制訊號控制而導通及不導通功率元件200。
請繼續參閱圖2B,於通道方向上,漂移區22a位於汲極29與本體區26之間,並分隔汲極29與本體區26,且位於靠近上表面21a之井區22中,用以作為功率元件200在導通操作中之漂移電流通道。
需說明的是,所謂反轉電流通道係指功率元件200在導通操作中因施加於閘極27的電壓,而使閘極27的下方形成反轉層(inversion layer)以使導通電流通過的區域,此為本領域具有通常知識所熟知,在此不予贅述。
需說明的是,所謂漂移電流通道係指功率元件200在導通操作中使導通電流以漂移的方式通過的區域,此為本領域具有通常知識所熟知,在此不予贅述。
需說明的是,上表面21a並非指一完全平坦的平面,而是指半導體層21’的一個表面。
需說明的是,前述之「第一導電型」與「第二導電型」係指於功率元件中,以不同導電型之雜質摻雜於半導體組成區域(例如但不限於前述之井區、本體區、源極與汲極等區域)內,使得半導體組成區域成為第一或第二導電型(例如但不限於第一導電型為N型,而第二導電型為P型,或反之亦可),其中,第一導電型與第二導電型為彼此電性相反的導電型。
此外需說明的是,所謂的功率元件,係指於正常操作時,施加於汲極的電壓高於一特定之電壓,例如5V,且本體區26與汲極29之橫向距離(漂移區長度)根據正常操作時所承受的操作電壓而調整,因而可操作於前述較高之特定電壓。此皆為本領域中具有通常知識者所熟知,在此不予贅述。
請參考圖3A與3B,其係分別根據本發明之另一實施例顯示功率元件300之上視示意圖與剖視示意圖。圖3B顯示圖3A的CC’剖線之剖視示意圖。如圖3A與3B所示,功率元件300包含:半導體層31’、井區32、場氧化區33、自動對準漂移區35、本體區36、閘極37、場極板(field plate)37’、源極38以及汲極39。井區32、自動對準漂移區35、源極38與汲極39具有第一導電型;本體區36具有第二導電型。
請繼續參閱圖3A與3B,本實施例與圖2B之實施例不同之處在於,本實施例之功率元件300包括場極板37’,其具有導電性,且場極板37’形成於場氧化區33上且連接於場氧化區33。場極板37’用以電連接於預設電位,以緩和功率元件300操作時的電場分布。在一種較佳的實施例中,場極板37’係電連接於源極38。於一實施例中,場極板37’可利用與閘極37相同之製程步驟形成。於此實施例中,如圖3B所示,場極板37’包括與上表面31a連接的介電層371’、具有導電性的導電層372’以及具有電絕緣特性之間隔層373’。於另一實施例中,場極板37’亦可以為利用其他矽化金屬製程步驟或金屬製程步驟所形成之矽化金屬層或金屬層。
請參考圖4A-4L,其係根據本發明之一實施例顯示功率元件製造方法的剖視示意圖。如圖4A所示,首先提供基板31,基板31例如但不限於為一P型或N型的半導體矽基板。接著,如圖4B所示,形成半導體層31’於基板31上,半導體層31’於垂直方向(如圖4B中之虛線箭號方向所示意,下同)上,具有相對之上表面31a與下表面31b。半導體層31’例如以磊晶的步驟,形成於基板31上,或是以基板31的部分,作為半導體層31’。形成半導體層31’的方式,為本領域中具有通常知識者所熟知,在此不予贅述。
請繼續參閱圖4B,接著,形成井區32於半導體層31’中,且於垂直方向上,井區32位於上表面31a下並連接於上表面31a。井區32具有第一導電型,例如可利用例如但不限於離子植入製程步驟,將第一導電型雜質,以加速離子的形式,如圖4B中向下的虛線箭號所示意,植入半導體層31’中,以形成井區32。
接著,請參閱圖4C,形成本體區36於半導體層31’中,且本體區36位於上表面31a下並連接於上表面31a,本體區36於通道方向(如圖4C中之實線箭號方向所示意,下同)上,與井區32鄰接。部分本體區36位於後續所形成之閘極37正下方並連接於閘極37,以提供功率元件300在導通操作中之反轉電流通道。本體區36具有第二導電型,形成本體區36之步驟,例如但不限於利用由微影製程步驟形成光阻層36’為遮罩,將第二導電型雜質摻雜至半導體層31’的井區32中,將定義的部分從井區32反摻雜(counter dope)而形成本體區36。其中,本實施例可利用例如但不限於離子植入製程步驟,將第二導電型雜質,以加速離子的形式,植入部分井區32中,以形成本體區36。
接著,請參閱圖4D,利用例如沉積製程步驟形成遮罩材料34’於半導體層31’之上表面31a上,以覆蓋整個上表面31a。於一實施例中,遮罩材料34’例如但不限於氮化矽(SiN)。接續,請參照圖4E,利用例如微影製程步驟形成光阻層38’於遮罩材料34’之上。接著,請參閱圖4F,利用例如蝕刻製程步驟移除 未被光阻層38’覆蓋住的部分遮罩材料34’,使得剩餘的遮罩材料得以作為遮罩34。遮罩34係形成於上表面31a上且連接於上表面31a,且遮罩34係定義了場氧化區33與自動對準漂移區35。應注意者為,遮罩34係覆蓋整個低壓區域之上表面31a,只有在高壓區域才會如圖4F暴露出上表面31a。
之後,請參照圖4G,形成自動對準漂移區35於半導體層31’中。自動對準漂移區35完全位於並連接於後續所形成之場氧化區33正下方。自動對準漂移區35具有第一導電型,例如可利用例如但不限於離子植入製程步驟,將第一導電型雜質,以加速離子的形式,如圖4G中向下的虛線箭號所示意,植入遮罩34所定義的區域中,以形成自動對準漂移區35。於一實施例中,自動對準漂移區35之第一導電型雜質濃度低於汲極39之第一導電型雜質濃度,且自動對準漂移區35之第一導電型雜質濃度高於井區32之第一導電型雜質濃度。
接續,請參照圖4H,移除光阻層38’後,並利用例如沉積製程步驟形成氧化層33’於遮罩34之上。
接著,請參照圖4I,以CMP製程步驟將遮罩34所定義的區域之外的氧化層33’移除,以形成場氧化區33於上表面31a上。場氧化區33介於後續所形成之閘極37與汲極39之間。
之後,請參照圖4J,移除遮罩34。接著,請參照圖4K,形成閘極37於半導體層31’之上表面31a上,且形成場極板37’於場氧化區33上。其中,部分本體區36位於閘極37正下方並連接於閘極37,以提供功率元件300在導通操作中之反轉電流通道。部分井區32位於閘極37正下方,以提供功率元件300在導通操作中之漂移電流通道。場極板37’連接於場氧化區33,且場極板37’具有導電性。場極板37’用以電連接於預設電位,以緩和功率元件300操作時的電場分布。場極板37’電連接於後續所形成之源極38。
於本實施例中,場極板37’可利用與閘極37相同之製程步驟同時形成。於此實施例中,如圖4K所示,場極板37’包括與上表面31a連接的介電層371’、具有導電性的導電層372’以及具有電絕緣特性之間隔層373’。於另一實施例中,場極板37’亦可為利用其他矽化金屬製程步驟或金屬製程步驟所形成之矽化金屬層或金屬層。
如圖4K所示,閘極37包括與上表面31a連接的介電層371、具有導電性的導電層372以及具有電絕緣特性之間隔層373。閘極37用以接受控制訊號控制而導通及不導通功率元件300。
請繼續參閱圖4L,形成源極38與汲極39於上表面31a下並連接於上表面31a,且源極38與汲極39分別位於閘極37在通道方向之外部下方之本體區36中與遠離本體區36側之井區32中,且於通道方向上,漂移區32a位於汲極39與本體區36之間,靠近上表面31a之井區32中,用以作為功率元件300在導通操作中之漂移電流通道。形成源極38與汲極39之步驟,例如但不限於利用閘極37、場極板37’、場氧化區33以及由微影製程步驟形成光阻層為遮罩,將第一導電型雜質分別摻雜至本體區36中與井區32中,以形成源極38與汲極39。其中,本實施例可利用例如但不限於離子植入製程步驟,將第一導電型雜質,以加速離子的形式,植入本體區36中與井區32中,以形成源極38與汲極39。
如上所述,本發明提供了一種具有場氧化區33與自動對準漂移區35的功率元件300及其製造方法,其藉由遮罩覆蓋整個低壓區域並只暴露高壓區域之上表面可保護低壓區域,藉由遮罩可防止絕緣結構被蝕刻,僅用單一遮罩就可同時形成自動對準漂移區及場氧化區,藉由CMP製程步驟取代加熱製程步驟可減少加熱製程對低壓區域的影響,且藉由自動對準漂移區可使高壓區域具有漸進式的第一導電形雜質濃度。
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,在不影響元件主要的特性下,可加入其他製程步驟或結構,如矽化金屬層等;又如,微影技術並不限於光罩技術,亦可包含電子束微影技術。凡此種種,皆可根據本發明的教示類推而得。此外,所說明之各個實施例,並不限於單獨應用,亦可以組合應用,例如但不限於將兩實施例併用。因此,本發明的範圍應涵蓋上述及其他所有等效變化。此外,本發明的任一實施型態不必須達成所有的目的或優點,因此,請求專利範圍任一項也不應以此為限。
21:基板
21’:半導體層
21a:上表面
21b:下表面
22:井區
22a:漂移區
23:場氧化區
25:自動對準漂移區
26:本體區
27:閘極
28:源極
29:汲極
200:功率元件
271:介電層
272:導電層
273:間隔層

Claims (8)

  1. 一種功率元件,包含:一半導體層,形成於一基板上,該半導體層具有一上表面;一井區,具有一第一導電型,形成於該半導體層中,且該井區位於該上表面下並連接於該上表面;一本體區,具有一第二導電型,形成於該半導體層中,且該本體區位於該上表面下並連接於該上表面,該本體區於一通道方向上,與該井區鄰接;一閘極,形成於該上表面上,部分該本體區位於該閘極正下方並連接於該閘極,以提供該功率元件在一導通操作中之一反轉電流通道,且部分該井區位於該閘極正下方,以提供該功率元件在該導通操作中之一漂移電流通道;一源極與一汲極,具有該第一導電型,且該源極與該汲極形成於該上表面下並連接於該上表面,且該源極與該汲極分別位於該閘極之外部下方之該本體區中與遠離該本體區側之該井區中;一場氧化區,形成於該上表面上,且該場氧化區介於該閘極與該汲極之間,且該場氧化區由一化學機械研磨(chemical mechanical polish,CMP)製程步驟所形成;以及一自動對準漂移區,具有該第一導電型,形成於該半導體層中,且該自動對準漂移區完全位於並連接於該場氧化區正下方;其中該自動對準漂移區與該場氧化區由同一個微影製程步驟所定義。
  2. 如請求項1所述之功率元件,更包含一場極板,具有導電性,且該場極板形成於該場氧化區上且連接於該場氧化區,該場極板用以電連接於一預設電位,以緩和該功率元件操作時的電場分布。
  3. 如請求項1所述之功率元件,其中該自動對準漂移區之第一導電型雜質濃度低於該汲極之第一導電型雜質濃度,且該自動對準漂移區之第一導電型雜質濃度高於該井區之第一導電型雜質濃度。
  4. 如請求項2所述之功率元件,其中該場極板電連接於該源極。
  5. 一種功率元件製造方法,包含:形成一半導體層於一基板上,該半導體層具有一上表面;形成一井區於該半導體層中,且該井區具有第一導電型,且該井區位於該上表面下並連接於該上表面;形成一本體區於該半導體層中,且該本體區具有一第二導電型,且該本體區位於該上表面下並連接於該上表面,該本體區於一通道方向上,與該井區鄰接;以一微影製程步驟形成一遮罩於該上表面上且連接於該上表面,且該遮罩定義一場氧化區與一自動對準漂移區;以一離子植入製程步驟,將該第一導電型雜質,以加速離子的形式,植入該遮罩所定義的區域中,以形成該自動對準漂移區;以一沉積製程步驟,沉積一氧化層;以一化學機械研磨(chemical mechanical polish,CMP)製程步驟形成該場氧化區於該上表面上,且該CMP製程步驟將該遮罩所定義的區域之外的該氧化層移除;移除該遮罩以形成該自動對準漂移區於該半導體層中,該自動對準漂移區具有該第一導電型,且該自動對準漂移區完全位於並連接於該場氧化區正下方;形成一閘極於該上表面上,部分該本體區位於該閘極正下方並連接於該閘極,以提供該功率元件在一導通操作中之一反轉電流通道,且部分該井區 位於該閘極正下方,以提供該功率元件在該導通操作中之一漂移電流通道;以及形成一源極與一汲極於該上表面下並連接於該上表面,且該源極與該汲極具有該第一導電型,且該源極與該汲極分別位於該閘極之外部下方之該本體區中與遠離該本體區側之該井區中;其中該場氧化區介於該閘極與該汲極之間。
  6. 如請求項5所述之功率元件製造方法,更包含形成一場極板於該場氧化區上且連接於該場氧化區,其中該場極板具有導電性,且該場極板用以電連接於一預設電位,以緩和該功率元件操作時的電場分布。
  7. 如請求項5所述之功率元件製造方法,其中該自動對準漂移區之第一導電型雜質濃度低於該汲極之第一導電型雜質濃度,且該自動對準漂移區之第一導電型雜質濃度高於該井區之第一導電型雜質濃度。
  8. 如請求項6所述之功率元件製造方法,其中該場極板電連接於該源極。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102468335A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
US20210234041A1 (en) * 2018-07-27 2021-07-29 Csmc Technologies Fab2 Co., Ltd. Semiconductor Device and Method For Manufacturing Same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102468335A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
US20210234041A1 (en) * 2018-07-27 2021-07-29 Csmc Technologies Fab2 Co., Ltd. Semiconductor Device and Method For Manufacturing Same

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