WO2021128355A1 - 横向扩散金属氧化物半导体晶体管及制造方法 - Google Patents

横向扩散金属氧化物半导体晶体管及制造方法 Download PDF

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Publication number
WO2021128355A1
WO2021128355A1 PCT/CN2019/129485 CN2019129485W WO2021128355A1 WO 2021128355 A1 WO2021128355 A1 WO 2021128355A1 CN 2019129485 W CN2019129485 W CN 2019129485W WO 2021128355 A1 WO2021128355 A1 WO 2021128355A1
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Prior art keywords
insulating medium
modulation gate
passivation layer
metal oxide
diffused metal
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PCT/CN2019/129485
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English (en)
French (fr)
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晏锦辉
张孝坤
杨承瑜
贾秋凌
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华为技术有限公司
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Priority to PCT/CN2019/129485 priority Critical patent/WO2021128355A1/zh
Priority to CN201980103018.5A priority patent/CN114830352A/zh
Publication of WO2021128355A1 publication Critical patent/WO2021128355A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a laterally diffused metal oxide semiconductor transistor and a manufacturing method.
  • LDMOS Laterally Diffused Metal-Oxide-Semiconductor
  • LDMOS is often used to make radio frequency power amplifiers for base stations because it can meet the requirements of high output power and gate-source breakdown voltage greater than 60 volts. Compared with other devices, the maximum frequency of LDMOS power amplifier is relatively small and is often used in microwave/RF circuits to make RF power amplifiers for base stations.
  • Breakdown voltage is a key parameter of high-voltage LDMOS devices. Too small a breakdown voltage will cause LDMOS to be broken down under high voltage and cause device failure. Therefore, it is necessary to increase the breakdown voltage of high-voltage LDMOS devices.
  • the embodiments of the present application provide a laterally diffused metal oxide semiconductor transistor and a manufacturing method thereof, which solves the problem that the breakdown voltage of a high-voltage LDMOS device is too small, which causes the device to fail.
  • a laterally diffused metal oxide semiconductor transistor including: a substrate including a source region, a body region, a drift region, and a drain region arranged along a first direction, wherein the The first direction is a direction parallel to the first surface of the substrate; the first modulation gate is disposed close to the surface of the body region; a passivation layer is disposed close to the surface of the drift region; the passivation layer includes: along the first surface The first insulating medium and the second insulating medium are alternately arranged in one direction; the dielectric constant of the second insulating medium is different from the dielectric constant of the first insulating medium.
  • the first insulating medium and the second insulating medium with different dielectric constants, it is possible to avoid the formation of extra current on the first insulating medium or the second insulating medium, making the passivation layer more resistant to breakdown and improving the first insulating medium.
  • a modulation of the breakdown voltage between the gate and the drain region improves the breakdown resistance of the laterally diffused metal oxide semiconductor transistor.
  • the widths of the first insulating medium and the second insulating medium in the passivation layer along the first direction are equal.
  • the first insulating medium and the second insulating medium are uniformly distributed, and the breakdown resistance of the laterally diffused metal oxide semiconductor transistor is improved.
  • the width of each layer of the second insulating medium along the first direction is 0.1 ⁇ m-0.8 ⁇ m. Therefore, the width of each layer of the second insulating medium is small, and the formation of current on the second insulating medium is avoided.
  • the thickness of the passivation layer is 0.1 ⁇ m-0.3 ⁇ m. Therefore, the thickness of the passivation layer is small, and the production cost is saved.
  • the first insulating medium is silicon dioxide
  • the second insulating medium is silicon oxynitride. Therefore, the cost of the first insulating medium and the second insulating medium are lower, and they are used in the passivation layer to increase the breakdown voltage of the laterally diffused metal oxide semiconductor transistor and reduce the production cost at the same time.
  • the laterally diffused metal oxide semiconductor transistor further includes: a second modulation gate, a part of the second modulation gate is disposed on the surface of the drift region, and the other part is disposed on the first modulation gate.
  • the second modulation gate On the surface of the gate, the second modulation gate is connected to the passivation layer, wherein the second modulation gate is connected to the first surface of the substrate, the second modulation gate and the first modulation gate, the The first insulating medium is provided between the first modulation gate and the first surface of the substrate.
  • the second modulation gate has played a shielding role in the drain region and the first modulation gate so far, so that the parasitic capacitance between the first modulation gate and the drain region is greatly reduced, so that the switching speed of the device can be greatly improved. Switching power consumption is greatly reduced.
  • the passivation layer is provided on the surface of the first modulation gate and the surface of the drain region, wherein the passivation layer and the first modulation gate, the passivation layer and the The first insulating medium is provided between the first surface of the substrate, the first modulation gate and the first surface of the substrate.
  • a method for manufacturing a laterally diffused metal oxide semiconductor transistor including: depositing a first modulation gate on a first surface of a substrate, wherein the substrate includes The source region, the body region, the drift region and the drain region are provided, wherein the first direction is a direction parallel to the first surface, and the first modulation gate is opposite to the body region; on the first modulation gate A passivation layer is deposited, wherein the passivation layer is opposite to the drift zone; wherein, the passivation layer includes: a first insulating medium and a second insulating medium alternately arranged along the first direction, and the second insulating medium The dielectric constant is greater than and different from the dielectric constant of the first insulating medium.
  • depositing the passivation layer on the first insulating medium includes: depositing a second insulating medium on the first insulating medium; etching the second insulating medium to make the second insulating medium The medium is exposed; the first insulating medium is deposited at the etching position, so that the first insulating medium and the second insulating medium are alternately arranged along the first direction.
  • the first insulating medium and the second insulating medium have the same width in the first direction.
  • the width of the second insulating medium in the first direction is 0.1 ⁇ m-0.8 ⁇ m.
  • the thickness of the passivation layer is 0.1 ⁇ m-0.3 ⁇ m.
  • the first insulating medium is silicon dioxide
  • the second insulating medium is silicon oxynitride
  • the widths of the first insulating medium and the second insulating medium in the passivation layer along the first direction are equal.
  • the method before depositing the first modulation gate on the first insulating medium, the method further includes: depositing the first insulating medium on the first surface of the substrate.
  • the method before depositing a passivation layer on the first insulating medium, the method further includes: depositing a second modulation gate on the first modulation gate and the first surface of the substrate, A part of the second modulation gate is arranged close to the surface of the drift region, and the other part is arranged on the surface of the first modulation gate, wherein the second modulation gate is connected to the passivation layer.
  • the method before depositing the second modulation gate on the first surface of the first modulation gate and the substrate, the method further includes: The first insulating medium is deposited on the first surface.
  • the passivation layer is provided on the surface of the first modulation gate and the surface of the drain region, wherein the passivation layer and the first modulation gate, the passivation layer and the The first surface of the substrate is provided with the first insulating medium between the first modulation gate and the first surface of the substrate.
  • FIG. 1 is a schematic structural diagram of a laterally diffused metal oxide transistor provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of another laterally diffused metal oxide transistor provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of another laterally diffused metal oxide transistor provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of another laterally diffused metal oxide transistor provided by an embodiment of the application.
  • 4A is a graph of the breakdown voltage of the laterally diffused metal oxide transistor in FIG. 4 as a function of time;
  • FIG. 5 is a schematic structural diagram of another laterally diffused metal oxide transistor provided by an embodiment of the application.
  • FIG. 5A is a graph of the breakdown voltage of the laterally diffused metal oxide transistor in FIG. 5 as a function of time;
  • 6A is a top view of a laterally diffused metal oxide transistor provided by an embodiment of the application.
  • 6B is a top view of another laterally diffused metal oxide transistor provided by an embodiment of the application.
  • 6C is a top view of another laterally diffused metal oxide transistor provided by an embodiment of the application.
  • FIG. 7 is a flowchart of a method for manufacturing a laterally diffused metal oxide transistor according to an embodiment of the application.
  • 8A, 8B, 8C, and 8D are schematic diagrams of the product structure obtained by performing each step in FIG. 7;
  • FIG. 9 is a flowchart of another method for manufacturing a laterally diffused metal oxide transistor according to an embodiment of the application.
  • FIG. 10A is a schematic diagram of the product structure obtained by performing the steps in FIG. 9;
  • FIG. 11 is a flowchart of another method for manufacturing a laterally diffused metal oxide transistor according to an embodiment of the application.
  • FIG. 12A, FIG. 12B, and FIG. 12C are schematic diagrams of the product structure obtained by performing the steps in FIG. 11.
  • Dielectric constant When an electric field is applied to the medium, an induced charge will be generated to weaken the electric field.
  • the ratio of the original applied electric field (in vacuum) to the electric field in the final medium is the dielectric constant, which is related to frequency.
  • Breakdown voltage The voltage at which dielectric breakdown occurs. Under the action of a strong electric field, the dielectric will lose its dielectric properties and become a conductor, which is called dielectric breakdown, and the corresponding voltage is called breakdown voltage.
  • Miller effect In electronics, in the inverting amplifier circuit, the distributed capacitance or parasitic capacitance between the input and output due to the amplifier's amplification effect, the capacitance value equivalent to the input end will be enlarged by 1+K times, where K It is the magnification of the voltage of the amplifying circuit of this stage.
  • K the magnification of the voltage of the amplifying circuit of this stage.
  • MOSFET MOSFET
  • the coverage capacitance between the gate and the drain is the Miller capacitance, and the coverage capacitance is just across the input terminal (gate) and the output terminal (drain), so the Miller effect increases the equivalent input capacitance. Large, resulting in lower frequency characteristics.
  • FIG. 1 is a schematic structural diagram of the laterally diffused metal oxide transistor provided by an embodiment of the present application.
  • the laterally diffused metal oxide transistor includes: a substrate 200, and a first modulation gate 102 and a passivation layer 103 disposed on the substrate 200.
  • the substrate includes a source region 201, a body region 202, a drift region 203, and a drain region 204 arranged along the first direction.
  • the substrate 200 is, for example, a silicon substrate doped with the first conductivity type.
  • the first direction is a direction parallel to the first surface of the substrate 200.
  • the substrate 200 has a cubic shape, for example, and the first surface of the substrate 200 may be any surface of the substrate 200.
  • the surfaces of the source region 201, the body region 202, the drift region 203, and the drain region 204 are, for example, all located on the first surface of the substrate 200 and extend from the first surface of the substrate 200 to the interior of the substrate 200.
  • the source region 201 and the drain region 204 are respectively located on both sides of the substrate 200 in the first direction, and the body region 202 and the drift region 203 are located between the source region 201 and the drain region 204 in the first direction.
  • the first direction is, for example, the direction of the X axis in FIG. 1.
  • the drift region 203 is composed of, for example, a second conductivity type ion implantation region, and the body region 202 is composed of, for example, a first conductivity type ion implantation region.
  • the source region 201 and the body region 202 have the same doping type and different doping concentrations.
  • the doping type of the drain region 204 and the drift region 203 are the same, and the doping concentration is different.
  • the first modulation gate 102 is provided on the surface of the body region 202.
  • the first modulation gate 102 is made of, for example, polysilicon.
  • the first modulation gate 102 is used to control the switch on and off of the source region 201 and the drain region 204 according to the voltage.
  • the source region 201 and the drain region 204 can pass through the body.
  • the region 202 and the drift region 203 are turned on.
  • a first insulating medium 101 is provided between the first modulation gate 102 and the surface of the body region 202, and the first insulating medium 101 can insulate the first modulation gate 102 and the body region 202.
  • the first modulation gate 102 covers the surface of the body region 202 and the second side surface of the first modulation gate 102 extends to the surface of the drift region 203.
  • the surface of the body region 202 covered by the first modulation gate 102 is used to form a channel.
  • the capacitance between the first modulation gate 102 and the drain region 204 becomes the most critical parasitic capacitance in the laterally diffused metal oxide semiconductor transistor device due to the Miller effect.
  • the parasitic capacitance causes an electric field to be formed between the first modulation gate 102 and the drain region 204.
  • the medium between the first modulation gate 102 and the drain region 204 loses its dielectric properties under the action of the electric field and becomes a conductor. , So that the laterally diffused metal oxide semiconductor transistor device fails.
  • the embodiment of the present application does not limit the coverage of the passivation layer 103.
  • the drift region 203 has the largest electric field intensity.
  • the passivation layer 103 is, for example, disposed on the surface of the drift region 203.
  • a first insulating medium 101 is provided between the passivation layer 103 and the drift region 203 to isolate the passivation layer 103 from the drift region 203 and the drain region 204.
  • the embodiment of the present application does not limit the specific structure of the passivation layer 103.
  • the passivation layer 103 includes a second insulating medium 105, and the dielectric constant of the second insulating medium 105 is greater than the dielectric constant of the first insulating medium 101.
  • the passivation layer 103 has a relatively large dielectric constant.
  • the dielectric performance between the first modulation gate and the drain can be improved, thereby improving the impact of the laterally diffused metal oxide semiconductor transistor. Wear voltage.
  • the embodiment of the present application does not limit the materials of the first insulating medium 101 and the second insulating medium 105.
  • the first insulating medium 101 is, for example, silicon dioxide
  • the second insulating medium 105 is, for example, silicon oxynitride.
  • the dielectric constant of silicon dioxide is relatively low, about 3.9, which is easily broken down in high-voltage LDMOS.
  • Silicon oxynitride has a high dielectric constant of about 7-8, good insulation, low leakage, and oxidation resistance. As the passivation layer 103, it has a better isolation effect and can prevent the laterally diffused metal oxide semiconductor transistor from being broken down.
  • the breakdown voltage of the laterally diffused metal oxide semiconductor transistor can be increased.
  • pure silicon oxynitride captures some electrons, which makes the atoms mismatched and the disorder is more serious.
  • An additional current is formed in the silicon oxynitride.
  • the electrons in the silicon oxynitride generate current under the action of an electric field, it will cause breakdown
  • the sudden drop in voltage as shown in the line graph in FIG. 4A, makes the LDMOS breakdown voltage curve not smooth, which affects the breakdown resistance of the laterally diffused metal oxide semiconductor transistor.
  • FIG. 2 is a schematic structural diagram of another laterally diffused metal oxide transistor provided by an embodiment of the application.
  • the passivation layer 103 further includes: a first insulating medium 101, and the first insulating medium 101 and the second insulating medium 105 are alternately arranged, for example, along the first direction.
  • the use of the first insulating medium 101 to separate the second insulating medium 105 can avoid the formation of additional current on the second insulating medium 105.
  • the laterally diffused metal oxide semiconductor transistor using the passivation layer 103 may be damaged.
  • the breakdown voltage curve is smoother, which improves the breakdown resistance of the device.
  • the passivation layer has a relatively large dielectric constant.
  • the first insulating medium and the second insulating medium are alternately arranged, so that the first insulating medium separates the second insulating medium, avoiding the formation of extra current on the second insulating medium, making the passivation layer more resistant to breakdown and improving
  • the breakdown voltage between the first gate and the drain region 204 is modulated, and the breakdown resistance of the laterally diffused metal oxide semiconductor transistor is improved.
  • the second insulating medium is separated by the first insulating medium, without introducing a new medium, so as to avoid affecting the performance of the laterally diffused metal oxide semiconductor transistor device.
  • the passivation layer 103 is disposed close to the surface of the first modulation gate 102, the surface of the drift region 203, and the surface of the drain region 204, wherein the passivation layer 103 and A first insulating medium is provided between the surface of the first modulation gate 102, the surface of the passivation layer 103 and the drift region 203, and the surface of the passivation layer 103 and the drain region 204.
  • the portion of the passivation layer 103 on the first modulation gate 102 is approximately one third of the width of the first modulation gate 102 in the first direction in the first direction.
  • the other positions of the first modulation gate 102 and the source region 201 are used to connect to other parts of the power amplifier circuit, for example.
  • the coverage of the passivation layer 103 is enlarged, and the breakdown resistance of the laterally diffused metal oxide semiconductor transistor is further improved.
  • FIG. 4 is a schematic structural diagram of another laterally diffused metal oxide semiconductor transistor provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of another laterally diffused metal oxide transistor provided by an embodiment of the application. As shown in FIG. 4 and FIG. 5, the laterally diffused metal oxide semiconductor transistor further includes: a second modulation gate 104.
  • the second modulation gate 104 is partially disposed close to the surface of the drift region 203 and partially disposed on the surface of the first modulation gate 102.
  • the above-mentioned distribution mode of the second modulation gate 104 is only an implementation mode of the embodiment of the present application, and those skilled in the art can adjust it according to the specific structure of the laterally diffused metal oxide semiconductor transistor, which all fall within the protection scope of the present application.
  • the second modulation gate 104 is made of, for example, polysilicon.
  • the second modulation gate 104 acts as a shield between the drain region 204 and the first modulation gate 102.
  • the voltage between the first modulation gate 102 and the drain region 204 can be The parasitic capacitance is greatly reduced, so that the switching speed of the device can be greatly improved, and the switching power consumption is greatly reduced.
  • a first insulating medium 101 is provided between the second modulation gate 104 and the surface of the drift region 203, and between the second modulation gate 104 and the surface of the first modulation gate 102.
  • the first insulating medium 101 can isolate the second modulation gate 104 and the first modulation gate 102, as well as the second modulation gate 104 and the drift region 203.
  • the second modulation gate 104 includes a first side surface, and the first side surface of the second modulation gate 104 is connected to the passivation layer 103.
  • the second modulation gate 104 can be provided to reduce the parasitic capacitance between the first modulation gate and the drain region 204, thereby increasing the first modulation gate and the drain.
  • the breakdown voltage between the regions 204 is beneficial to improve the breakdown resistance of the laterally diffused metal oxide semiconductor transistor.
  • the embodiment of the present application does not limit the shapes of the first insulating medium 101 and the second insulating medium 105 in the passivation layer 103.
  • the first insulating medium 101 and the second insulating medium 105 are, for example, a plurality of alternately arranged strip-shaped structures, and the first insulating medium 101 and the second insulating medium 105 have the same width in the first direction. .
  • the first insulating medium and the second insulating medium are uniformly distributed, and the breakdown resistance of the laterally diffused metal oxide semiconductor transistor is improved.
  • the shape of the first insulating medium 101 and the second insulating medium 105 may also be a broken line shape or a wave shape.
  • the embodiment of the present application does not limit the size of the first insulating medium 101 and the second insulating medium 105 in the passivation layer 103.
  • the width of each layer of the first insulating medium 101 and the second insulating medium 105 along the first direction is 0.1 ⁇ m-0.8 ⁇ m. Therefore, the width of each layer of the second insulating medium is small, and the formation of current on the second insulating medium is avoided.
  • each layer of the first insulating medium 101 and the second insulating medium 105 is 0.1 ⁇ m-0.3 ⁇ m. Therefore, the thickness of the passivation layer is small and the production cost is saved.
  • an embodiment of the present application provides a method for manufacturing a laterally diffused metal oxide transistor.
  • a laterally diffused metal oxide transistor include:
  • a first insulating medium 101 is deposited on the first surface of the substrate 200.
  • the substrate 200 includes a source region 201, a body region 202, a drift region 203, and a drain region 204 arranged along a first direction.
  • the first insulating medium 101 is in contact with the source region 201, the body region 202, the drift region 203 and the drain region 204. ⁇ On the first surface.
  • ion doping and diffusion may be performed in the substrate 200 to form a body region 202 and a drift region 203 with different doping types. Subsequently, ions are implanted at appropriate locations to form source and drain electrodes.
  • the laterally diffused metal oxide transistor is an N-type device
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the laterally diffused metal oxide transistor is a P-type device
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the substrate 200 includes, for example, a silicon base and an epitaxial layer, the epitaxial layer is disposed on the silicon base, and the source region 201, the body region 202, the drift region 203, and the drain region 204 are formed on the epitaxial layer, for example.
  • the first insulating medium 101 is, for example, silicon dioxide.
  • a first modulation gate 102 is deposited on the first insulating medium 101.
  • the first modulation gate 102 is located on the surface of the body region 202.
  • the first modulation gate 102 is made of, for example, polysilicon.
  • the first modulation gate 102 is used to control the switch on and off of the source region 201 and the drain region 204 according to the voltage.
  • the source region 201 and the drain region 204 can pass through the body.
  • the region 202 and the drift region 203 are turned on.
  • a first insulating medium 101 is provided between the first modulation gate 102 and the surface of the body region 202, and the first insulating medium 101 can insulate the first modulation gate 102 and the body region 202.
  • depositing the first insulating medium 101 on the first modulation gate 102 includes: disposing a first insulating medium on the side of the first modulation gate 102 away from the first surface of the substrate 200 and on the side of the first modulation gate 102. Medium 101.
  • a layer of the first insulating medium 101 may be deposited on the first modulation gate 102 and the first surface of the substrate provided with the first insulating medium 101.
  • a passivation layer 103 is deposited on the first insulating medium 101.
  • the passivation layer 103 is located on the surface of the drift region 203.
  • the passivation layer is located on the first modulation gate 102, the drift region 203, and the drain region 204.
  • the coverage of the passivation layer is enlarged, and the breakdown voltage of the laterally diffused metal oxide semiconductor transistor can be improved.
  • the passivation layer 103 includes: a second insulating medium 105, the dielectric constant of the second insulating medium 105 is greater than the dielectric constant of the first insulating medium 101.
  • the passivation layer 103 has a relatively large dielectric constant. By providing the passivation layer 103, the dielectric performance between the first modulation gate and the drain can be improved, thereby increasing the breakdown voltage of the laterally diffused metal oxide semiconductor transistor.
  • a first insulating medium 101 is provided between the passivation layer 103 and the drift region 203 and between the passivation layer 103 and the drain region 204 to isolate the passivation layer 103 from the drift region 203 and the drain region 204.
  • the second insulating medium 105 is, for example, silicon oxynitride, with a high dielectric constant of about 7-8, good insulation, low leakage, and oxidation resistance. As the passivation layer 103, the isolation effect is better and can prevent lateral diffusion of metal oxidation The semiconductor transistor is broken down.
  • the method before depositing the passivation layer 103 on the first insulating medium 101, the method further includes:
  • a second modulation gate 104 is deposited on the first insulating medium 101, so that a part of the second modulation gate 104 is disposed on the drift region 203, and the other part is disposed on the first modulation gate 102 .
  • the second modulation gate 104 is connected to the passivation layer 103.
  • the second modulation gate 104 is a shielding gate, which can be energized to the second modulation gate 104, so that the second modulation gate 104 acts as a shield between the drain region 204 and the first modulation gate 102, so that the first modulation gate
  • the parasitic capacitance between the pole 102 and the drain region 204 is greatly reduced, so the switching speed of the device is greatly improved, and the switching power consumption is greatly reduced.
  • a first insulating medium 101 is provided between the second modulation gate 104 and the surface of the drift region 203, and between the second modulation gate 104 and the surface of the first modulation gate 102.
  • the first insulating medium 101 can isolate the second modulation gate 104 and the first modulation gate 102, as well as the second modulation gate 104 and the drift region 203.
  • depositing a passivation layer 103 on the first insulating medium 101 includes:
  • the second insulating medium 105 is located on the surface of the drift region 203 and the drain region 204.
  • the second modulation gate 104 is partially located on the first modulation gate 102 and partially located on the drift region 203.
  • the second insulating medium 105 is connected to the second side of the second modulation gate 104.
  • the first groove 106 may be etched on the second insulating medium, and the bottom of the first groove 106 is the first insulating medium 101. After the etching is completed, the first insulating medium 101 is exposed.
  • the first insulating medium 101 may be deposited in the first groove 106.
  • the first insulating medium 101 can separate the second insulating medium 105 in the first direction, and the two are alternately arranged to avoid the formation of additional current on the second insulating medium 105, so that the passivation layer 103 is more resistant to breakdown.
  • the second insulating medium 105 is separated by the first insulating medium 101, and there is no need to introduce a new medium, so as to avoid affecting the performance of the laterally diffused metal oxide semiconductor transistor device.

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Abstract

本申请实施例公开了一种横向扩散金属氧化物半导体晶体管及制造方法，该横向扩散金属氧化物半导体晶体管包括：衬底，该衬底包括沿第一方向设置，且表面位于该衬底的第一表面内的源区、体区、漂移区、漏区，其中，该第一方向为平行于该衬底第一表面的方向；第一调制栅极，靠近该体区设置；钝化层，靠近该漂移区设置；该钝化层包括：沿该第一方向交替设置的第一绝缘介质和第二绝缘介质；该第二绝缘介质的介电常数和该第一绝缘介质的介电常数不同。由此，将介电常数不同的第一绝缘介质和第二绝缘介质交替设置，可以避免在第一绝缘介质或第二绝缘介质上形成额外电流，使得钝化层更耐击穿，提升了横向扩散金属氧化物半导体晶体管的抗击穿性能。

Description

横向扩散金属氧化物半导体晶体管及制造方法 技术领域
本申请实施例涉及半导体领域，尤其涉及一种横向扩散金属氧化物半导体晶体管及制造方法。
背景技术
横向扩散金属氧化物半导体(Laterally Diffused Metal-Oxide-Semiconductor,LDMOS)经常被用于微波/射频电路。
LDMOS常被用于制作基站的射频功率放大器，原因是它可以满足高输出功率、栅源击穿电压大于60伏的要求。与其他器件相比，LDMOS功放极大值的频率相对较小经常被用于微波/射频电路，以制作基站的射频功率放大器。
击穿电压是高压LDMOS器件一项关键参数，击穿电压过小会导致LDMOS在高压下被击穿，导致器件失效，因此，有必要提高高压LDMOS器件的击穿电压。
发明内容
本申请实施例提供一种横向扩散金属氧化物半导体晶体管及制造方法，解决了高压LDMOS器件击穿电压过小，引起器件失效的问题。
为达到上述目的，本申请实施例采用如下技术方案：
本申请实施例的第一方面，提供一种横向扩散金属氧化物半导体晶体管，包括：衬底，该衬底包括沿第一方向设置的源区、体区、漂移区、漏区，其中，该第一方向为平行于该衬底第一表面的方向；第一调制栅极，靠近该体区的表面设置；钝化层，靠近该漂移区的表面设置；该钝化层包括：沿该第一方向交替设置的第一绝缘介质和第二绝缘介质；该第二绝缘介质的介电常数和该第一绝缘介质的介电常数不同。由此，将介电常数不同的第一绝缘介质和第二绝缘介质交替设置，可以避免在第一绝缘介质或第二绝缘介质上形成额外电流，使得钝化层更耐击穿，提高了第一调制栅极和漏区之间的击穿电压，提升了横向扩散金属氧化物半导体晶体管的抗击穿性能。
一种可选的实现方式中，该钝化层中的该第一绝缘介质和该第二绝缘介质沿该第一方向的宽度相等。由此，第一绝缘介质和第二绝缘介质均匀分布，提高了横向扩散金属氧化物半导体晶体管的抗击穿性能。
一种可选的实现方式中，每层该第二绝缘介质沿第一方向的宽度为0.1μm-0.8μm。由此，每层第二绝缘介质的宽度较小，避免在第二绝缘介质上形成电流。
一种可选的实现方式中，该钝化层的厚度为0.1μm-0.3μm。由此，钝化层厚度小，节省生产成本。
一种可选的实现方式中，该第一绝缘介质为二氧化硅，该第二绝缘介质为氮氧化硅。由此，第一绝缘介质和第二绝缘介质成本较低，用于钝化层中，提高了横向扩散金属氧化物半导体晶体管的击穿电压，同时降低了生产成本。
一种可选的实现方式中，该横向扩散金属氧化物半导体晶体管还包括：第二调制栅极，该第二调制栅极的一部分设置在该漂移区的表面，另一部分设置在该第一调制 栅极的表面，该第二调制栅极与该钝化层连接，其中，该第二调制栅极与该衬底的第一表面、该第二调制栅极与该第一调制栅极、该第一调制栅极与该衬底的第一表面之间设有该第一绝缘介质。由此，该第二调制栅极在漏区和第一调制栅极至今起到屏蔽作用，使得第一调制栅极和漏区之间的寄生电容大大减小，因此器件开关速度得以大幅提高，开关功耗大幅减小。
一种可选的实现方式中，该第一调制栅极的表面、该漏区的表面设置有该钝化层，其中，该钝化层与该第一调制栅极、该钝化层与该衬底的第一表面、该第一调制栅极与该衬底的第一表面之间设有该第一绝缘介质。由此，扩大了该钝化层的覆盖范围，进一步提高了第一调制栅极和漏区之间的击穿电压，提升了该横向扩散金属氧化物半导体的抗击穿性能。
本申请实施例的第二方面，提供一种横向扩散金属氧化物半导体晶体管的制造方法，包括：在衬底的第一表面上沉积第一调制栅极，其中，该衬底包括沿第一方向设置的源区、体区、漂移区和漏区，其中，该第一方向为平行于该第一表面的方向，该第一调制栅极与该体区相对；在该第一调制栅极上沉积钝化层，其中，该钝化层与该漂移区相对；其中，该钝化层包括：沿该第一方向交替设置的第一绝缘介质和第二绝缘介质，该第二绝缘介质的介电常数大于和该第一绝缘介质的介电常数不同。
一种可选的实现方式中，在该第一绝缘介质上沉积该钝化层，包括：在该第一绝缘介质上沉积第二绝缘介质；刻蚀该第二绝缘介质，使得该第二绝缘介质裸露；在刻蚀位置沉积第一绝缘介质，使得该第一绝缘介质和该第二绝缘介质沿第一方向交替设置。
一种可选的实现方式中，该第一绝缘介质和该第二绝缘介质第一方向的宽度相等。
一种可选的实现方式中，该第二绝缘介质第一方向的宽度为0.1μm-0.8μm。
一种可选的实现方式中，该钝化层的厚度为0.1μm-0.3μm。
一种可选的实现方式中，该第一绝缘介质为二氧化硅，该第二绝缘介质为氮氧化硅。
一种可选的实现方式中，该钝化层中的该第一绝缘介质和该第二绝缘介质沿该第一方向的宽度相等。
一种可选的实现方式中，在该第一绝缘介质上沉积第一调制栅极之前，该方法还包括：在该衬底的第一表面上沉积该第一绝缘介质。
一种可选的实现方式中，在该第一绝缘介质上沉积钝化层之前，该方法还包括：在该第一调制栅极和该衬底的第一表面上沉积第二调制栅极，使得该第二调制栅极的一部分靠近该漂移区的表面设置，另一部分设置在该第一调制栅极的表面，其中，该第二调制栅极与该钝化层连接。
一种可选的实现方式中，在该第一调制栅极和该衬底的第一表面上沉积第二调制栅极之前，该方法还包括：在该第一调制栅极和该衬底的第一表面上沉积该第一绝缘介质。
一种可选的实现方式中，该第一调制栅极的表面、该漏区的表面设置有该钝化层，其中，该钝化层与该第一调制栅极、该钝化层与该衬底的第一表面，以及该第一调制栅极与该衬底的第一表面之间设有该第一绝缘介质。
附图说明
图1为本申请实施例提供的一种横向扩散金属氧化物晶体管的结构示意图；
图2为本申请实施例提供的另一种横向扩散金属氧化物晶体管的结构示意图；
图3为本申请实施例提供的另一种横向扩散金属氧化物晶体管的结构示意图；
图4为本申请实施例提供的另一种横向扩散金属氧化物晶体管的结构示意图；
图4A为图4中横向扩散金属氧化物晶体管的击穿电压随时间变化的曲线图；
图5为本申请实施例提供的另一种横向扩散金属氧化物晶体管的结构示意图；
图5A为图5中横向扩散金属氧化物晶体管的击穿电压随时间变化的曲线图；
图6A为本申请实施例提供的一种横向扩散金属氧化物晶体管的俯视图；
图6B为本申请实施例提供的另一种横向扩散金属氧化物晶体管的俯视图；
图6C为本申请实施例提供的另一种横向扩散金属氧化物晶体管的俯视图；
图7为本申请实施例提供的一种横向扩散金属氧化物晶体管的制造方法流程图；
图8A、图8B、图8C、图8D为执行图7中各步骤得到的产品结构示意图；
图9为本申请实施例提供的另一种横向扩散金属氧化物晶体管的制造方法流程图；
图10A为执行图9中步骤得到的产品结构示意图；
图11为本申请实施例提供的另一种横向扩散金属氧化物晶体管的制造方法流程图；
图12A、图12B、图12C为执行图11中各步骤得到的产品结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
以下，对本申请实施例可能出现的术语进行解释。
介电常数：介质在外加电场时会产生感应电荷而削弱电场，原外加电场(真空中)与最终介质中电场比值即为介电常数，与频率相关。介电常数ε可以定义为电位移D和电场强度E之比，ε＝D/Ε。
击穿电压：使电介质击穿的电压。电介质在足够强的电场作用下将失去其介电性能成为导体，称为电介质击穿，所对应的电压称为击穿电压。
密勒效应：是在电子学中，反相放大电路中，输入与输出之间的分布电容或寄生电容由于放大器的放大作用，其等效到输入端的电容值会扩大1+K倍，其中K是该级放大电路电压放大倍数。对于MOSFET，栅极与漏极之间的覆盖电容是密勒电容，覆盖电容正好跨接在输入端(栅极)与输出端(漏极)之间，故密勒效应使得等效输入电容增大，导致频率特性降低。
本申请实施例提供一种横向扩散金属氧化物晶体管，图1为本申请实施例提供的横向扩散金属氧化物晶体管的结构示意图。如图1所示，该横向扩散金属氧化物晶体管包括：衬底200，以及设置在该衬底200上方的第一调制栅极102和钝化层103。
其中，该衬底包括沿第一方向设置的源区201、体区202、漂移区203、漏区204。其中，该衬底200例如为第一导电类型掺杂的硅衬底。该第一方向为平行于衬底200第一表面的方向。
衬底200例如为立方体形状，衬底200的第一表面可以是衬底200的任意一个表面。其中，源区201、体区202、漂移区203、漏区204的表面例如均位于衬底200的第一表面，并由衬底200的第一表面向衬底200内部延伸。
源区201和漏区204分别在第一方向上位于衬底200的两侧，体区202和漂移区203在第一方向上位于源区201和漏区204之间。第一方向例如为图1中的X轴的方向。
需要说明的是，第一方向与图1中的X轴所在方向可以存在误差，只需使得第一方向与衬底的第一表面平行即可，这些均属于本申请的保护范围。
漂移区203例如由第二导电类型离子注入区组成，体区202例如由第一导电类型离子注入区组成，源区201与体区202的掺杂类型相同，掺杂浓度不同。漏区204与漂移区203的掺杂类型相同，掺杂浓度不同。
第一调制栅极102设置在体区202的表面上。第一调制栅极102例如为多晶硅材质。第一调制栅极102用于根据电压控制源区201和漏区204开关导通和关断，在第一调制栅极102输入高电压时，可以使得源区201和漏区204之间通过体区202和漂移区203导通。
第一调制栅极102与体区202的表面之间设有第一绝缘介质101，第一绝缘介质101可以使得第一调制栅极102与体区202绝缘。
其中，第一调制栅极102覆盖体区202的表面且第一调制栅极102的第二侧面延伸到漂移区203的表面。被第一调制栅极102所覆盖的体区202表面用于形成沟道。
其中，第一调制栅极102和漏区204之间的电容因密勒效应成为横向扩散金属氧化物半导体晶体管器件中最关键的寄生电容。寄生电容使得第一调制栅极102和漏区204之间形成电场，当电场足够强时时，第一调制栅极102和漏区204之间的介质在电场的作用下失去其介电性能成为导体，使得横向扩散金属氧化物半导体晶体管器件失效。
本申请实施例对钝化层103的覆盖范围不做限制。其中，漂移区203电场强度最大，本实施例中，钝化层103例如设置在漂移区203的表面上。
钝化层103与漂移区203之间设有第一绝缘介质101，以隔离钝化层103与漂移区203和漏区204。
本申请实施例对钝化层103的具体结构不做限制。本实施例中，钝化层103包括：第二绝缘介质105，第二绝缘介质105的介电常数大于第一绝缘介质101的介电常数。
由此，钝化层103的介电常数较大，通过设置钝化层103，可以提高第一调制栅极与漏极之间的介电性能，进而提高了横向扩散金属氧化物半导体晶体管的击穿电压。
本申请实施例对第一绝缘介质101和第二绝缘介质105的材质不做限制。本实施 例中，第一绝缘介质101例如为二氧化硅，第二绝缘介质105例如为氮氧化硅。
二氧化硅的介电常数较低，约为3.9，在高压LDMOS中容易被击穿。
氮氧化硅的介电常数高，约为7-8、绝缘性好、漏电低、抗氧化，其作为钝化层103，隔离效果较佳，可以防止横向扩散金属氧化物半导体晶体管被击穿。
本申请实施例提供的横向扩散金属氧化物半导体晶体管，通过设置钝化层103，可以提高横向扩散金属氧化物半导体晶体管的击穿电压。
其中，纯氮氧化硅会捕捉一些电子，使得原子失配，无序性更严重，在氮氧化硅中形成额外电流，当氮氧化硅中的电子在电场作用下产生电流时，会使得击穿电压突然下降，如图4A中的线条图所示，使得LDMOS击穿电压曲线不平滑，影响横向扩散金属氧化物半导体晶体管的抗击穿性能。
为此，本申请实施例还提供一种横向扩散金属氧化物半导体晶体管。图2为本申请实施例提供的另一种横向扩散金属氧化物晶体管的结构示意图。如图2所示，钝化层103还包括：第一绝缘介质101，第一绝缘介质101和第二绝缘介质105例如沿第一方向交替设置。
采用第一绝缘介质101将第二绝缘介质105分隔开，可以避免在第二绝缘介质105上形成额外电流，如图5A所示，采用钝化层103的横向扩散金属氧化物半导体晶体管的击穿电压曲线更平滑，提高了器件的抗击穿性能。
本申请实施例提供的横向扩散金属氧化物半导体晶体管，钝化层的介电常数较大，通过设置钝化层，可以提高了横向扩散金属氧化物半导体晶体管的击穿电压。
同时，将第一绝缘介质和第二绝缘介质交替设置，使得第一绝缘介质将第二绝缘介质分隔开，避免在第二绝缘介质上形成额外电流，使得钝化层更耐击穿，提高了第一调制栅极和漏区204之间的击穿电压，提升了横向扩散金属氧化物半导体晶体管的抗击穿性能。同时，通过第一绝缘介质将第二绝缘介质隔开，无需引入新的介质，避免影响横向扩散金属氧化物半导体晶体管器件的性能。
在本申请另一种实现方式中，如图3所示，钝化层103靠近第一调制栅极102的表面、漂移区203的表面和漏区204的表面设置，其中，钝化层103与第一调制栅极102的表面、钝化层103与漂移区203的表面、钝化层103与漏区204的表面之间设有第一绝缘介质。
钝化层103在第一调制栅极102上的部分，在第一方向上大约为第一调制栅极102第一方向宽度的三分之一。第一调制栅极102的其他位置和源区201例如用于和功率放大电路的其他部分连接。
由此，扩大了钝化层103的覆盖范围，进一步提高了横向扩散金属氧化物半导体晶体管的抗击穿性能。
上述钝化层的覆盖方式仅为本申请实施例的一种实现方式，本领域技术人员可根据横向扩散金属氧化物半导体晶体管的具体结构进行调整，这些均属于本申请的保护范围。
图4为本申请实施例提供的另一种横向扩散金属氧化物半导体晶体管的结构示意图。图5为本申请实施例提供的另一种横向扩散金属氧化物晶体管的结构示意图。如图4、图5所示，横向扩散金属氧化物半导体晶体管还包括：第二调制栅极104。
第二调制栅极104部分靠近漂移区203的表面设置，部分设置在第一调制栅极102的表面。
上述第二调制栅极104的分布方式仅为本申请实施例的一种实现方式，本领域技术人员可根据横向扩散金属氧化物半导体晶体管的具体结构进行调整，这些均属于本申请的保护范围。
第二调制栅极104例如为多晶硅材质。第二调制栅极104在漏区204和第一调制栅极102之间起到屏蔽作用，通过调整第二调制栅极104的电压，可使得第一调制栅极102和漏区204之间的寄生电容大大减小，使得器件开关速度得以大幅提高，开关功耗大幅减小。
第二调制栅极104与漂移区203的表面、第二调制栅极104与第一调制栅极102的表面之间设有第一绝缘介质101。第一绝缘介质101可以隔离第二调制栅极104和第一调制栅极102，以及隔离第二调制栅极104和漂移区203。
其中，第二调制栅极104包括第一侧面，第二调制栅极104的第一侧面与钝化层103连接。
本申请实施例提供的横向扩散金属氧化物半导体晶体管，通过设置第二调制栅极104，可以减小第一调制栅极和漏区204之间的寄生电容，进而提高第一调制栅极和漏区204之间的击穿电压，有利于提升横向扩散金属氧化物半导体晶体管的抗击穿性能。
本申请实施例对钝化层103中第一绝缘介质101和第二绝缘介质105的形状不做限制。本实施例中，如图6A所示，第一绝缘介质101和第二绝缘介质105例如为多个交替设置的条形结构，第一绝缘介质101和第二绝缘介质105第一方向的宽度相等。
由此，第一绝缘介质和第二绝缘介质均匀分布，提高了横向扩散金属氧化物半导体晶体管的抗击穿性能。
此外，如图6B、图6C所示，第一绝缘介质101和第二绝缘介质105的形状还可以为折线形、波形。
本申请实施例对钝化层103中第一绝缘介质101和第二绝缘介质105的尺寸不做限制。本实施例中，每层第一绝缘介质101和第二绝缘介质105沿第一方向的宽度为0.1μm-0.8μm。由此，每层第二绝缘介质的宽度较小，避免在第二绝缘介质上形成电流。
每层第一绝缘介质101和第二绝缘介质105厚度为0.1μm-0.3μm。由此，钝化层厚度小，节省生产成本。
如图7所示，本申请实施例提供一种横向扩散金属氧化物晶体管的制造方法。包括：
S101、如图8A所示，在衬底200的第一表面上沉积第一绝缘介质101。
其中，衬底200包括沿第一方向设置的源区201、体区202、漂移区203和漏区204，第一绝缘介质101与源区201、体区202、漂移区203和漏区204接触于第一表面。
本步骤，具体可以在衬底200中进行离子掺杂和扩散，形成掺杂类型不同的体区202和漂移区203。随后在适当位置注入离子，形成源极和漏极。
其中，若横向扩散金属氧化物晶体管为N型器件，第一导电类型为P型，第二导 电类型为N型。或者，横向扩散金属氧化物晶体管为P型器件，则第一导电类型为N型，第二导电类型为P型。
衬底200例如包括：硅基底和外延层，外延层设置在硅基底上，源区201、体区202、漂移区203和漏区204例如形成在外延层上。第一绝缘介质101例如为二氧化硅。
S102、如图8B所示，在第一绝缘介质101上沉积第一调制栅极102。
其中，第一调制栅极102位于体区202的表面上。第一调制栅极102例如为多晶硅材质。第一调制栅极102用于根据电压控制源区201和漏区204开关导通和关断，在第一调制栅极102输入高电压时，可以使得源区201和漏区204之间通过体区202和漂移区203导通。
第一调制栅极102与体区202的表面之间设有第一绝缘介质101，第一绝缘介质101可以使得第一调制栅极102与体区202绝缘。
S103、如图8C所示，在第一调制栅极102上沉积第一绝缘介质101。
其中，在第一调制栅极102上沉积第一绝缘介质101包括：在第一调制栅极102远离衬底200的第一表面的一侧、以及第一调制栅极102的侧面设置第一绝缘介质101。
本实施例中，可以在第一调制栅极102、以及设有第一绝缘介质101的衬底的第一表面上沉积一层第一绝缘介质101。
S104、如图8D所示，在第一绝缘介质101上沉积钝化层103。
本实施例中，钝化层103位于漂移区203的表面上。
在本申请另一种实现方式中，钝化层位于第一调制栅极102、漂移区203和漏区204上。扩大了钝化层的覆盖范围，可以提高横向扩散金属氧化物半导体晶体管的击穿电压。
其中，钝化层103包括：第二绝缘介质105，第二绝缘介质105的介电常数大于第一绝缘介质101的介电常数。
钝化层103的介电常数较大，通过设置钝化层103，可以提高第一调制栅极与漏极之间的介电性能，进而提高了横向扩散金属氧化物半导体晶体管的击穿电压。
钝化层103与漂移区203、钝化层103与漏区204之间设有第一绝缘介质101，以隔离钝化层103与漂移区203和漏区204。
第二绝缘介质105例如为氮氧化硅，介电常数高，约为7-8、绝缘性好、漏电低、抗氧化，其作为钝化层103，隔离效果较佳，可以防止横向扩散金属氧化物半导体晶体管被击穿。
在本申请另一种实现方式中，如图9所示，在第一绝缘介质101上沉积钝化层103之前，方法还包括：
S105、如图10A所示，在第一绝缘介质101上沉积第二调制栅极104，使得第二调制栅极104的一部分设置在漂移区203上，另一部分设置在第一调制栅极102上。
其中，第二调制栅极104与钝化层103连接。
第二调制栅极104为屏蔽栅，可以向第二调制栅极104通电，使得第二调制栅极104在漏区204和第一调制栅极102之间起到屏蔽作用，使得第一调制栅极102和漏区204之间的寄生电容大大减小，因此器件开关速度得以大幅提高，开关功耗大幅减小。
第二调制栅极104与漂移区203的表面、第二调制栅极104与第一调制栅极102的表面之间设有第一绝缘介质101。第一绝缘介质101可以隔离第二调制栅极104和第一调制栅极102，以及隔离第二调制栅极104和漂移区203。
在本申请另一种实现方式中，如图11所示，在第一绝缘介质101上沉积钝化层103，包括：
S1041、如图12A所示，在第一绝缘介质101上沉积第二绝缘介质105。
其中，第二绝缘介质105位于漂移区203和漏区204的表面上。第二调制栅极104部分位于第一调制栅极102上，部分位于漂移区203上。第二绝缘介质105与第二调制栅极104的第二侧连接。
S1042、如图12B所示，在第二绝缘介质105上进行刻蚀，使得第一绝缘介质101裸露。
其中，可以在第二绝缘介质上刻蚀出第一凹槽106，第一凹槽106的槽底为第一绝缘介质101。刻蚀完成后，第一绝缘介质101裸露。
S1043、如图12C所示，在刻蚀位置沉积第一绝缘介质101，使得第一绝缘介质101和第二绝缘介质105沿第一方向交替设置。
其中，可以在第一凹槽106中沉积第一绝缘介质101。
由此，第一绝缘介质101可以将第二绝缘介质105沿第一方向分隔开，二者交替设置，避免在第二绝缘介质105上形成额外电流，使得钝化层103更耐击穿。
同时，通过第一绝缘介质101将第二绝缘介质105隔开，无需引入新的介质，避免影响横向扩散金属氧化物半导体晶体管器件的性能。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种横向扩散金属氧化物半导体晶体管，其特征在于，包括：
    衬底，包括沿第一方向设置的源区、体区、漂移区、漏区，其中，所述第一方向为平行于所述衬底第一表面的方向；
    第一调制栅极，靠近所述体区的表面设置；
    钝化层，靠近所述漂移区的表面设置；
    所述钝化层包括：沿所述第一方向交替设置的第一绝缘介质和第二绝缘介质；
    所述第二绝缘介质的介电常数和所述第一绝缘介质的介电常数不同。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体晶体管，其特征在于，所述第一绝缘介质为二氧化硅，所述第二绝缘介质为氮氧化硅。
  3. 根据权利要求1或2所述的横向扩散金属氧化物半导体晶体管，其特征在于，每层所述第二绝缘介质沿第一方向的宽度为0.1μm-0.8μm。
  4. 根据权利要求1-3任一项所述的横向扩散金属氧化物半导体晶体管，其特征在于，所述钝化层的厚度为0.1μm-0.3μm。
  5. 根据权利要求1-4任一项所述的横向扩散金属氧化物半导体晶体管，其特征在于，所述钝化层中的所述第一绝缘介质和所述第二绝缘介质沿所述第一方向的宽度相等。
  6. 根据权利要求1-5任一项所述的横向扩散金属氧化物半导体晶体管，其特征在于，还包括：第二调制栅极，所述第二调制栅极的一部分设置在所述漂移区的表面，另一部分设置在所述第一调制栅极的表面，所述第二调制栅极与所述钝化层连接，其中，所述第二调制栅极与所述衬底的第一表面、所述第二调制栅极与所述第一调制栅极、所述第一调制栅极与所述衬底的第一表面之间设有所述第一绝缘介质。
  7. 根据权利要求1-5任一项所述的横向扩散金属氧化物半导体晶体管，其特征在于，所述第一调制栅极的表面、所述漏区的表面设置有所述钝化层，其中，所述钝化层与所述第一调制栅极、所述钝化层与所述衬底的第一表面，以及所述第一调制栅极与所述衬底的第一表面之间设有所述第一绝缘介质。
  8. 一种横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，包括：
    在衬底的第一表面上沉积第一调制栅极，所述衬底包括沿第一方向设置的源区、体区、漂移区、漏区，其中，所述第一方向为平行于所述衬底第一表面的方向，所述第一调制栅极靠近所述体区的表面设置；
    在所述衬底的第一表面上沉积钝化层，其中，所述钝化层靠近所述漂移区的表面设置；
    其中，所述钝化层包括：沿所述第一方向交替设置的第一绝缘介质和第二绝缘介质，所述第二绝缘介质的介电常数和所述第一绝缘介质的介电常数不同。
  9. 根据权利要求8所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述在所述第一绝缘介质上沉积所述钝化层，包括：
    在所述第一绝缘介质上沉积第二绝缘介质；
    刻蚀所述第二绝缘介质，使得所述第二绝缘介质裸露；
    在刻蚀位置沉积第一绝缘介质，使得所述第一绝缘介质和所述第二绝缘介质沿第 一方向交替设置。
  10. 根据权利要求8或9所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，
    所述第一绝缘介质为二氧化硅，所述第二绝缘介质为氮氧化硅。
  11. 根据权利要求8-10任一项所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述第二绝缘介质第一方向的宽度为0.1μm-0.8μm。
  12. 根据权利要求8-11任一项所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述钝化层的厚度为0.1μm-0.3μm。
  13. 根据权利要求8-12任一项所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述钝化层中的所述第一绝缘介质和所述第二绝缘介质沿所述第一方向的宽度相等。
  14. 根据权利要求8-13任一项所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述在衬底的第一表面上沉积第一调制栅极之前，所述方法还包括：
    在所述衬底的第一表面上沉积所述第一绝缘介质。
  15. 根据权利要求8-14任一项所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述在所述第一绝缘介质上沉积钝化层之前，所述方法还包括：
    在所述第一调制栅极和所述衬底的第一表面上沉积第二调制栅极，使得所述第二调制栅极的一部分靠近所述漂移区的表面设置，另一部分设置在所述第一调制栅极的表面，所述第二调制栅极与所述钝化层连接。
  16. 根据权利要求15所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述在所述第一调制栅极和所述衬底的第一表面上沉积第二调制栅极之前，所述方法还包括：
    在所述第一调制栅极和所述衬底的第一表面上沉积所述第一绝缘介质。
  17. 根据权利要求8-14任一项所述的横向扩散金属氧化物半导体晶体管的制造方法，其特征在于，所述第一调制栅极的表面、所述漏区的表面设置有所述钝化层，其中，所述钝化层与所述第一调制栅极的表面之间设有所述第一绝缘介质。
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CN117012835B (zh) * 2023-10-07 2024-01-23 粤芯半导体技术股份有限公司 横向扩散金属氧化物半导体器件及其制造方法

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