WO2022037180A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2022037180A1
WO2022037180A1 PCT/CN2021/097750 CN2021097750W WO2022037180A1 WO 2022037180 A1 WO2022037180 A1 WO 2022037180A1 CN 2021097750 W CN2021097750 W CN 2021097750W WO 2022037180 A1 WO2022037180 A1 WO 2022037180A1
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Prior art keywords
trench
barrier layer
channel region
source
semiconductor substrate
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PCT/CN2021/097750
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English (en)
French (fr)
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李玉坤
陈涛
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长鑫存储技术有限公司
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Priority to EP21857280.8A priority Critical patent/EP4184589A4/en
Priority to US17/404,114 priority patent/US20220059695A1/en
Publication of WO2022037180A1 publication Critical patent/WO2022037180A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device and a preparation method thereof.
  • the gate of the transistor is placed on the silicon substrate, and the length of the channel is determined by the light
  • the engraving is defined, the source and drain need to be obliquely incident, and the transistor devices are mainly isolated by silicon oxide shallow trenches.
  • the gate of the transistor is placed on the silicon substrate, which leads to a significant increase in the risk of loading effect of etching.
  • the channel length defined by lithography cannot be flexibly fine-tuned according to the actual situation in the process (requires light Mask revision), the oblique incident doping of the source and drain is easily blocked by the photoresist, resulting in electrical failure, and the silicon oxide shallow trench isolation between transistor devices is easily affected by the subsequent cleaning process.
  • the technical problem to be solved by this application is to provide a semiconductor device and a preparation method thereof, which can avoid various drawbacks existing in the manufacturing process of traditional transistor devices and improve the performance of the semiconductor device.
  • the present application provides a method for fabricating a semiconductor device, which includes the following steps: providing a semiconductor substrate in which a plurality of trenches independent of each other are formed; A barrier layer is formed between the trenches; a gate structure is formed in the trench; a channel region is formed in the semiconductor substrate, and the channel region corresponds to the trench; A source-drain region is formed between the barrier layers, the source-drain region is electrically connected to the channel region, and the conductivity type of the barrier layer is opposite to that of the source-drain region.
  • the barrier layer in the step of forming a barrier layer between adjacent trenches, is disposed around the outer side of the trench, and there is a space between the barrier layer and the outer side of the trench. distance greater than zero.
  • the gate structure includes a gate insulating layer and a gate
  • the step of forming the gate structure in the trench further includes: forming a gate insulating material in the trench, the gate A very insulating material covers the sidewalls of the trench and the surface of the semiconductor substrate; a conductive material is filled in the trench, the conductive material fills the trench, and covers the gate insulation on the surface of the semiconductor substrate material; removing the conductive material and the gate insulating material on the surface of the semiconductor substrate to form a gate insulating layer and a gate located in the trench.
  • the step of forming a channel region in the semiconductor substrate further includes plasma implanting the semiconductor substrate to form the channel region.
  • the width of the channel region is greater than the width of the trench.
  • an annealing process is performed to extend the channel region upward along the trench sidewalls.
  • the plasma implantation depth is varied such that the channel region extends up the trench sidewalls.
  • the plasma for forming the barrier layer and the plasma for forming the channel region are ions of the same conductivity type.
  • the step of forming the source and drain regions further includes: performing plasma implantation on the semiconductor substrate to form shallowly doped drains and source and drain regions, so that The source and drain are electrically connected to the channel region through the shallowly doped drain.
  • the step includes the following step: forming a passivation layer, the passivation layer covering the surface of the semiconductor substrate and the entire surface of the semiconductor substrate. the surface of the gate structure.
  • the present application also provides a semiconductor device, which includes: a semiconductor substrate in which a plurality of independent trenches are formed; a barrier layer formed between adjacent trenches by a plasma implantation process; a gate structure is formed in the trench; a channel region is formed in the semiconductor substrate and corresponds to the trench; a source and drain region is arranged between the trench and the barrier layer, and In electrical connection with the channel region, the barrier layer has a conductivity type opposite to that of the source and drain regions.
  • the barrier layer is disposed around the outer side of the trench, and there is a space between the barrier layer and the outer side of the trench.
  • the gate structure includes a gate insulating layer covering sidewalls of the trench and a gate filling the trench.
  • the width of the channel region is greater than the width of the trench.
  • the channel region is disposed at the bottom of the trench and extends upward along the sidewalls of the trench.
  • a passivation layer is further included, and the passivation layer covers the surface of the semiconductor substrate and the surface of the gate structure.
  • the advantage of the embodiments of the present application is that, in the prior art, a shallow trench isolation structure is used as the isolation layer of the source and drain regions of adjacent transistors, and the shallow trench isolation structure is affected by subsequent cleaning and other processes, which will cause defects, so that there are The source regions are in contact due to surface tension, resulting in a short circuit in the active region.
  • the barrier layer formed by plasma implantation is used as an isolation layer for the source and drain regions of adjacent transistors.
  • a PN junction is formed between the source and drain regions and the blocking layer, and the built-in electric field of the PN junction can prevent the diffusion of electrons, thereby achieving the effect of isolation.
  • the preparation method of the present application avoids various drawbacks existing in the manufacturing process of traditional transistor devices, and improves the performance of semiconductor devices.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for manufacturing a semiconductor device of the present application
  • FIGS. 2 to 10 are process flow diagrams of an embodiment of a method for fabricating a semiconductor device of the present application.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for manufacturing a semiconductor device of the present application. Please refer to FIG. 1 .
  • the method for manufacturing a semiconductor device of the present application includes the following steps: Step S10 , providing a semiconductor substrate in which a semiconductor substrate is formed. multiple independent trenches; step S11, plasma implantation, forming a barrier layer between adjacent trenches; step S12, forming gate structures in the trenches; step S13, in the semiconductor substrate A channel region is formed, the channel region corresponds to the trench; step S14, a source and drain region is formed between the trench and the barrier layer, and the source and drain regions are electrically connected to the channel region. connect.
  • FIGS. 2 to 10 are process flow diagrams of an embodiment of a method for fabricating a semiconductor device of the present application.
  • a semiconductor substrate 200 is provided, and a plurality of trenches 210 independent of each other are formed in the semiconductor substrate 200 .
  • the semiconductor substrate 200 may be a semiconductor substrate such as silicon, germanium, or the like. In this embodiment, the semiconductor substrate 200 is described as a silicon substrate.
  • the trenches 210 can be formed by photolithography and etching processes. Specifically, in this step, a mask layer and a patterned photoresist layer are formed on the semiconductor substrate 200; the pattern of the photoresist layer is transferred to the mask layer; The film layer is a mask to etch the semiconductor substrate 200 to form the trench 210 ; after the trench 210 is formed, the mask layer is removed.
  • step S11 and FIG. 3 plasma implantation is performed to form barrier layers 220 between adjacent trenches 210 .
  • plasma implantation is performed on the semiconductor substrate 200 to form a barrier layer 220 in the semiconductor substrate 200 .
  • the barrier layer 220 serves as an isolation layer for the source and drain regions of adjacent transistors formed by the preparation method of the present application, so as to avoid electric leakage.
  • the semiconductor substrate 200 is not shielded, and the barrier layer 220 formed in the semiconductor substrate 200 is disposed around the outer side of the trench 210 , And the distance between the barrier layer 220 and the outer side surface of the trench 210 is greater than zero.
  • the distance between the barrier layer 220 and the outer side surface of the trench 210 and the thickness of the barrier layer 220 are determined by the properties of the semiconductor device finally formed. Wherein, the distance between the barrier layer 220 and the outer side of the trench 210 (ie, the plasma implantation can be adjusted by adjusting the energy of the plasma implantation, the implantation dose, the implanted element species and the grain boundary of the semiconductor substrate 200 ). depth) and the thickness of the barrier layer 220.
  • the plasma implantation process adopts vertical implantation, and the vertical implantation can make the barrier layer 220 evenly and symmetrically distributed on both sides of the trench 210 . If the barrier layers 220 are distributed asymmetrically on both sides of the trench 210 , for example, one side is closer to the trench and the other is farther away from the trench, the barrier layer 220 that is closer may overlap with the subsequently formed source and drain regions, resulting in failure.
  • the semiconductor substrate 200 is partially shielded, and only the region between the adjacent trenches 210 is exposed, and the width of the exposed region is is smaller than the width between the adjacent trenches 210, after the plasma implantation is performed, a barrier layer is only formed in the exposed area, and the barrier layer and the outer side surface of the trench have a gap greater than zero. distance, no barrier layer was formed in other areas.
  • the conductivity type of the plasma injected in this step is P-type, and if a P-type semiconductor device is to be formed, the conductivity type of the plasma injected in this step is N-type.
  • a shallow trench isolation structure is used as the isolation layer of the source and drain regions of adjacent transistors. Due to the influence of subsequent cleaning and other processes, the shallow trench isolation structure will cause defects, so that the active region is affected by surface tension. contact, resulting in a short circuit in the active area.
  • the barrier layer formed by plasma implantation is used as an isolation layer for the source and drain regions of adjacent transistors.
  • a PN junction is formed between the source and drain regions and the blocking layer, and the built-in electric field of the PN junction can prevent the diffusion of electrons, thereby achieving the effect of isolation. Wherein, the farther the distance between adjacent transistors is, the better the isolation effect of the barrier layer 220 is.
  • a gate structure 230 is formed in the trench 210 .
  • the gate structure 230 includes a gate insulating layer 231 and a gate 232 .
  • the method for forming the gate structure further includes the following steps:
  • a gate insulating material 400 is formed in the trench 210 , and the gate insulating material 400 covers the sidewall of the trench 210 and the surface of the semiconductor substrate 200 .
  • the gate insulating material 400 may be oxide or nitride.
  • the gate insulating material 400 may be formed by in-situ steam generation (ISSG), atomic layer deposition (ALD) or thermal oxidation.
  • the specific thickness of the gate insulating material is determined by the device voltage. For example, in this embodiment, the thickness of the gate insulating material 400 is 2 nm-10 nm.
  • the gate insulating material 400 is formed by an atomic layer deposition process, and the gate insulating material 400 is silicon oxide.
  • a conductive material 410 is filled in the trench 210 , the conductive material 410 fills the trench 210 , and covers the gate insulating material 400 on the surface of the semiconductor substrate 200 .
  • the conductive material 410 may be a conventional material for forming gates, eg, polysilicon.
  • the conductive material 400 may be formed using a low pressure chemical vapor deposition process (LPCVD).
  • the conductive material 410 and the gate insulating material 400 on the surface of the semiconductor substrate 200 are removed to form the gate insulating layer 231 and the gate electrode 232 in the trench 210 .
  • the steps of etching back, chemical mechanical polishing and cleaning may be used to remove the conductive material 410 and the gate insulating material 400 on the surface of the semiconductor substrate 200 .
  • the gate insulating layer 231 covers the sidewall of the trench 210
  • the gate 232 covers the gate insulating layer 231 and fills the trench 210 .
  • a channel region 240 is formed in the semiconductor substrate 200 , and the channel region 240 corresponds to the trench 210 .
  • the barrier layer 220 separates the semiconductor substrate into a plurality of regions, each region having a trench 210 in which a channel region 240 is formed within the semiconductor substrate 200 .
  • the channel region 240 is formed in the semiconductor substrate 200 under the trench 210 and is also formed in the semiconductor substrate 200 on the side of the trench 210, that is, the channel layer 240 extends upward along the sidewall of the trench 210 . It can be understood that, in order to form the source and drain regions subsequently, the channel region 240 is only formed on a part of the side surface of the trench 210 . In another embodiment of the present application, the channel region 240 may also be formed only in the semiconductor substrate 200 under the trench 210 .
  • a photoresist layer is used to partially shield the semiconductor substrate 200 to expose a region where a channel needs to be formed; plasma implantation is performed on the semiconductor substrate 200, The channel region 240 is formed.
  • the depth and thickness of the formed channel region 240 can be adjusted by controlling the energy of plasma implantation, the implanted dose, the types of implanted elements and the grain boundaries of the semiconductor substrate 200; by controlling the thickness of the photoresist layer
  • the width of the opening can control the width of the channel region 240 .
  • the plasma implantation process adopts vertical implantation, and the vertical implantation can make the channel region 240 be formed directly under the trench 210 and symmetrically distributed, thereby ensuring the channel length; if the plasma implantation process adopts If the incident is oblique, the formed channel region 240 may also be inclined, which may cause the source and drain regions to be unable to be electrically connected to the channel region, thereby affecting the performance of the device. Further, the width of the channel region 240 is greater than the width of the trench 210 to ensure the channel length. If the width of the channel region 240 is narrow, the source and drain regions need to be implanted at a deeper position to form an electrical connection, so that the channel length is too short, which affects the performance of the semiconductor device.
  • annealing is performed, so that the ions of the channel region 240 are diffused upward to form a channel region extending upward along the sidewall of the trench 210 .
  • the channel region 240 is disposed corresponding to the bottom and sides of the trench 210, so that the source and drain regions 250 (shown in FIG. 9) are in contact with the channel region 240, and the channel region 240 and the The overlapping area of the gate structures 230 increases the length of the channel (see FIG. 10 for the length H of the channel).
  • the plasma implantation depth is changed, so that the channel region 240 extends upward along the sidewall of the trench 210 . That is, as the depth of the trench 210 decreases, the plasma implantation depth gradually decreases to avoid injecting plasma into the gate structure 230 to form a channel region extending upward along the sidewall of the trench 210 . 240.
  • the groove depth at the bottom is the largest, and correspondingly, the depth of the plasma implantation is the largest, and the groove depth of the sidewalls gradually decreases, correspondingly, the plasma implantation depth gradually decreases. decrease.
  • the plasma for forming the barrier layer 220 and the plasma for forming the channel region 240 are ions of the same conductivity type. That is, the barrier layer 220 and the channel region 240 are of the same conductivity type.
  • the conductivity type of the plasma injected in this step is P-type.
  • the conductivity type of the plasma injected in this step is N-type.
  • a source-drain region 250 is formed, and the source-drain region 250 is electrically connected to the channel region 240 .
  • the fact that the source and drain regions 250 are electrically connected to the channel region 240 means that when a voltage is applied to the gate structure 230 , the channel region 240 is turned on, the carriers between the source and the drain flow, and further form a current.
  • the conductivity type of the source and drain regions 250 is opposite to that of the barrier layer 220 .
  • the conductivity type of the source-drain region 250 is N-type, and the conductivity type of the barrier layer 220 is P-type; if a P-type semiconductor device is to be formed, the source-drain region 250 is of N-type conductivity.
  • the conductivity type of the region 250 is P-type, and the conductivity type of the barrier layer 220 is N-type.
  • the source-drain regions 250 and the blocking layer 220 form a PN junction, and the built-in electric field of the PN junction prevents electrons from diffusing, thereby achieving an isolation effect.
  • a structure such as a photoresist layer is used to partially shield the semiconductor substrate 200 , and only the regions where the source and drain regions 250 need to be formed are exposed, that is, the gap between the trench 210 and the barrier layer 220 is exposed.
  • plasma implantation is performed on the exposed region of the semiconductor substrate 200 to form the source and drain regions 250 .
  • the depth and width of the source and drain regions 250 are determined by the performance of the semiconductor device, and the source and drain regions 250 can be adjusted by adjusting the plasma implantation energy, implantation dose, implanted element species and grain boundaries of the semiconductor substrate 200 . depth and concentration.
  • the source and drain regions are formed by oblique incidence doping, and the oblique incidence doping is easily blocked by the photoresist layer above it, resulting in electrical failure.
  • the source and drain regions 250 are formed by a plasma implantation process, and there is no oblique incident doping and no shielding by the photoresist layer, so that electrical failure is not caused, and the performance of the semiconductor device is improved.
  • the source-drain region 250 includes a shallow-doped drain 251 and a source-drain 252 .
  • the source and drain 252 are electrically connected to the channel region 240 through the shallowly doped drain 251 , that is, the shallowly doped drain 251 is located below the source and drain 252 and is connected to the channel region 240 electrical connection.
  • the shallow doped drain 251 can be formed through a plasma implantation process first, and then the parameters of the plasma implantation can be changed to form the source drain 252 . Both the shallowly doped drain 251 and the source and drain 252 can be formed by a plasma implantation process.
  • the shallowly doped drain and the source and drain are formed by multiple oblique incident doping methods.
  • the shallow-doped drain 251 and the source-drain 252 formed by the preparation method of the present application have better conductivity.
  • the step includes the following steps: forming a passivation layer 260 , and the passivation layer 260 covers the The surface of the semiconductor substrate 200 and the surface of the gate structure 230 .
  • the passivation layer 260 is used to isolate the gate structure 230 from the outside world and play a protective role.
  • the passivation layer 260 includes, but is not limited to, nitrides, such as silicon nitride, which may be formed using a low pressure chemical vapor deposition process (LPCVD).
  • the length of the channel is usually defined by the photolithography process. If the electrical properties of the formed semiconductor device are not good and the channel length needs to be adjusted, the mask needs to be redesigned, and the cost of modifying the mask is relatively high. , time-consuming and expensive; and the length of the channel of the semiconductor device formed by the preparation method of the present application (as shown in H in FIG. 10 ) can be determined by the depth of the trench 210 and the depth of the source and drain regions 250 , and can directly pass through the trench 210 The etching depth and the plasma implantation depth of the source and drain regions 250 can adjust the length of the channel, which can be fine-tuned at any time, which greatly reduces the production cost and takes less time. In addition, the preparation method of the present application can reduce the number of masks and save process steps.
  • the present application also provides a semiconductor device prepared by the above preparation method.
  • the semiconductor device includes a semiconductor substrate 200 , a barrier layer 220 , a gate structure 230 , a channel region 240 and a source-drain region 250 .
  • the gate structure 230, the channel region 240 and the source and drain regions 250 form a transistor.
  • the semiconductor substrate 200 is formed with a plurality of trenches 210 which are independent of each other.
  • the semiconductor substrate 200 may be a substrate of silicon, germanium, or the like. In this embodiment, the semiconductor substrate 200 is a silicon substrate.
  • the barrier layer 220 is formed between adjacent trenches 210 through a plasma implantation process.
  • the blocking layer 220 serves as an isolation layer between adjacent transistors. There is a gap between the trench 210 and the barrier layer 220 .
  • the barrier layer 220 is disposed around the outer side of the trench 210 , and the interval between the barrier layer 220 and the outer side of the trench 210 is greater than zero.
  • the blocking layer 220 is only formed between adjacent transistors, rather than surrounding the outer side of the trench 210 .
  • the gate structure 230 is formed in the trench 210 .
  • the gate structure 230 includes a gate insulating layer 231 covering the sidewall of the trench 210 and a gate 232 filling the trench 210 .
  • the gate insulating layer 231 serves as an isolation layer between the gate electrode 232 , the channel region 240 and the source and drain regions 250 .
  • the channel region 240 is formed in the semiconductor substrate 200 and corresponds to the trench 210 .
  • the channel region 250 is disposed at the bottom of the trench 210 and extends upward along the sidewall of the trench 210 . It can be understood that, in order to provide sufficient formation space for the source and drain regions 250 , the channel region 240 is only formed on a part of the side surface of the trench 210 . In another embodiment of the present application, the channel region 240 may also be formed only in the semiconductor substrate 200 under the trench 210 .
  • the width of the channel region 240 is greater than the width of the trench 210 to increase the contact area between the source and drain regions 250 and the channel region 240 . If the width of the channel region 240 is narrow, the source and drain regions need to be formed at a deeper position, resulting in an excessively short channel length, which affects the performance of the semiconductor device.
  • the source and drain regions 250 are disposed between the trenches 210 and the barrier layer 220 and are electrically connected to the channel regions 240 .
  • the source and drain regions 250 are formed in spaced regions between the trenches 210 and the barrier layer 220 .
  • the conductivity type of the barrier layer 220 is opposite to that of the source and drain regions 250 .
  • the conductivity type of the source-drain region 250 is N-type, and the conductivity type of the barrier layer 220 is P-type; if a P-type semiconductor device is to be formed, the source-drain region 250 is of N-type conductivity.
  • the conductivity type of the region 250 is P-type, and the conductivity type of the barrier layer 220 is N-type.
  • the source-drain regions 250 and the blocking layer 220 form a PN junction, and the built-in electric field of the PN junction prevents electrons from diffusing, thereby achieving an isolation effect.
  • the source-drain region 250 includes a shallow-doped drain 251 and a source-drain 252 .
  • the source and drain 252 are electrically connected to the channel region 240 through the shallowly doped drain 251 , that is, the shallowly doped drain 251 is located below the source and drain 252 and is connected to the channel region 240 electrical connection.
  • the semiconductor device further includes a passivation layer 260 covering the surface of the semiconductor substrate 200 and the surface of the gate structure 230 .
  • the passivation layer 260 is used to isolate the gate structure 230 from the outside world and play a protective role.
  • the passivation layer 260 includes, but is not limited to, nitrides such as silicon nitride.
  • the semiconductor device of the present application has good electrical performance, simple preparation and low process cost.
  • a plurality of trenches independent of each other are formed in the semiconductor substrate; plasma implantation, a barrier layer is formed between adjacent trenches; and a barrier layer is formed in the trenches a gate structure; a channel region is formed in the semiconductor substrate, the channel region corresponds to the trench; a source-drain region is formed between the trench and the barrier layer, and the source-drain region is formed A region is electrically connected to the channel region, and the barrier layer has a conductivity type opposite to that of the source and drain regions.
  • the barrier layer formed by plasma implantation is used as an isolation layer for the source and drain regions of adjacent transistors.
  • a PN junction is formed between the barrier layers, and the built-in electric field of the PN junction can prevent the diffusion of electrons, thereby achieving an isolation effect.

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Abstract

本申请提供一种半导体器件及其制备方法，制备方法包括如下步骤：提供半导体衬底，所述半导体衬底中形成有多个彼此独立的沟槽；等离子体注入，在相邻沟槽之间形成阻挡层；在所述沟槽内形成栅极结构；在所述半导体衬底内形成沟道区，所述沟道区与所述沟槽对应；在所述沟槽与所述阻挡层之间，形成源漏区，所述源漏区与所述沟道区电连接，所述阻挡层的导电类型与所述源漏区的导电类型相反。本申请优点是，无需形成浅沟槽隔离结构，通过等离子体注入形成的阻挡层作为相邻晶体管的源漏区的隔离层，由于源漏区与阻挡层注入的是反型离子，因此在源漏区与阻挡层之间形成PN结，PN结的内建电场可以阻止电子的扩散，进而起到了隔离的效果。

Description

半导体器件及其制备方法
相关申请的交叉引用
本申请要求在2020年08月21日提交中国专利局、申请号为202010848727.0、申请名称为“半导体器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造领域，尤其涉及一种半导体器件及其制备方法。
背景技术
随着半导体技术向高度集成化的演进，同等大小的芯片内部集成了越来越多的晶体管器件，传统的集成电路布局中，晶体管的栅极置于硅衬底之上，通道的长度由光刻定义，源漏极需斜入射完成，晶体管器件之间主要通过氧化硅浅槽隔离。
然而，芯片尺寸微缩以及集成度的提高，晶体管的栅极置于硅衬底之上导致蚀刻的负载效应风险显著增加，由光刻定义的通道长度无法根据制程中的实际情况灵活微调(需光罩改版)，源漏极的斜入射掺杂容易被光阻遮挡导致电性失效，晶体管器件之间的氧化硅浅槽隔离由于受后续清洗制程的影响容易产生凹槽造成栅极或导线短路。
因此，需要改进制程工艺，规避传统晶体管器件在制程中存在的多种弊端。
发明内容
本申请所要解决的技术问题是，提供一种半导体器件及其制备方法，其规避传统晶体管器件在制程中存在的多种弊端，提高半导体器件性能。
为了解决上述问题，本申请提供了一种半导体器件的制备方法，其包括如下步骤：提供半导体衬底，所述半导体衬底中形成有多个彼此独立的沟槽；等 离子体注入，在相邻沟槽之间形成阻挡层；在所述沟槽内形成栅极结构；在所述半导体衬底内形成沟道区，所述沟道区与所述沟槽对应；在所述沟槽与所述阻挡层之间，形成源漏区，所述源漏区与所述沟道区电连接，所述阻挡层的导电类型与所述源漏区的导电类型相反。
在一些实施例中，在相邻沟槽之间形成阻挡层的步骤中，所述阻挡层围绕所述沟槽的外侧面设置，且所述阻挡层与所述沟槽的外侧面之间具有大于零的距离。
在一些实施例中，所述栅极结构包括栅极绝缘层及栅极，在所述沟槽内形成栅极结构的步骤进一步包括：在所述沟槽内形成栅极绝缘材料，所述栅极绝缘材料覆盖所述沟槽侧壁及所述半导体衬底表面；在所述沟槽内填充导电材料，所述导电材料充满所述沟槽，且覆盖所述半导体衬底表面的栅极绝缘材料；去除半导体衬底表面的导电材料及栅极绝缘材料，形成位于所述沟槽内的形成栅极绝缘层及栅极。
在一些实施例中，在所述半导体衬底内形成沟道区的步骤进一步包括，对所述半导体衬底进行等离子体注入，形成所述沟道区。
在一些实施例中，沟道区的宽度大于所述沟槽的宽度。
在一些实施例中，等离子体注入后，进行退火处理，以使沟道区沿所述沟槽侧壁向上延伸。
在一些实施例中，改变等离子体注入深度，以使沟道区沿所述沟槽侧壁向上延伸。
在一些实施例中，形成所述阻挡层的等离子体与形成所述沟道区的等离子体为同种导电类型离子。
在一些实施例中，在所述沟槽与所述阻挡层之间，形成源漏区的步骤进一步包括：对所述半导体衬底进行等离子体注入，形成浅掺杂漏及源漏极，所述源漏极通过所述浅掺杂漏与所述沟道区电连接。
在一些实施例中，在所述沟槽与所述阻挡层之间，形成源漏区的步骤之后，包括如下步骤：形成钝化层，所述钝化层覆盖所述半导体衬底表面及所述栅极 结构表面。
本申请还提供一种半导体器件，其包括：半导体衬底，所述半导体衬底中形成有多个彼此独立的沟槽；阻挡层，通过等离子体注入工艺形成在相邻的沟槽之间；栅极结构，形成在所述沟槽内；沟道区，形成在半导体衬底中，且与所述沟槽对应；源漏区，设置在所述沟槽与所述阻挡层之间，且与所述沟道区电连接，所述阻挡层的导电类型与所述源漏区的导电类型相反。
在一些实施例中，所述阻挡层围绕所述沟槽的外侧面设置，且所述阻挡层与所述沟槽的外侧面之间具有间隔。
在一些实施例中，所述栅极结构包括覆盖所述沟槽侧壁的栅极绝缘层及填充所述沟槽的栅极。
在一些实施例中，沟道区的宽度大于所述沟槽的宽度。
在一些实施例中，所述沟道区设置在所述沟槽底部，且沿所述沟槽侧壁向上延伸。
在一些实施例中，还包括钝化层，所述钝化层覆盖所述半导体衬底表面及所述栅极结构表面。
本申请实施例的优点在于，现有技术中，采用浅沟槽隔离结构作为相邻晶体管的源漏区的隔离层，浅沟槽隔离结构受后续清洗等制程的影响，会产生缺陷，使得有源区因表面张力的作用而接触，造成有源区短路。而本申请无需形成浅沟槽隔离结构进行隔离，其通过等离子体注入形成的阻挡层作为相邻晶体管的源漏区的隔离层，由于源漏区与阻挡层注入的是反型离子，因此在源漏区与阻挡层之间形成PN结，PN结的内建电场可以阻止电子的扩散，进而起到了隔离的效果。本申请制备方法规避了传统晶体管器件在制程中存在的多种弊端，提高半导体器件性能。
附图说明
图1是本申请半导体器件的制备方法的一实施例的步骤示意图；
图2～图10是本申请半导体器件的制备方法的一实施例的工艺流程图。
具体实施方式
下面结合附图对本申请提供的半导体器件及其制备方法的具体实施方式做详细说明。
图1是本申请半导体器件的制备方法的一实施例的步骤示意图，请参阅图1，本申请半导体器件的制备方法包括如下步骤：步骤S10，提供半导体衬底，所述半导体衬底中形成有多个彼此独立的沟槽；步骤S11，等离子体注入，在相邻沟槽之间形成阻挡层；步骤S12，在所述沟槽内形成栅极结构；步骤S13，在所述半导体衬底内形成沟道区，所述沟道区与所述沟槽对应；步骤S14，在所述沟槽与所述阻挡层之间，形成源漏区，所述源漏区与所述沟道区电连接。
图2～图10是本申请半导体器件的制备方法的一实施例的工艺流程图。
请参阅步骤S10及图2，提供半导体衬底200，所述半导体衬底200中形成有多个彼此独立的沟槽210。所述半导体衬底200可为硅、锗等半导体衬底。在本实施例中，以所述半导体衬底200为硅衬底进行描述。
在该步骤中，可采用光刻及刻蚀工艺形成所述沟槽210。具体地说，在该步骤中，在所述半导体衬底200上形成掩膜层及图形化的光阻层；将所述光阻层的图案转移到所述掩膜层上；以所述掩膜层为掩膜刻蚀所述半导体衬底200，形成所述沟槽210；形成所述沟槽210后去除所述掩膜层。
请参阅步骤S11及图3，等离子体注入，在相邻沟槽210之间形成阻挡层220。在该步骤中，对所述半导体衬底200进行等离子体注入，在所述半导体衬底200内形成阻挡层220。所述阻挡层220作为本申请制备方法形成的相邻的晶体管的源漏区的隔离层，从而避免漏电。
在本实施例中，在进行等离子体注入工艺时，未对所述半导体衬底200进行遮挡，则在所述半导体衬底200内形成的阻挡层220围绕所述沟槽210的外侧面设置，且所述阻挡层220与所述沟槽210的外侧面之间具有大于零的距离。所述阻挡层220与所述沟槽210的外侧面的距离及所述阻挡层220的厚度由最终形成的半导体器件的性能决定。其中，可通过调整等离子体注入的能量、注 入的剂量、注入的元素种类及半导体衬底200的晶界等调整所述阻挡层220与所述沟槽210的外侧面的距离(即等离子体注入的深度)及所述阻挡层220的厚度。
进一步，在本实施例中，所述等离子体注入工艺采用垂直注入，垂直注入可以使阻挡层220在沟槽210两边均匀对称分布。若在沟槽210两边所述阻挡层220分布不对称，例如一边距离沟槽较近一边距离沟槽较远，则距离较近的阻挡层220有可能与后续形成的源漏区域重叠导致失效。
在本申请另一实施例中，在进行等离子体注入工艺时，对所述半导体衬底200进行部分遮挡，仅暴露相邻的所述沟槽210之间的区域，且所述暴露区域的宽度小于相邻的所述沟槽210之间的宽度，则进行等离子体注入后，仅在所述暴露区域形成阻挡层，且所述阻挡层与所述沟槽的外侧面之间具有大于零的距离，在其他区域未形成阻挡层。
若要形成N型半导体器件，则在该步骤中注入的等离子体的导电类型为P型，若要形成P型半导体器件，则在该步骤中注入的等离子体的导电类型为N型。
现有技术中，采用浅沟槽隔离结构作为相邻晶体管的源漏区的隔离层，浅沟槽隔离结构由于受后续清洗等制程的影响，会产生缺陷，使得有源区因表面张力的作用而接触，造成有源区短路。而本申请无需形成浅沟槽隔离结构进行隔离，其通过等离子体注入形成的阻挡层作为相邻晶体管的源漏区的隔离层，由于源漏区与阻挡层注入的是反型离子，因此在源漏区与阻挡层之间形成PN结，PN结的内建电场可以阻止电子的扩散，进而起到了隔离的效果。其中，相邻的晶体管之间的距离越远，所述阻挡层220的隔离作用越好。
请参阅步骤S12及图6，在所述沟槽210内形成栅极结构230。
所述栅极结构230包括栅极绝缘层231及栅极232。则在本实施例中，形成所述栅极结构的方法进一步包括如下步骤：
请参阅图4，在所述沟槽210内形成栅极绝缘材料400，所述栅极绝缘材料400覆盖所述沟槽210侧壁及所述半导体衬底200表面。所述栅极绝缘材料400 可为氧化物或者氮化物。其中，可以采用原位水汽生成(in-situ steam generation，ISSG)、原子层沉积工艺(ALD)或者热氧化工艺形成所述栅极绝缘材料400。所述栅极绝缘材料的具体厚度由器件电压决定，例如，在本实施例中，所述栅极绝缘材料400的厚度为2nm-10nm。在本实施例中，采用原子层沉积工艺形成所述栅极绝缘材料400，所述栅极绝缘材料400为氧化硅。
请参阅图5，在所述沟槽210内填充导电材料410，所述导电材料410充满所述沟槽210，且覆盖所述半导体衬底200表面的栅极绝缘材料400。所述导电材料410可为形成栅极的常规材料，例如，多晶硅。在该步骤中，可采用低压化学气相沉积工艺(LPCVD)形成所述导电材料400。
请参阅图6，去除半导体衬底200表面的导电材料410及栅极绝缘材料400，形成位于所述沟槽210内的栅极绝缘层231及栅极232。具体地说，在该步骤中，可采用回刻、化学机械研磨及清洗的步骤去除半导体衬底200表面的导电材料410及栅极绝缘材料400。所述栅极绝缘层231覆盖所述沟槽210侧壁，所述栅极232覆盖所述栅极绝缘层231且充满所述沟槽210。
请参阅步骤S13及图7，在所述半导体衬底200内形成沟道区240，所述沟道区240与所述沟槽210对应。所述阻挡层220将所述半导体衬底分隔为多个区域，每一区域具有沟槽210，在该区域，在半导体衬底200内形成沟道区240。
在本实施例中，所述沟道区240形成在所述沟槽210下方的半导体衬底200中，同时还形成在所述沟槽210侧面的半导体衬底200中，即所述沟道层240沿所述沟槽210侧壁向上延伸。可以理解的是，为了后续形成源漏区，所述沟道区240仅形成在所述沟槽210的部分侧面。而在本申请另一实施例中，所述沟道区240也可仅形成在所述沟槽210下方的半导体衬底200中。
进一步，在本实施例中，如图7所示，对所述半导体衬底200采用光阻层进行部分遮挡，暴露出需要形成沟道的区域；对所述半导体衬底200进行等离子体注入，形成所述沟道区240。其中，通过控制等离子体注入的能量、注入的剂量、注入的元素种类及半导体衬底200的晶界等可以调整形成的所述沟道区240的深度及厚度；通过控制所述光阻层的开口宽度可以控制所述沟道区240 的宽度。
进一步，在本实施例中，所述等离子体注入工艺采用垂直注入，垂直注入可以使沟道区240形成在沟槽210的正下方且对称分布，进而保证沟道长度；若等离子体注入工艺采用倾斜入射，则所形成的沟道区240也可能是倾斜的，有可能导致源漏区与沟道区无法电连接，影响器件性能。进一步，所述沟道区240的宽度大于所述沟槽210的宽度，以保证沟道长度。若所述沟道区240的宽度较窄，则源漏区需要注入在更深的位置以形成电连接，使得沟道长度过短，影响半导体器件性能。
进一步，请参阅图8，在本实施例中，在进行等离子体注入后，进行退火处理，以使沟道区240的离子向上扩散，形成沿所述沟槽210侧壁向上延伸的沟道区240。所述沟道区240对应所述沟槽210的底部及侧面设置，以使源漏区250(绘示于图9中)与所述沟道区240接触，同时增加所述沟道区240与所述栅极结构230的重叠面积，进而增加沟道的长度(所述沟道的长度H请参阅图10所示)。
在本申请另一实施例中，改变等离子体注入深度，以使沟道区240沿所述沟槽210侧壁向上延伸。即随着所述沟槽210深度的减小，等离子体注入深度逐渐减小，以避免在所述栅极结构230中注入等离子体，形成沿所述沟槽210侧壁向上延伸的沟道区240。例如，对于侧壁倾斜的沟槽210，其底部的沟槽深度最大，则对应地，等离子体注入的深度最大，其侧壁的沟槽深度逐渐减小，则对应地，等离子体注入深度逐渐减小。
进一步，形成所述阻挡层220的等离子体与形成所述沟道区240的等离子体为同种导电类型离子。即所述阻挡层220与所述沟道区240为同种导电类型，例如，若要形成N型半导体器件，则在该步骤中注入的等离子体的导电类型为P型，若要形成P型半导体器件，则在该步骤中注入的等离子体的导电类型为N型。
请参阅步骤S14及图9，在所述沟槽210与所述阻挡层220之间，形成源漏区250，所述源漏区250与所述沟道区240电连接。所述源漏区250与所述 沟道区240电连接是指，当对所述栅极结构230施加电压时，所述沟道区240导通，源漏之间的载流子流动，进而形成电流。
所述沟槽210与所述阻挡层220之间具有一间隔，该间隔用于形成源漏区250。所述源漏区250的导电类型与所述阻挡层220的导电类型相反。例如，若要形成N型半导体器件，则所述源漏区250的导电类型为N型，而所述阻挡层220的导电类型为P型；若要形成P型半导体器件，则所述源漏区250的导电类型为P型，而所述阻挡层220的导电类型为N型。所述源漏区250与所述阻挡层220形成PN结，PN结的内建电场防止电子扩散，起到隔离效果。
进一步，在本实施例中，采用光阻层等结构对半导体衬底200进行部分遮挡，仅暴露需要形成源漏区250的区域，即暴露出所述沟槽210与所述阻挡层220之间的间隔区域，对所述半导体衬底200暴露的区域进行等离子体注入，形成源漏区250。所述源漏区250的深度及宽度由半导体器件的性能决定，可通过调整等离子体注入的能量、注入的剂量、注入的元素种类及半导体衬底200的晶界等调整所述源漏区250的深度及浓度。
在现有技术中，源漏区采用斜入射掺杂的方法形成，而斜入射掺杂容易被其上方的光阻层遮挡，导致电性失效。而本申请制备方法通过等离子体注入工艺形成所述源漏区250，不存在斜入射掺杂，也不会被光阻层遮挡，从而不会导致电性失效，提高了半导体器件的性能。
进一步，在本实施例中，所述源漏区250包括浅掺杂漏251及源漏极252。所述源漏极252通过所述浅掺杂漏251与所述沟道区240电连接，即所述浅掺杂漏251位于所述源漏极252的下方，其与所述沟道区240电连接。在本实施例中，可先通过等离子体注入工艺形成所述浅掺杂漏251，再改变等离子体注入的参数，形成所述源漏极252。所述浅掺杂漏251及所述源漏极252均可通过等离子体注入工艺形成，相较于现有技术中分多次采用斜入射掺杂的方法形成浅掺杂漏及源漏极而言，本申请制备方法形成所述浅掺杂漏251及源漏极252导电性能更好。
进一步，请参阅图10，在所述沟槽210与所述阻挡层220之间，形成源漏 区150的步骤之后，包括如下步骤：形成钝化层260，所述钝化层260覆盖所述半导体衬底200表面及所述栅极结构230表面。所述钝化层260用于将栅极结构230与外界隔离，并起到保护作用。所述钝化层260包括但不限于氮化物，例如氮化硅，其可采用低压化学气相沉积工艺(LPCVD)形成。
在现有技术中，沟道的长度通常由光刻工艺定义，若形成的半导体器件的电性不好，需要调整沟道长度时，就需要重新制定光罩，而修改光罩的成本较高，耗时费钱；而采用本申请制备方法形成的半导体器件，其沟道的长度(如图10中H)可由沟槽210的深度及源漏区250的深度决定，可以直接通过沟槽210的刻蚀深度和源漏区250的等离子体注入深度调节沟道的长度，可随时进行微调，大大降低了生产成本，且耗时短。另外，本申请制备方法能够减少光罩，节省工艺步骤。
本申请还提供一种采用上述制备方法制备的半导体器件。请参阅图10，在本申请半导体器件的一实施例中，所述半导体器件包括半导体衬底200、阻挡层220、栅极结构230、沟道区240及源漏区250。所述栅极结构230、沟道区240及源漏区250形成一个晶体管。
所述半导体衬底200形成有多个彼此独立的沟槽210。所述半导体衬底200可为硅、锗等衬底。在本实施例中，所述半导体衬底200为硅衬底。
所述阻挡层220通过等离子体注入工艺形成在相邻的沟槽210之间。所述阻挡层220作为相邻的晶体管之间的隔离层。所述沟槽210与所述阻挡层220之间具有一间隔。在本实施例中，所述阻挡层220围绕所述沟槽210的外侧面设置，且所述阻挡层220与所述沟槽210的外侧面之间的间隔大于零。在本申请另一实施例中，所述阻挡层220仅形成在相邻的晶体管之间，而并非是围绕所述沟槽210的外侧面。
所述栅极结构230形成在所述沟槽210内。其中，所述栅极结构230包括覆盖所述沟槽210侧壁的栅极绝缘层231及填充所述沟槽210的栅极232。所述栅极绝缘层231作为所述栅极232与所述沟道区240及所述源漏区250的隔离层。
所述沟道区240形成在半导体衬底200中，且与所述沟槽210对应。在本实施例中，所述沟道区250设置在所述沟槽210底部，且沿所述沟槽210侧壁向上延伸。可以理解的是，为了给源漏区250提供足够的形成空间，所述沟道区240仅形成在所述沟槽210的部分侧面。而在本申请另一实施例中，所述沟道区240也可仅形成在所述沟槽210下方的半导体衬底200中。
进一步，所述沟道区240的宽度大于所述沟槽210的宽度，以增大源漏区250与所述沟道区240的接触面积。若所述沟道区240的宽度较窄，则源漏区需要形成在更深的位置，造成沟道长度过短，影响半导体器件性能。
所述源漏区250设置在所述沟槽210与所述阻挡层220之间，且与所述沟道区240电连接。所述源漏区250形成在所述沟槽210与所述阻挡层220之间的间隔区域。所述阻挡层220的导电类型与所述源漏区250的导电类型相反。例如，若要形成N型半导体器件，则所述源漏区250的导电类型为N型，而所述阻挡层220的导电类型为P型；若要形成P型半导体器件，则所述源漏区250的导电类型为P型，而所述阻挡层220的导电类型为N型。所述源漏区250与所述阻挡层220形成PN结，PN结的内建电场防止电子扩散，起到隔离效果。
进一步，在本实施例中，所述源漏区250包括浅掺杂漏251及源漏极252。所述源漏极252通过所述浅掺杂漏251与所述沟道区240电连接，即所述浅掺杂漏251位于所述源漏极252的下方，其与所述沟道区240电连接。
进一步，所述半导体器件还包括钝化层260，所述钝化层260覆盖所述半导体衬底200表面及所述栅极结构230表面。所述钝化层260用于将栅极结构230与外界隔离，并起到保护作用。所述钝化层260包括但不限于氮化物，例如氮化硅。
本申请半导体器件电学性能好，且制备简单，工艺成本低。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。
工业实用性：
本申请实施例中，通过提供半导体衬底，所述半导体衬底中形成有多个彼此独立的沟槽；等离子体注入，在相邻沟槽之间形成阻挡层；在所述沟槽内形成栅极结构；在所述半导体衬底内形成沟道区，所述沟道区与所述沟槽对应；在所述沟槽与所述阻挡层之间，形成源漏区，所述源漏区与所述沟道区电连接，所述阻挡层的导电类型与所述源漏区的导电类型相反。这样，无需形成浅沟槽隔离结构，通过等离子体注入形成的阻挡层作为相邻晶体管的源漏区的隔离层，由于源漏区与阻挡层注入的是反型离子，因此在源漏区与阻挡层之间形成PN结，PN结的内建电场可以阻止电子的扩散，进而起到了隔离的效果。

Claims (16)

  1. 一种半导体器件的制备方法，包括如下步骤：
    提供半导体衬底，所述半导体衬底中形成有多个彼此独立的沟槽；
    等离子体注入，在相邻沟槽之间形成阻挡层；
    在所述沟槽内形成栅极结构；
    在所述半导体衬底内形成沟道区，所述沟道区与所述沟槽对应；
    在所述沟槽与所述阻挡层之间，形成源漏区，所述源漏区与所述沟道区电连接，所述阻挡层的导电类型与所述源漏区的导电类型相反。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，在相邻沟槽之间形成阻挡层的步骤中，所述阻挡层围绕所述沟槽的外侧面设置，且所述阻挡层与所述沟槽的外侧面之间具有大于零的距离。
  3. 根据权利要求1所述的半导体器件的制备方法，其中，所述栅极结构包括栅极绝缘层及栅极，在所述沟槽内形成栅极结构的步骤进一步包括：
    在所述沟槽内形成栅极绝缘材料，所述栅极绝缘材料覆盖所述沟槽侧壁及所述半导体衬底表面；
    在所述沟槽内填充导电材料，所述导电材料充满所述沟槽，且覆盖所述半导体衬底表面的栅极绝缘材料；
    去除半导体衬底表面的导电材料及栅极绝缘材料，形成位于所述沟槽内的栅极绝缘层及栅极。
  4. 根据权利要求1所述的半导体器件的制备方法，其中，在所述半导体衬底内形成沟道区的步骤进一步包括，对所述半导体衬底进行等离子体注入，形成所述沟道区。
  5. 根据权利要求4所述的半导体器件的制备方法，其中，沟道区的宽度大于所述沟槽的宽度。
  6. 根据权利要求5所述的半导体器件的制备方法，其中，等离子体注入后，进行退火处理，以使沟道区沿所述沟槽侧壁向上延伸。
  7. 根据权利要求5所述的半导体器件的制备方法，其中，改变等离子体注入深度，以使沟道区沿所述沟槽侧壁向上延伸。
  8. 根据权利要求4所述的半导体器件的制备方法，其中，形成所述阻挡层的等离子体与形成所述沟道区的等离子体为同种导电类型离子。
  9. 根据权利要求1所述的半导体器件的制备方法，其中，在所述沟槽与所述阻挡层之间，形成源漏区的步骤进一步包括：对所述半导体衬底进行等离子体注入，形成浅掺杂漏及源漏极，所述源漏极通过所述浅掺杂漏与所述沟道区电连接。
  10. 根据权利要求1所述的半导体器件的制备方法，其中，在所述沟槽与所述阻挡层之间，形成源漏区的步骤之后，包括如下步骤：形成钝化层，所述钝化层覆盖所述半导体衬底表面及所述栅极结构表面。
  11. 一种半导体器件，包括：
    半导体衬底，所述半导体衬底中形成有多个彼此独立的沟槽；
    阻挡层，通过等离子体注入工艺形成在相邻的沟槽之间；
    栅极结构，形成在所述沟槽内；
    沟道区，形成在半导体衬底中，且与所述沟槽对应；
    源漏区，设置在所述沟槽与所述阻挡层之间，且与所述沟道区电连接，所述阻挡层的导电类型与所述源漏区的导电类型相反。
  12. 根据权利要求11所述的半导体器件，其中，所述阻挡层围绕所述沟槽的外侧面设置，且所述阻挡层与所述沟槽的外侧面之间具有间隔。
  13. 根据权利要求11所述的半导体器件，其中，所述栅极结构包括覆盖所述沟槽侧壁的栅极绝缘层及填充所述沟槽的栅极。
  14. 根据权利要求11所述的半导体器件，其中，沟道区的宽度大于所述沟槽的宽度。
  15. 根据权利要求11所述的半导体器件，其中，所述沟道区设置在所述沟槽底部，且沿所述沟槽侧壁向上延伸。
  16. 根据权利要求11所述的半导体器件，其中，还包括钝化层，所述钝化 层覆盖所述半导体衬底表面及所述栅极结构表面。
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