CN114078764A - 半导体器件及其制备方法 - Google Patents
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Abstract
本发明提供一种半导体器件及其制备方法,制备方法包括如下步骤:提供半导体衬底,所述半导体衬底中形成有多个彼此独立的沟槽;等离子体注入,在相邻沟槽之间形成阻挡层;在所述沟槽内形成栅极结构;在所述半导体衬底内形成沟道区,所述沟道区与所述沟槽对应;在所述沟槽与所述阻挡层之间,形成源漏区,所述源漏区与所述沟道区电连接,所述阻挡层的导电类型与所述源漏区的导电类型相反。本发明优点是,无需形成浅沟槽隔离结构,通过等离子体注入形成的阻挡层作为相邻晶体管的源漏区的隔离层,由于源漏区与阻挡层注入的是反型离子,因此在源漏区与阻挡层之间形成PN结,PN结的内建电场可以阻止电子的扩散,进而起到了隔离的效果。
Description
技术领域
本发明涉及半导体制造领域,尤其涉及一种半导体器件及其制备方法。
背景技术
随着半导体技术向高度集成化的演进,同等大小的芯片内部集成了越来越多的晶体管器件,传统的集成电路布局中,晶体管的栅极置于硅衬底之上,通道的长度由光刻定义,源漏极需斜入射完成,晶体管器件之间主要通过氧化硅浅槽隔离。
然而,芯片尺寸微缩以及集成度的提高,晶体管的栅极置于硅衬底之上导致蚀刻的负载效应风险显著增加,由光刻定义的通道长度无法根据制程中的实际情况灵活微调(需光罩改版),源漏极的斜入射掺杂容易被光阻遮挡导致电性失效,晶体管器件之间的氧化硅浅槽隔离由于受后续清洗制程的影响容易产生凹槽造成栅极或导线短路。
因此,需要改进制程工艺,规避传统晶体管器件在制程中存在的多种弊端。
发明内容
本发明所要解决的技术问题是,提供一种半导体器件及其制备方法,其规避传统晶体管器件在制程中存在的多种弊端,提高半导体器件性能。
为了解决上述问题,本发明提供了一种半导体器件的制备方法,其包括如下步骤:提供半导体衬底,所述半导体衬底中形成有多个彼此独立的沟槽;等离子体注入,在相邻沟槽之间形成阻挡层;在所述沟槽内形成栅极结构;在所述半导体衬底内形成沟道区,所述沟道区与所述沟槽对应;在所述沟槽与所述阻挡层之间,形成源漏区,所述源漏区与所述沟道区电连接,所述阻挡层的导电类型与所述源漏区的导电类型相反。
进一步,在相邻沟槽之间形成阻挡层的步骤中,所述阻挡层围绕所述沟槽的外侧面设置,且所述阻挡层与所述沟槽的外侧面之间具有大于零的距离。
进一步,所述栅极结构包括栅极绝缘层及栅极,在所述沟槽内形成栅极结构的步骤进一步包括:在所述沟槽内形成栅极绝缘材料,所述栅极绝缘材料覆盖所述沟槽侧壁及所述半导体衬底表面;在所述沟槽内填充导电材料,所述导电材料充满所述沟槽,且覆盖所述半导体衬底表面的栅极绝缘材料;去除半导体衬底表面的导电材料及栅极绝缘材料,形成位于所述沟槽内的形成栅极绝缘层及栅极。
进一步,在所述半导体衬底内形成沟道区的步骤进一步包括,对所述半导体衬底进行等离子体注入,形成所述沟道区。
进一步,沟道区的宽度大于所述沟槽的宽度。
进一步,等离子体注入后,进行退火处理,以使沟道区沿所述沟槽侧壁向上延伸。
进一步,改变等离子体注入深度,以使沟道区沿所述沟槽侧壁向上延伸。
进一步,形成所述阻挡层的等离子体与形成所述沟道区的等离子体为同种导电类型离子。
进一步,在所述沟槽与所述阻挡层之间,形成源漏区的步骤进一步包括:对所述半导体衬底进行等离子体注入,形成浅掺杂漏及源漏极,所述源漏极通过所述浅掺杂漏与所述沟道区电连接。
进一步,在所述沟槽与所述阻挡层之间,形成源漏区的步骤之后,包括如下步骤:形成钝化层,所述钝化层覆盖所述半导体衬底表面及所述栅极结构表面。
本发明还提供一种半导体器件,其包括:半导体衬底,所述半导体衬底中形成有多个彼此独立的沟槽;阻挡层,通过等离子体注入工艺形成在相邻的沟槽之间;栅极结构,形成在所述沟槽内;沟道区,形成在半导体衬底中,且与所述沟槽对应;源漏区,设置在所述沟槽与所述阻挡层之间,且与所述沟道区电连接,所述阻挡层的导电类型与所述源漏区的导电类型相反。
进一步,所述阻挡层围绕所述沟槽的外侧面设置,且所述阻挡层与所述沟槽的外侧面之间具有间隔。
进一步,所述栅极结构包括覆盖所述沟槽侧壁的栅极绝缘层及填充所述沟槽的栅极。
进一步,沟道区的宽度大于所述沟槽的宽度。
进一步,所述沟道区设置在所述沟槽底部,且沿所述沟槽侧壁向上延伸。
进一步,还包括钝化层,所述钝化层覆盖所述半导体衬底表面及所述栅极结构表面。
本发明的优点在于,现有技术中,采用浅沟槽隔离结构作为相邻晶体管的源漏区的隔离层,浅沟槽隔离结构受后续清洗等制程的影响,会产生缺陷,使得有源区因表面张力的作用而接触,造成有源区短路。而本发明无需形成浅沟槽隔离结构进行隔离,其通过等离子体注入形成的阻挡层作为相邻晶体管的源漏区的隔离层,由于源漏区与阻挡层注入的是反型离子,因此在源漏区与阻挡层之间形成PN结,PN结的内建电场可以阻止电子的扩散,进而起到了隔离的效果。本发明制备方法规避了传统晶体管器件在制程中存在的多种弊端,提高半导体器件性能。
附图说明
图1是本发明半导体器件的制备方法的一实施例的步骤示意图;
图2~图10是本发明半导体器件的制备方法的一实施例的工艺流程图。
具体实施方式
下面结合附图对本发明提供的半导体器件及其制备方法的具体实施方式做详细说明。
图1是本发明半导体器件的制备方法的一实施例的步骤示意图,请参阅图1,本发明半导体器件的制备方法包括如下步骤:步骤S10,提供半导体衬底,所述半导体衬底中形成有多个彼此独立的沟槽;步骤S11,等离子体注入,在相邻沟槽之间形成阻挡层;步骤S12,在所述沟槽内形成栅极结构;步骤S13,在所述半导体衬底内形成沟道区,所述沟道区与所述沟槽对应;步骤S14,在所述沟槽与所述阻挡层之间,形成源漏区,所述源漏区与所述沟道区电连接。
图2~图10是本发明半导体器件的制备方法的一实施例的工艺流程图。
请参阅步骤S10及图2,提供半导体衬底200,所述半导体衬底200中形成有多个彼此独立的沟槽210。所述半导体衬底200可为硅、锗等半导体衬底。在本实施例中,以所述半导体衬底200为硅衬底进行描述。
在该步骤中,可采用光刻及刻蚀工艺形成所述沟槽210。具体地说,在该步骤中,在所述半导体衬底200上形成掩膜层及图形化的光阻层;将所述光阻层的图案转移到所述掩膜层上;以所述掩膜层为掩膜刻蚀所述半导体衬底200,形成所述沟槽210;形成所述沟槽210后去除所述掩膜层。
请参阅步骤S11及图3,等离子体注入,在相邻沟槽210之间形成阻挡层220。在该步骤中,对所述半导体衬底200进行等离子体注入,在所述半导体衬底200内形成阻挡层220。所述阻挡层220作为本发明制备方法形成的相邻的晶体管的源漏区的隔离层,从而避免漏电。
在本实施例中,在进行等离子体注入工艺时,未对所述半导体衬底200进行遮挡,则在所述半导体衬底200内形成的阻挡层220围绕所述沟槽210的外侧面设置,且所述阻挡层220与所述沟槽210的外侧面之间具有大于零的距离。所述阻挡层220与所述沟槽210的外侧面的距离及所述阻挡层220的厚度由最终形成的半导体器件的性能决定。其中,可通过调整等离子体注入的能量、注入的剂量、注入的元素种类及半导体衬底200的晶界等调整所述阻挡层220与所述沟槽210的外侧面的距离(即等离子体注入的深度)及所述阻挡层220的厚度。
进一步,在本实施例中,所述等离子体注入工艺采用垂直注入,垂直注入可以使阻挡层220在沟槽210两边均匀对称分布。若在沟槽210两边所述阻挡层220分布不对称,例如一边距离沟槽较近一边距离沟槽较远,则距离较近的阻挡层220有可能与后续形成的源漏区域重叠导致失效。
在本发明另一实施例中,在进行等离子体注入工艺时,对所述半导体衬底200进行部分遮挡,仅暴露相邻的所述沟槽210之间的区域,且所述暴露区域的宽度小于相邻的所述沟槽210之间的宽度,则进行等离子体注入后,仅在所述暴露区域形成阻挡层,且所述阻挡层与所述沟槽的外侧面之间具有大于零的距离,在其他区域未形成阻挡层。
若要形成N型半导体器件,则在该步骤中注入的等离子体的导电类型为P型,若要形成P型半导体器件,则在该步骤中注入的等离子体的导电类型为N型。
现有技术中,采用浅沟槽隔离结构作为相邻晶体管的源漏区的隔离层,浅沟槽隔离结构由于受后续清洗等制程的影响,会产生缺陷,使得有源区因表面张力的作用而接触,造成有源区短路。而本发明无需形成浅沟槽隔离结构进行隔离,其通过等离子体注入形成的阻挡层作为相邻晶体管的源漏区的隔离层,由于源漏区与阻挡层注入的是反型离子,因此在源漏区与阻挡层之间形成PN结,PN结的内建电场可以阻止电子的扩散,进而起到了隔离的效果。其中,相邻的晶体管之间的距离越远,所述阻挡层220的隔离作用越好。
请参阅步骤S12及图6,在所述沟槽210内形成栅极结构230。
所述栅极结构230包括栅极绝缘层231及栅极232。则在本实施例中,形成所述栅极结构的方法进一步包括如下步骤:
请参阅图4,在所述沟槽210内形成栅极绝缘材料400,所述栅极绝缘材料400覆盖所述沟槽210侧壁及所述半导体衬底200表面。所述栅极绝缘材料400可为氧化物或者氮化物。其中,可以采用原位水汽生成(in—situ steam generation,ISSG)、原子层沉积工艺(ALD)或者热氧化工艺形成所述栅极绝缘材料400。所述栅极绝缘材料的具体厚度由器件电压决定,例如,在本实施例中,所述栅极绝缘材料400的厚度为2nm-10nm。在本实施例中,采用原子层沉积工艺形成所述栅极绝缘材料400,所述栅极绝缘材料400为氧化硅。
请参阅图5,在所述沟槽210内填充导电材料410,所述导电材料410充满所述沟槽210,且覆盖所述半导体衬底200表面的栅极绝缘材料400。所述导电材料410可为形成栅极的常规材料,例如,多晶硅。在该步骤中,可采用低压化学气相沉积工艺(LPCVD)形成所述导电材料400。
请参阅图6,去除半导体衬底200表面的导电材料410及栅极绝缘材料400,形成位于所述沟槽210内的栅极绝缘层231及栅极232。具体地说,在该步骤中,可采用回刻、化学机械研磨及清洗的步骤去除半导体衬底200表面的导电材料410及栅极绝缘材料400。所述栅极绝缘层231覆盖所述沟槽210侧壁,所述栅极232覆盖所述栅极绝缘层231且充满所述沟槽210。
请参阅步骤S13及图7,在所述半导体衬底200内形成沟道区240,所述沟道区240与所述沟槽210对应。所述阻挡层220将所述半导体衬底分隔为多个区域,每一区域具有沟槽210,在该区域,在半导体衬底200内形成沟道区240。
在本实施例中,所述沟道区240形成在所述沟槽210下方的半导体衬底200中,同时还形成在所述沟槽210侧面的半导体衬底200中,即所述沟道层240沿所述沟槽210侧壁向上延伸。可以理解的是,为了后续形成源漏区,所述沟道区240仅形成在所述沟槽210的部分侧面。而在本发明另一实施例中,所述沟道区240也可仅形成在所述沟槽210下方的半导体衬底200中。
进一步,在本实施例中,如图7所示,对所述半导体衬底200采用光阻层进行部分遮挡,暴露出需要形成沟道的区域;对所述半导体衬底200进行等离子体注入,形成所述沟道区240。其中,可控制等离子体注入的能量、注入的剂量、注入的元素种类及半导体衬底200的晶界等调整形成的所述沟道区240的深度及厚度;可控制所述光阻层的开口宽度,以控制所述沟道区240的宽度。
进一步,在本实施例中,所述等离子体注入工艺采用垂直注入,垂直注入可以使沟道区240形成在沟槽210的正下方且对称分布,进而保证沟道长度;若等离子体注入工艺采用倾斜入射,则所形成的沟道区240也可能是倾斜的,有可能导致源漏区与沟道区无法电连接,影响器件性能。进一步,所述沟道区240的宽度大于所述沟槽210的宽度,以保证沟道长度。若所述沟道区240的宽度较窄,则源漏区需要注入在更深的位置以形成电连接,使得沟道长度过短,影响半导体器件性能。
进一步,请参阅图8,在本实施例中,在进行等离子体注入后,进行退火处理,以使沟道区240的离子向上扩散,形成沿所述沟槽210侧壁向上延伸的沟道区240。所述沟道区240对应所述沟槽210的底部及侧面设置,以使源漏区250(绘示于图9中)与所述沟道区240接触,,同时增加所述沟道区240与所述栅极结构230的重叠面积,进而增加沟道的长度(所述沟道的长度H请参阅图10所示)。
在本发明另一实施例中,改变等离子体注入深度,以使沟道区240沿所述沟槽210侧壁向上延伸。即随着所述沟槽210深度的减小,等离子体注入深度逐渐减小,以避免在所述栅极结构230中注入等离子体,形成沿所述沟槽210侧壁向上延伸的沟道区240。例如,对于侧壁倾斜的沟槽210,其底部的沟槽深度最大,则对应地,等离子体注入的深度最大,其侧壁的沟槽深度逐渐减小,则对应地,等离子体注入深度逐渐减小。
进一步,形成所述阻挡层220的等离子体与形成所述沟道区240的等离子体为同种导电类型离子。即所述阻挡层220与所述沟道区240为同种导电类型,例如,若要形成N型半导体器件,则在该步骤中注入的等离子体的导电类型为P型,若要形成P型半导体器件,则在该步骤中注入的等离子体的导电类型为N型。
请参阅步骤S14及图9,在所述沟槽210与所述阻挡层220之间,形成源漏区250,所述源漏区250与所述沟道区240电连接。所述源漏区250与所述沟道区240电连接是指,当对所述栅极结构230施加电压时,所述沟道区240导通,源漏之间的载流子流动,进而形成电流。
所述沟槽210与所述阻挡层220之间具有一间隔,该间隔用于形成源漏区250。所述源漏区250的导电类型与所述阻挡层220的导电类型相反。例如,若要形成N型半导体器件,则所述源漏区250的导电类型为N型,而所述阻挡层220的导电类型为P型;若要形成P型半导体器件,则所述源漏区250的导电类型为P型,而所述阻挡层220的导电类型为N型。所述源漏区250与所述阻挡层220形成PN结,PN结的内建电场防止电子扩散,起到隔离效果。
进一步,在本实施例中,采用光阻层等结构对半导体衬底200进行部分遮挡,仅暴露需要形成源漏区250的区域,即暴露出所述沟槽210与所述阻挡层220之间的间隔区域,对所述半导体衬底200暴露的区域进行等离子体注入,形成源漏区250。所述源漏区250的深度及宽度由半导体器件的性能决定,可通过调整等离子体注入的能量、注入的剂量、注入的元素种类及半导体衬底200的晶界等调整所述源漏区250的深度及浓度。
在现有技术中,源漏区采用斜入射掺杂的方法形成,而斜入射掺杂容易被其上方的光阻层遮挡,导致电性失效。而本发明制备方法通过等离子体注入工艺形成所述源漏区250,不存在斜入射掺杂,也不会被光阻层遮挡,从而不会导致电性失效,提高了半导体器件的性能。
进一步,在本实施例中,所述源漏区250包括浅掺杂漏251及源漏极252。所述源漏极252通过所述浅掺杂漏251与所述沟道区240电连接,即所述浅掺杂漏251位于所述源漏极252的下方,其与所述沟道区240电连接。在本实施例中,可先通过等离子体注入工艺形成所述浅掺杂漏251,再改变等离子体注入的参数,形成所述源漏极252。所述浅掺杂漏251及所述源漏极252均可通过等离子体注入工艺形成,相较于现有技术中分多次采用斜入射掺杂的方法形成浅掺杂漏及源漏极而言,本发明制备方法形成所述浅掺杂漏251及源漏极252导电性能好。
进一步,请参阅图10,在所述沟槽210与所述阻挡层220之间,形成源漏区150的步骤之后,包括如下步骤:形成钝化层260,所述钝化层260覆盖所述半导体衬底200表面及所述栅极结构230表面。所述钝化层260用于将栅极结构230与外界隔离,并起到保护作用。所述钝化层260包括但不限于氮化物,例如氮化硅,其可采用低压化学气相沉积工艺(LPCVD)形成。
在现有技术中,沟道的长度通常由光刻工艺定义,若形成的半导体器件的电性不好,需要调整沟道长度时,就需要重新制定光罩,而修改光罩的成本较高,耗时费钱;而采用本发明制备方法形成的半导体器件,其沟道的长度(如图10中H)可由沟槽210的深度及源漏区250的深度决定,可以直接通过沟槽210的刻蚀深度和源漏区250的等离子体注入深度调节沟道的长度,可随时进行微调,大大降低了生产成本,且耗时短。另外,本发明制备方法能够减少光罩,节省工艺步骤。
本发明还提供一种采用上述制备方法制备的半导体器件。请参阅图10,在本发明半导体器件的一实施例中,所述半导体器件包括半导体衬底200、阻挡层220、栅极结构230、沟道区240及源漏区250。所述栅极结构230、沟道区240及源漏区250形成一个晶体管。
所述半导体衬底200形成有多个彼此独立的沟槽210。所述半导体衬底200可为硅、锗等衬底。在本实施例中,所述半导体衬底200为硅衬底。
所述阻挡层220通过等离子体注入工艺形成在相邻的沟槽210之间。所述阻挡层220作为相邻的晶体管之间的隔离层。所述沟槽210与所述阻挡层220之间具有一间隔。在本实施例中,所述阻挡层220围绕所述沟槽210的外侧面设置,且所述阻挡层220与所述沟槽210的外侧面之间的间隔大于零。在本发明另一实施例中,所述阻挡层220仅形成在相邻的晶体管之间,而并非是围绕所述沟槽210的外侧面。
所述栅极结构230形成在所述沟槽210内。其中,所述栅极结构230包括覆盖所述沟槽210侧壁的栅极绝缘层231及填充所述沟槽210的栅极232。所述栅极绝缘层231作为所述栅极232与所述沟道区240及所述源漏区250的隔离层。
所述沟道区240形成在半导体衬底200中,且与所述沟槽210对应。在本实施例中,所述沟道区250设置在所述沟槽210底部,且沿所述沟槽210侧壁向上延伸。可以理解的是,为了给源漏区250提供足够的形成空间,所述沟道区240仅形成在所述沟槽210的部分侧面。而在本发明另一实施例中,所述沟道区240也可仅形成在所述沟槽210下方的半导体衬底200中。
进一步,所述沟道区240的宽度大于所述沟槽210的宽度,以增大源漏区250与所述沟道区240的接触面积。若所述沟道区240的宽度较窄,则源漏区需要形成在更深的位置,造成沟道长度过短,影响半导体器件性能。
所述源漏区250设置在所述沟槽210与所述阻挡层220之间,且与所述沟道区240电连接。所述源漏区250形成在所述沟槽210与所述阻挡层220之间的间隔区域。所述阻挡层220的导电类型与所述源漏区250的导电类型相反。例如,若要形成N型半导体器件,则所述源漏区250的导电类型为N型,而所述阻挡层220的导电类型为P型;若要形成P型半导体器件,则所述源漏区250的导电类型为P型,而所述阻挡层220的导电类型为N型。所述源漏区250与所述阻挡层220形成PN结,PN结的内建电场防止电子扩散,起到隔离效果。
进一步,在本实施例中,所述源漏区250包括浅掺杂漏251及源漏极252。所述源漏极252通过所述浅掺杂漏251与所述沟道区240电连接,即所述浅掺杂漏251位于所述源漏极252的下方,其与所述沟道区240电连接。
进一步,所述半导体器件还包括钝化层260,所述钝化层260覆盖所述半导体衬底200表面及所述栅极结构230表面。所述钝化层260用于将栅极结构230与外界隔离,并起到保护作用。所述钝化层260包括但不限于氮化物,例如氮化硅。
本发明半导体器件电学性能好,且制备简单,工艺成本低。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (16)
1.一种半导体器件的制备方法,其特征在于,包括如下步骤:
提供半导体衬底,所述半导体衬底中形成有多个彼此独立的沟槽;
等离子体注入,在相邻沟槽之间形成阻挡层;
在所述沟槽内形成栅极结构;
在所述半导体衬底内形成沟道区,所述沟道区与所述沟槽对应;
在所述沟槽与所述阻挡层之间,形成源漏区,所述源漏区与所述沟道区电连接,所述阻挡层的导电类型与所述源漏区的导电类型相反。
2.根据权利要求1所述的半导体器件的制备方法,其特征在于,在相邻沟槽之间形成阻挡层的步骤中,所述阻挡层围绕所述沟槽的外侧面设置,且所述阻挡层与所述沟槽的外侧面之间具有大于零的距离。
3.根据权利要求1所述的半导体器件的制备方法,其特征在于,所述栅极结构包括栅极绝缘层及栅极,在所述沟槽内形成栅极结构的步骤进一步包括:在所述沟槽内形成栅极绝缘材料,所述栅极绝缘材料覆盖所述沟槽侧壁及所述半导体衬底表面;
在所述沟槽内填充导电材料,所述导电材料充满所述沟槽,且覆盖所述半导体衬底表面的栅极绝缘材料;
去除半导体衬底表面的导电材料及栅极绝缘材料,形成位于所述沟槽内的栅极绝缘层及栅极。
4.根据权利要求1所述的半导体器件的制备方法,其特征在于,在所述半导体衬底内形成沟道区的步骤进一步包括,对所述半导体衬底进行等离子体注入,形成所述沟道区。
5.根据权利要求4所述的半导体器件的制备方法,其特征在于,沟道区的宽度大于所述沟槽的宽度。
6.根据权利要求5所述的半导体器件的制备方法,其特征在于,等离子体注入后,进行退火处理,以使沟道区沿所述沟槽侧壁向上延伸。
7.根据权利要求5所述的半导体器件的制备方法,其特征在于,改变等离子体注入深度,以使沟道区沿所述沟槽侧壁向上延伸。
8.根据权利要求4所述的半导体器件的制备方法,其特征在于,形成所述阻挡层的等离子体与形成所述沟道区的等离子体为同种导电类型离子。
9.根据权利要求1所述的半导体器件的制备方法,其特征在于,在所述沟槽与所述阻挡层之间,形成源漏区的步骤进一步包括:对所述半导体衬底进行等离子体注入,形成浅掺杂漏及源漏极,所述源漏极通过所述浅掺杂漏与所述沟道区电连接。
10.根据权利要求1所述的半导体器件的制备方法,其特征在于,在所述沟槽与所述阻挡层之间,形成源漏区的步骤之后,包括如下步骤:形成钝化层,所述钝化层覆盖所述半导体衬底表面及所述栅极结构表面。
11.一种半导体器件,其特征在于,包括:
半导体衬底,所述半导体衬底中形成有多个彼此独立的沟槽;
阻挡层,通过等离子体注入工艺形成在相邻的沟槽之间;
栅极结构,形成在所述沟槽内;
沟道区,形成在半导体衬底中,且与所述沟槽对应;
源漏区,设置在所述沟槽与所述阻挡层之间,且与所述沟道区电连接,所述阻挡层的导电类型与所述源漏区的导电类型相反。
12.根据权利要求11所述的半导体器件,其特征在于,所述阻挡层围绕所述沟槽的外侧面设置,且所述阻挡层与所述沟槽的外侧面之间具有间隔。
13.根据权利要求11所述的半导体器件,其特征在于,所述栅极结构包括覆盖所述沟槽侧壁的栅极绝缘层及填充所述沟槽的栅极。
14.根据权利要求11所述的半导体器件,其特征在于,沟道区的宽度大于所述沟槽的宽度。
15.根据权利要求11所述的半导体器件,其特征在于,所述沟道区设置在所述沟槽底部,且沿所述沟槽侧壁向上延伸。
16.根据权利要求11所述的半导体器件,其特征在于,还包括钝化层,所述钝化层覆盖所述半导体衬底表面及所述栅极结构表面。
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