TWI396240B - 製造功率半導體元件的方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims description 170
- 239000000758 substrate Substances 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 59
- 239000002019 doping agent Substances 0.000 claims description 45
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 239000002344 surface layer Substances 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000005137 deposition process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000005684 electric field Effects 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Description
本發明有關一種功率元件的製作方法,特別有關一種可改善不均勻電場分佈的功率半導體元件的製作方法。
功率元件主要用於電源管理的部分,例如應用於切換式電源供應器、電腦中心或周邊電源管理IC、背光板電源供應器以及馬達控制等等用途,其種類包含有絕緣閘雙極性電晶體(insulated gate bipolar transistor,IGBT)、金氧半場效電晶體(metal-oxide-semiconductor thin film transistor,MOSFET)與雙載子接面電晶體(bipolar junction transistor,BJT)等元件。
為了得到較低的導通電阻值、降低元件尺寸,且能夠在耗費低功率的情況下進行電壓控制,溝槽式(trench)功率MOSFET之發展成為功率元件的一大趨勢。如第1圖所示,一習知溝槽式MOSFET功率元件10包含一n+
型的半導體材質的晶圓基材12。晶圓基材12上利用磊晶方式形成一n-
型的半導體層14,而半導體層14中則包含一第一溝槽16、複數個第二溝槽18、一p型基體20、複數個p+
型區21、及複數個n+
型的源極區22。第一溝槽16與第二溝槽18內均設置有一閘極氧化層32及多晶矽材料34,多晶矽材料34是作為溝槽式MOSFET功率元件10的閘極。一層間介電層24覆蓋於p型基體20、閘極、及源極區22上方。一閘極金屬層26設置於層間介電層24上,經由接觸插塞(contact plug)28與第一溝槽16內的閘極電連接,一源極金屬層27設置於層間介電層24上,經由複數個接觸插塞30與複數個源極區22及p+
型區21電連接。在晶圓基材12的另一面上,則設置有汲極金屬層36。
隨著電子產品日益朝向輕、薄、短、小發展,積體電路元件設計的尺寸與間距亦不斷縮小,以符合高積集度和高密度之潮流。因此,習知溝槽式MOSFET功率元件10的佈局設計,也朝向縮減溝槽寬度及其節距而努力。然而,因與閘極電連接的接觸插塞有一定的製程極限,形成接觸插塞用的開口必須具有一定寬度,以利填入鎢等材料以形成接觸插塞,所以需要使第一溝槽16具有一定寬度,例如0.8微米,以便使閘極具有足夠的頂表面積供形成接觸插塞。但複數個第二溝槽18則不需接觸插塞的設置,因此溝槽寬度可較窄,例如0.2微米。於製程上,第一溝槽16與第二溝槽18通常是藉由蝕刻製程同時形成的,當溝槽寬度較寬時,由於負載效應(loading effect)使得蝕刻速率較快,所以形成的深度也比較深。在p型基體20的深度均為一致的情形下,較深的閘極溝槽(gate trench)導致較強的電場,使得電場不均勻,並且較大的電場也使得崩潰電壓(breakdown voltage)降低。一種習知的解決方法是,犧牲這一帶p-n接合面及其附近的阻值,以將崩潰電壓提升至原預定值,但會影響可靠度。另一種習知的解決方法是,在第一溝槽16的周圍形成一環狀的保護環(guard ring)摻雜區,例如第2圖所示的習知溝槽式MOSFET功率元件11,其進一步具有一保護環摻雜區38。保護環摻雜區38摻雜有低濃度的p-
型摻雜物,如此使得接合面高度降低,可降低阻值。但是習知形成保護環摻雜區的製程尚需要使用一道光罩遮住保護環摻雜區以外的區域,導致製程成本增加。如下述。
習知的功率半導體元件製程會先在一半導體基底上使用光罩定義主動區,然後會有如第3圖的流程圖所示的若干使用到光罩的主要步驟。例如,進行步驟2,使用一光罩以於主動區的半導體基底進行摻雜,而於預定位置形成保護環摻雜區;然後進行步驟3,使用一光罩以蝕刻基底,形成閘極溝槽;後來進行步驟4,沉積多晶矽材料以填滿溝槽,並回蝕刻(etching back);然後進行步驟5,分別使用光罩進行n型及p型摻雜製程,以製得所欲的p基體、p+
型區等摻雜區、及源極區;形成層間介電層後,進行步驟6,使用一光罩以於層間介電層中形成通孔(through hole),填入鎢金屬,形成接觸插塞;然後進行步驟7,使用一光罩以將形成於層間介電層上的金屬層圖案化,形成源極金屬層與閘極金屬層。一般,形成金屬層後,尚可進一步使用光罩形成一保護層。如此,於習知的標準製程中,總共需要使用7道光罩。特別注意到步驟2中,在形成保護環摻雜區時必須使用到光罩,而增加製程成本。
因此,仍需要一種新穎的製造功率半導體元件的方法,以簡便及經濟的方式解決如上述的電場不均勻的問題,並能維持高且穩定的崩潰電壓。
本發明的一目的是提供一種製造功率半導體元件的方法,簡便及經濟,可解決如上述的電場不均勻的問題,並維持高且穩定的崩潰電壓。
依據本發明的製造功率半導體元件的方法,包括下列步驟。首先,提供一基底,基底具有一原始表面與一背面。經由一第一光罩對基底進行蝕刻,以形成一第一溝槽及至少一第二溝槽,其中,第一溝槽的寬度大於第二溝槽的寬度。於基底上全面形成一閘極絕緣層,覆蓋基底的原始表面、及第一溝槽與第二溝槽的側壁及底面。其次,進行一第一沉積製程,以於閘極絕緣層上全面形成一第一閘極材料層,其中第一溝槽未被第一閘極材料層填滿。接著,進行一等向性回蝕刻或異向性回蝕刻製程,以將位於第一溝槽內及基底原始表面上方的第一閘極材料層移除。然後,全面進行一斜向離子佈植(tilt ion implantation)製程,以於基底的表層中形成一第一摻雜物層,基底的表層包括基底位於原始表面的表層及位於第一溝槽的側壁與底面位置的表層。然後,進行一第二沉積製程,以於基底上全面形成一第二閘極材料層,其中第一閘極材料層與第二閘極材料層合而為一閘極材料層,閘極材料層填滿第一溝槽及第二溝槽,並且覆蓋基底原始表面上的閘極絕緣層。進行一異向性回蝕刻製程,以部分移除閘極材料層,俾露出位於基底原始表面上的閘極絕緣層。全面進行一第一離子佈植製程,以於基底原始表面的表層中形成一第二摻雜物層。進行一驅入(drive-in)製程,以將第一摻雜物層及第二摻雜物層的摻雜物往基底的更深層延伸分佈,俾形成一基體於基底中及形成一底部輕摻雜層(bottom lightly doped layer)圍繞第一溝槽底部並與基體相鄰。
本發明利用在二次的沉積及回蝕刻閘極材料層之間對較大寬度的閘極溝槽的側壁與底部的基底佈植摻雜物,而在製作基體時一併與基體的摻雜物一起進行驅入製程,以於基底中形成一底部輕摻雜層圍繞較大寬度的閘極溝槽底部,可改善不均勻電場的問題,並完整保護閘極溝槽的底部,提升崩潰電壓,製程中並不需要增加光罩的使用,顯得經濟與便利。
第4圖顯示本發明使用到光罩的主要步驟的流程示意圖,可與第3圖的習知技術的流程做比較。於定義主動區之後,本發明的方法不進行習知技術的使用光罩形成保護環摻雜區的步驟2,而是直接進行步驟3以形成閘極溝槽,然後進行閘極材料的填入。閘極材料的填入係藉由步驟101、102、及103來完成。即,進行步驟101之第一次閘極材料沉積及回蝕刻;然後進行步驟102的斜向離子佈植,供後續形成底部輕摻雜層的步驟使用;再進行步驟103的第二次閘極材料沉積及回蝕刻。在形成閘極溝槽的填入後,可進一步進行一基體(例如p基體(p base))的製作,其中可使步驟102的摻雜物與基體的摻雜物一起進行驅入製程,同時達成底部輕摻雜層與基體的形成。然後,進行步驟5、6、及7。若再使用光罩形成一保護層,則總共需要使用6道光罩,較習知技術的7道光罩少用一道,而節省成本。
本發明之製造方法可涵括例如IGBT、MOSFET與BJT等功率元件的製法,其中MOSFET功率元件尚可包括PMOS型及NMOS型。當功率半導體元件中需要製造複數個閘極溝槽,且溝槽具有不同寬度時,由於蝕刻製程具有負載效應之故,使得較寬閘極溝槽在製得後的深度相對較深。本發明的製法可適用於製造這樣的功率半導體元件,形成一底部輕摻雜層圍繞在較寬閘極溝槽的較深底部周圍。
下述以一製造功率NMOSFET元件的具體實施例詳細說明本發明。請參閱第5至12圖所繪示的本發明一具體實施例製作功率半導體元件的方法示意圖,其中所製作的功率元件可包含溝槽式之功率MOSFET,而圖式中相同的元件或部位沿用相同的符號來表示。需注意的是圖式係以說明為目的,並未依照原尺寸作圖。
如第5圖所示,首先提供一基底。基底可為半導體基底,例如矽基材。基底也可進一步由一半導體晶圓基材111及一形成於半導體晶圓基材111上的半導體層112所構成。當功率元件是高功率時,較佳使半導體層112為一n型輕摻雜(n-
)的半導體材質的磊晶層,功率越高時,則因為需要更高的耐壓,因此可使磊晶層厚度更厚。半導體晶圓基材111則可包括一n型重摻雜(n+
)區。基底具有一原始表面113與一背面114,於本例中,基底具有半導體晶圓基材111與半導體層112,因此原始表面113為半導體層112的原始表面,而背面114為半導體晶圓基材111的背面。然後,於半導體層112上形成一圖案化的光阻層119,具有對應於閘極溝槽位置的開口,使用光阻層119做為光罩,經由此光罩對半導體層112進行蝕刻,以形成一第一溝槽116及複數個第二溝槽118。其中,第一溝槽116位於閘極插塞接觸區域,第二溝槽118位於電晶體單元區域(cell region),第一溝槽116的寬度大於各第二溝槽118的寬度,並且較深。
然後,移除光阻層119。接著,請參閱第6圖,於半導體層112上全面形成一閘極絕緣層132,覆蓋原始表面113、及第一溝槽116與第二溝槽118的側壁及底面。閘極絕緣層132可包括例如矽氧化物。可利用例如熱氧化製程形成閘極絕緣層132,厚度可為例如250至1000埃。然後進行一沉積製程,以於閘極絕緣層132上全面形成一閘極材料層134。由於第一溝槽116的寬度較第二溝槽118的寬度大,因此,當第二溝槽118填滿閘極材料後,第一溝槽116尚未被填滿,並且,原始表面113上的閘極材料層厚度會與第一溝槽116的側壁及底面上的閘極材料層厚度類似。利用此時點的特性,可便利的使用等向性或異向性的蝕刻製程進行回蝕刻,將第一溝槽116的側壁及底面上的閘極材料層移除,由於原始表面113上的閘極材料層厚度與第一溝槽116的側壁及底面上的閘極材料層厚度類似,因此也被同時移除。部分移除閘極材料層後的情形如第7圖所示,留下第二溝槽118內的閘極材料層,其符號記做134a。等向性的蝕刻製程可為例如濕蝕刻(wet etching),蝕刻液對閘極材料層與閘極絕緣層具有蝕刻選擇比。閘極材料可為導電材料,例如經摻雜的多晶矽。
然後,請參閱第8圖,全面進行一斜向離子佈植製程140,以於半導體層112的表層中形成一第一摻雜物層142。半導體層112的表層包括半導體層112之位於原始表面113的表層及位於第一溝槽116的側壁與底面位置的表層。由於第一溝槽116內的閘極材料層已先被移除,因此在進行斜向離子佈植製程140時,可以使摻雜物通過溝槽上的閘極絕緣層132而佈植於構成第一溝槽116的側壁及底面的半導體層112的表層。並且由於此斜向離子佈植製程140是全面性的於基底上方進行,因此,在閘極材料層也被移除的原始表面113位置的半導體層112表層,也同樣被佈植而形成第一摻雜物層142。而第二溝槽118的側壁及底面,因為溝槽內尚有閘極材料層143a,形成阻擋,所以此處的基底表層不會有摻雜物層的形成。第一摻雜物層142主要是用以在後續製程中形成足以分攤電場及保護第一溝槽116底部的底部輕摻雜層。形成第一摻雜物層142時所使用的斜向植入角度可為例如10至45度,使用例如1至8×1012
cm-2
的劑量(dosage),摻雜物可為例如硼離子,但不限於此等參數。此等製程條件僅提供做為一個實施例,並不欲做為本發明範圍的限制,此等製程條件可依據結構或製程所需而適當選擇。例如,斜向植入角度只要是可供於閘極溝槽側壁與底部植入摻雜物的話都可使用;植入物種及劑量則可依所需電性而選擇。
然後,請參閱第9圖,進行一沉積製程,以於基底上全面再形成一閘極材料層,此閘極材料層與之前留在第二溝槽118的極材料層合而為一個閘極材料層,符號記為134b。此等分為二次所形成的閘極材料層並不限為相同、或不同材質。使閘極材料層134b填滿第一溝槽116及第二溝槽118,厚度可高至覆蓋原始表面113上的閘極絕緣層132。
再請參閱第10圖,進行一異向性回蝕刻製程,以部分移除閘極材料層134b,以便露出位於原始表面113上的閘極絕緣層132。異向性回蝕刻可舉例有乾蝕刻(dry etching)。如此,於第一溝槽116及第二溝槽118內留下閘極材料層做為閘極134c。然後,全面進行一離子佈植製程144,以於原始表面113的表層中形成一第二摻雜物層146。如此,因溝槽內均已填滿閘極材料,所以僅有原始表面113的表層中會形成有第二摻雜物層146。第二摻雜物層146是做為後續形成基體之用,其摻雜物可與第一摻雜物層142的摻雜物相同或不同,但所用劑量較大。
然後,請參閱第11圖,進行一驅入製程,例如加熱使摻雜物擴散,以將第一摻雜物層142及第二摻雜物層146的摻雜物往基底(即半導體層112)的更深層延伸分佈。例如加熱溫度為1150℃,歷時50分鐘。如此,位於原始表面113表層的第二摻雜物層146的摻雜物往半導體層112深處擴散而增大範圍,形成基體148,此例中,基體148為p型摻雜,接合(junction)深度可達例如1至1.5微米,不低於第二溝槽118的底面;而圍繞在第一溝槽116的第一摻雜物層142的摻雜物往外擴散而增大範圍,形成底部輕摻雜層150,此例中,底部輕摻雜層150為p-
型摻雜,接合深度可達例如0.3至0.6微米,較佳使下方的半導體層112留有大於空乏區的空間,可依耐壓需求設定半導體層112厚度。基體148與底部輕摻雜層150會有重疊之處,但因為基體148的摻雜濃度大於底部輕摻雜層150的摻雜濃度,重疊之處是呈現基體148的性質,而為基體148的一部分,符合功率MOS元件結構所需,而底部輕摻雜層150即圍繞第一溝槽116的底部並與基體148相鄰,達到保護第一溝槽116的底部的效用,分攤因第一溝槽116較深所導致的較高電場。再者,使第一摻雜物層142及第二摻雜物層146的驅入同時進行,也可以節省熱預算(thermal budget)。
然後,請參閱第12圖,經由一光罩(圖未示)進行一離子佈植,以於基體148上形成複數個源極區122,於本例中為n+
型摻雜。而在形成源極區122之前,亦可先於基體148的複數個接觸插塞預定區域,使用一光罩(圖未示)進行一離子佈植,於各接觸插塞預定區域形成一重摻雜的P+
型區121(即,一重摻雜區)。然後,於基底上方全面形成一層間介電層124。然後,通過層間介電層124形成通孔,填入金屬,例如鎢,形成閘極接觸插塞128,通過源極區122與層間介電層124形成通孔,填入金屬,例如鎢,以形成複數個源極接觸插塞130。再使用一光罩,於層間介電層124上形成一閘極金屬層126及複數個源極金屬層127,使得閘極接觸插塞128電連接第一溝槽16中的閘極材料層134c與閘極金屬層126,並使源極接觸插塞130電連接P+
型區121及源極區122與源極接觸插塞127。並進一步於背面114形成一汲極金屬層136,而形成如第12圖所示的溝槽式MOSFET功率元件100。
上述實施例僅以NMOS為例,若製造其他功率元件時,可參考使用習知的元件尺寸、製程參數、條件、電性等,沒有特別限制。但應注意的是由於本發明形成一底部輕摻雜層圍繞第一溝槽底部,因此應注意到基底的厚度(例如第12圖中的半導體層112的厚度)應足夠,以保有足夠的空間供形成空乏區。
本發明之優點是可改善不均勻電場,並完整保護閘極溝槽的底部,及提升崩潰電壓,雖然在結構上增加一底部的輕摻雜層,但其在製程中並不需要使用光罩來完成。因此,雖然較習知技術的標準製程多出額外的製程,即,閘極材料的沉積(poly deposition)及回蝕刻,但是相較於習知技術是省下一個光罩製程,而顯得較為經濟與便利。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
2、3、4、5、6、7、101、102、103...步驟
10、11、100...溝槽式MOSFET功率元件
12、111...晶圓基材
14、112...半導體層
16、116...第一溝槽
18、118...第二溝槽
20...p型基體
21、121...p+
型區
22、122...源極區
24、124...層間介電層
26、126...閘極金屬層
27、127...源極金屬層
28、30...接觸插塞
32...閘極氧化層
34...多晶矽材料
36、136...汲極金屬層
38...保護環摻雜區
113...原始表面
114...背面
119...光阻層
128...閘極接觸插塞
130...源極接觸插塞
132...閘極絕緣層
134、134a、134b、134c...閘極材料層
140...斜向離子佈植製程
142...第一摻雜物層
144...離子佈植製程
146...第二摻雜物層
148...基體
150...底部輕摻雜層
第1圖顯示一習知之溝槽式MOSFET功率元件截面示意圖。
第2圖顯示另一習知之溝槽式MOSFET功率元件截面示意圖。
第3圖顯示習知之製造功率元件時使用到光罩的主要步驟流程圖。
第4圖顯示依據本發明的方法製造功率元件時使用到光罩的主要步驟流程圖。
第5至12圖繪示的是依據本發明的製作功率元件的方法的一具體實施例的示意圖。
111...晶圓基材
112...半導體層
113...原始表面
114...背面
116...第一溝槽
118...第二溝槽
132...閘極絕緣層
134a...閘極材料層
140...斜向離子佈植製程
142...第一摻雜物層
Claims (13)
- 一種製造功率半導體元件的方法,包括:提供一基底,該基底具有一原始表面與一背面;經由一第一光罩對該基底進行蝕刻,以形成一第一溝槽及至少一第二溝槽,其中,該第一溝槽的寬度大於該至少一第二溝槽的寬度;於該基底上全面形成一閘極絕緣層,覆蓋該原始表面、及該第一溝槽與該至少一第二溝槽的側壁及底面;進行一第一沉積製程,以於該閘極絕緣層上全面形成一第一閘極材料層,其中該第一溝槽未被該第一閘極材料層填滿;進行一等向性或異向性回蝕刻製程,以將位於該第一溝槽內及該基底原始表面上方的該第一閘極材料層移除;全面進行一斜向(tilt)離子佈植製程,以於該基底的表層中形成一第一摻雜物層,該基底的表層包括該基底位於原始表面的表層及位於該第一溝槽的側壁與底面位置的表層;進行一第二沉積製程,以於該基底上全面形成一第二閘極材料層,其中該第一閘極材料層與該第二閘極材料層合而為一閘極材料層,該閘極材料層填滿該第一溝槽及該至少一第二溝槽,並且覆蓋該基底原始表面上的該閘極絕緣層;進行一異向性回蝕刻製程,以部分移除該閘極材料層,俾露出位於該基底原始表面上的閘極絕緣層;全面進行一第一離子佈植製程,以於該基底原始表面的表層中形成一第二摻雜物層;及進行一驅入(drive in)製程,以將該第一摻雜物層及該第二摻雜物層的摻雜物往該基底的更深層延伸分佈,俾形成一基體於該基底中及形成一底部輕摻雜層圍繞該第一溝槽底部並與該基體相鄰。
- 如請求項1所述之方法,其中該第一摻雜物層包括p型摻雜物。
- 如請求項1所述之方法,其中該第二摻雜物層包括p型摻雜物。
- 如請求項1所述之方法,其中該閘極材料層包括經摻雜的多晶矽。
- 如請求項1所述之方法,其中該基底包括一半導體晶圓基材及一形成於該半導體晶圓基材上的半導體層。
- 如請求項5所述之方法,其中該半導體層包括一n型輕摻雜磊晶層。
- 如請求項5所述之方法,其中該半導體晶圓基材包括一n型重摻雜區。
- 如請求項1所述之方法,其中該基體係為一p型基體。
- 如請求項1所述之方法,其中該底部輕摻雜層為一p型輕摻雜層。
- 如請求項1所述之方法,進一步經由一第二光罩進行一第二離子佈植,而於該基體上形成至少一源極區。
- 如請求項10所述之方法,其中該基體包括至少一接觸插塞預定區域,及進一步經由一第三光罩進行一第三離子佈植,於該至少一接觸插塞預定區域形成一重摻雜區。
- 如請求項11所述之方法,進一步於該基底上方全面形成一層間介電層,通過該至少一源極區與該層間介電層形成至少一源極接觸插塞,通過該層間介電層形成一閘極接觸插塞,及於該層間介電層上形成至少一源極金屬層及一閘極金屬層,其中,該至少一源極接觸插塞電連接該至少一重摻雜區與該至少一源極金屬層,及該閘極接觸插塞電連接該第一溝槽中的閘極材料層與該閘極金屬層。
- 如請求項10所述之方法,進一步於該基底的該背面形成一汲極金屬層。
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