TWI446459B - 具有超級介面之功率電晶體元件之製作方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 102
- 239000002019 doping agent Substances 0.000 claims description 96
- 238000000034 method Methods 0.000 claims description 88
- 239000000758 substrate Substances 0.000 claims description 69
- 239000004065 semiconductor Substances 0.000 claims description 53
- 238000005468 ion implantation Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 23
- 230000010354 integration Effects 0.000 claims description 15
- 239000011521 glass Substances 0.000 claims description 13
- 239000005368 silicate glass Substances 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 5
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- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 239000005388 borosilicate glass Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
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- 239000013078 crystal Substances 0.000 claims description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 2
- AYHOQSGNVUZKJA-UHFFFAOYSA-N [B+3].[B+3].[B+3].[B+3].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-] Chemical compound [B+3].[B+3].[B+3].[B+3].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-].[O-][Si]([O-])([O-])[O-] AYHOQSGNVUZKJA-UHFFFAOYSA-N 0.000 claims 1
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
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- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/26—Bombardment with radiation
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Description
本發明係關於一種具有超級介面之功率電晶體元件之製作方法,尤指一種具有超級介面之功率電晶體元件之製作方法,用於調整超級介面鄰近溝槽側壁之摻雜濃度。
在功率電晶體元件中,汲極與源極間導通電阻RDS(on)的大小係與元件之功率消耗成正比,因此降低導通電阻RDS(on)的大小可減少功率電晶體元件所消耗之功率。於導通電阻RDS(on)中,用於耐壓之磊晶層所造成之電阻值所佔的比例係為最高。雖然增加磊晶層中導電物質之摻雜濃度可降低磊晶層之電阻值,但磊晶層的作用係為用於承受高電壓。若增加摻雜濃度會降低磊晶層之崩潰電壓,因而降低功率電晶體元件之耐壓能力。
為了維持或提升功率電晶體元件之耐壓能力,並降低磊晶層之電阻值,目前已發展出一種具有超級介面(super junction)之功率電晶體元件,以兼具高耐壓能力以及低導通電阻。習知製作功率電晶體元件之方法是在N型基底上形成一N型磊晶層,然後利用蝕刻製程於N型磊晶層中形成複數個深溝槽。接著,在深溝槽中填入摻雜物來源層,並利用高溫擴散之方法將摻雜物來源層中之P型摻雜物擴散至N型磊晶層中,以形成P型摻雜區,且N型磊晶層與P型摻雜區構成垂直基底之PN接面,即超級介面。然而,P型摻雜區是利用擴散方式所形成,因此其摻雜濃度是隨著越接近深溝槽之側壁而越高。藉此,P型摻雜區之表面摻雜濃度容易過高,使超級介面中之電洞濃度與電子濃度分布不均勻,導致超級介面的耐壓能力不佳。
有鑑於此,降低用於形成超級介面之摻雜區的表面摻雜濃度,以解決超級介面結構中之電洞濃度與電子濃度分布不均勻之問題實為業界努力之目標。
本發明之主要目的在於提供一種具有超級介面之功率電晶體元件之製作方法,以解決超級介面中之電洞濃度與電子濃度分布不均勻之問題。
為達上述之目的,本發明提供一種具有超級介面之功率電晶體元件之製作方法。首先,提供一半導體基底,具有一第一導電類型。然後,於半導體基底中形成至少一溝槽。接著,於溝槽中填入一摻雜物來源層,其中摻雜物來源層包括複數個摻雜物,且摻雜物具有不同於第一導電類型之一第二導電類型。隨後,進行一第一熱趨入製程,將摻雜物擴散至半導體基底中,以於溝槽之二側之半導體基底中分別形成二擴散摻雜區,其中各擴散摻雜區鄰近溝槽之側壁之摻雜濃度不同於各擴散摻雜區遠離溝槽之側壁之摻雜濃度。接著,移除摻雜物來源層。然後,進行一斜角度離子佈植(tilt-angle ion implantation)製程與一第二熱趨入製程,以調整鄰近溝槽之側壁之各擴散摻雜區之摻雜濃度。
為達上述之目的,本發明另提供一種具有超級介面之功率電晶體元件之製作方法。首先,提供一半導體基底,具有一第一導電類型。接著,於半導體基底中形成至少一溝槽。然後,於溝槽中填入一第一摻雜物來源層,其中第一摻雜物來源層包括第一摻雜物,且第一摻雜物具有不同於第一導電類型之一第二導電類型。隨後,進行一第一熱趨入製程,將第一摻雜物擴散至半導體基底中,以於溝槽之二側之半導體基底中分別形成二擴散摻雜區,其中各擴散摻雜區鄰近溝槽之側壁之摻雜濃度不同於各擴散摻雜區遠離溝槽之側壁之摻雜濃度。接著,移除第一摻雜物來源層。然後,於溝槽中填入一摻雜濃度調整層,並進行一第二熱趨入製程,以調整鄰近溝槽之側壁之各擴散摻雜區之摻雜濃度。隨後,移除摻雜濃度調整層。
本發明利用斜角度離子佈植製程或於溝槽中填入摻雜濃度調整層並搭配熱趨入製程,來調整各擴散摻雜區鄰近各溝槽之側壁之摻雜濃度,藉此由各擴散摻雜區與半導體基底所構成之超級介面可具有均勻之電洞濃度與電子濃度之分布比例,進而可解決超級介面耐壓能力不佳的問題。
請參考第1圖至第8圖,第1圖至第8圖為本發明一較佳實施例之功率電晶體元件之製作方法示意圖。如第1圖所示,首先,提供一半導體基底102,且半導體基底102具有一第一導電類型。接著,於半導體基底102上形成一墊層104,例如二氧化矽(SiO2
),但不限於此。然後,進行一沉積製程,於墊層104上形成一硬遮罩層106,例如氮化矽(Si3
N4
),但不限於此。接著,進行一微影暨蝕刻製程,圖案化墊層104與硬遮罩層106,於墊層104與硬遮罩層106中形成複數個開口108,分別貫穿墊層104與硬遮罩層106並曝露出半導體基底102。然後,以硬遮罩層106為遮罩,進行一蝕刻製程,經由各開口108於半導體基底102中形成複數個溝槽110。於本實施例中,半導體基底102可包括一基材102a,例如矽晶圓,以及一磊晶層102b,且磊晶層102b設於基材102a上。並且,各溝槽110貫穿磊晶層102b,並曝露出基材102a,但本發明不限於此,各溝槽110亦可未貫穿磊晶層102b。此外,本發明之開口108與溝槽110之數量不限為複數個,亦可分別僅為單一個。
如第2圖所示,接著,於各溝槽110中填入一第一摻雜物來源層112,且第一摻雜物來源層112覆蓋於硬遮罩層106上。其中,第一摻雜物來源層112包含有複數個具有不同於第一導電類型之一第二導電類型的第一摻雜物。然後,進行一第一熱趨入製程,將第二導電類型之第一摻雜物擴散至半導體基底102中,以於各溝槽110之二側之半導體基底102中分別形成二擴散摻雜區114,其中各擴散摻雜區114鄰近各溝槽110之側壁之摻雜濃度不同於各擴散摻雜區114遠離各溝槽之側壁之摻雜濃度。於本實施例中,由於各擴散摻雜區114是藉由熱來擴散第一摻雜物而形成的,因此各擴散摻雜區114亦具有第二導電類型,且各擴散摻雜區114之摻雜濃度分布會隨著越接近摻雜物來源層112而具有越高之摻雜濃度。亦即,各擴散摻雜區114鄰近各溝槽110之側壁之摻雜濃度大於各擴散摻雜區114遠離各溝槽之側壁之摻雜濃度,但本發明不限於此。並且,第一導電類型為N型,且第二導電類型為P型,但不限於此,本發明之第一導電類型與第二導電類型亦可互換。另外,本實施例形成第一摻雜物來源層112之材料包含有硼矽玻璃(Boron silicate glass,BSG),但不限於此,本發明之第一摻雜物來源層112之材料可根據所欲形成之擴散摻雜區114的導電類型來決定。例如:當第二導電類型為P型時,形成第一摻雜物來源層之材料包括硼矽玻璃。當第二導電類型為N型時,形成第一摻雜物來源層之材料包括砷矽玻璃(arsenic silicate glass,ASG)或磷矽玻璃(phosphor silicate glass,PSG)。於本發明之其他實施例中,形成P型擴散摻雜區之方法亦可利用P型離子佈植製程,於N型半導體基底中植入P型第一摻雜物,然後進行第一熱趨入製程來形成P型擴散摻雜區。
如第3圖所示,然後,進行另一蝕刻製程,移除第一摻雜物來源層112。隨後,進行一斜角度離子佈植(tilt-angle ion implantation)製程116,以於鄰近各溝槽110之側壁之各P型擴散摻雜區114中植入複數個第二摻雜物。接著,進行一第二熱趨入製程,使第二摻雜物均勻擴散,以調整鄰近各溝槽110之側壁之各P型擴散摻雜區114之摻雜濃度。於本實施例中,斜角度離子佈植製程係為N型,以用於佈植具有N型的第二摻雜物,因此一濃度調整區118會形成於鄰近各溝槽110之側壁之各P型擴散摻雜區114中。由於植入各P型擴散摻雜區114之N型第二摻雜物係與各P型擴散摻雜區114之P型第一摻雜物的導電類型不同,因此於各濃度調整區118中,N型第二摻雜物會與各P型擴散摻雜區114中之部分P型第一摻雜物中和,使各濃度調整區118中之P型第一摻雜物的摻雜濃度被調整至接近各P型擴散摻雜區114之P型第一摻雜物的摻雜濃度。藉此,當各P型擴散摻雜區114鄰近各溝槽110之側壁之摻雜濃度過大時,各P型擴散摻雜區114鄰近各溝槽110之側壁之摻雜濃度可被降低至接近各P型擴散摻雜區114之其他區域的摻雜濃度,且由各P型擴散摻雜區114與N型半導體基底102所構成垂直於N型半導體基底102之PN接面,即超級介面,可具有均勻之電洞濃度與電子濃度之分布比例,進而可解決超級介面耐壓能力不佳的問題。
如第4圖所示,於N型斜角度離子佈植製程116與第二熱趨入製程之後,進行另一沉積製程,於硬遮罩層106上形成一絕緣材料層,例如:氧化矽,且絕緣材料層填滿於各溝槽110中。然後,進行一化學機械研磨(Chemical Mechanical Polishing,CMP)製程,移除位於硬遮罩層106上之絕緣材料層。接著,進行另一蝕刻製程,移除位於開口108中之絕緣材料層,以於各溝槽110中形成一絕緣層120。於本實施例中,絕緣層120之上表面約略與墊層104之上表面位於同一平面,但本發明並不限於此,絕緣層120之上表面亦可介於墊層104之上表面與N型半導體基底102之上表面之間,或與N型半導體基底102之上表面位於同一平面。
如第5圖所示,隨後,移除硬遮罩層106與墊層104,並曝露出N型半導體基底102。接著,進行一熱氧化製程,於N型半導體基底102上形成一閘極絕緣層122。然後,於閘極絕緣層122與絕緣層120上覆蓋一導電材料層,例如多晶矽。隨後,進行另一微影暨蝕刻製程,圖案化導電材料層,以於二相鄰溝槽110之間的N型半導體基底102上分別形成一閘極導電層124,作為功率電晶體元件之閘極,且各閘極導電層124與位於各閘極導電層124以及N型半導體基底102之間的閘極絕緣層122構成一閘極結構126。於本實施例中,閘極絕緣層122之上表面約略與絕緣層120之上表面位於同一平面,但不限於此。於本發明之其他實施例中,閘極結構亦可僅為單一個,而可於其中一溝槽之一側之N型半導體基底上形成閘極結構。
如第6圖所示,接著,以閘極導電層124為遮罩,進行一P型離子佈值製程以及另一熱趨入製程,於各閘極結構126之二側的N型半導體基底102中分別形成二P型基體摻雜區128,且各P型基體摻雜區128與各P型擴散摻雜區114以及P型濃度調降區118相接觸,並與各閘極結構126部分重疊,以作為功率電晶體元件之基極。
如第7圖所示,然後,利用一光罩(圖未示),進行一N型離子佈值製程以及另一熱趨入製程,於各P型基體摻雜區128中形成一N型源極摻雜區130,分別與各閘極結構126部分重疊,以作為功率電晶體元件之源極。本發明之閘極結構126、P型基體摻雜區128以及N型源極摻雜區130並不限分別具有複數個,且亦可僅具有單一個,並可依據實際需求來作相對應調整。
如第8圖所示,接著,於閘極結構126以及絕緣層120上覆蓋一介電層132,例如氧化矽。然後,進行另一微影暨蝕刻製程,於介電層132中形成複數個接觸洞132a,並移除部分閘極絕緣層122以及絕緣層120。各接觸洞132a曝露出N型源極摻雜區130與P型基體摻雜區128。接著,進行另一P型離子佈植製程與另一熱趨入製程,以於各P型基體摻雜區128中形成一P型接觸摻雜區134,以降低源極電阻。然後,進行另一沉積製程,於介電層132上與接觸洞132a之側壁與底部覆蓋一阻障層136,例如鈦或氮化鈦。接著,於阻障層136上形成一源極金屬層138,且源極金屬層138填滿接觸洞132a,並覆蓋於介電層132上。並且,於N型半導體基底102下形成一汲極金屬層140。至此已完成本實施例之功率電晶體元件100。於本實施例中,形成源極金屬層138與汲極金屬層140之步驟可分別包含進行電漿濺鍍或電子束沉積等製程,且源極金屬層138與汲極金屬層140可分別包括鈦、氮化鈦、鋁、鎢等金屬或金屬化合物,但不限於此。
以下將進一步說明本實施例利用N型斜角度離子佈植製程與第二熱趨入製程來降低各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度之功效。請參考第9圖,第9圖為各P型擴散摻雜區與N型半導體基底之摻雜濃度以及距離各溝槽之側壁之長度的關係示意圖。如第9圖所示,第一曲線C1
代表未進行N型斜角度離子佈植製程與第二熱趨入製程之前的各P型擴散摻雜區之摻雜濃度與距離各溝槽之側壁之長度的關係曲線;第二曲線C2
代表進行N型斜角度離子佈植製程與第二熱趨入製程之後的各P型擴散摻雜區之摻雜濃度與距離各溝槽之側壁之長度的關係曲線;以及第三曲線C3
代表N型半導體基底之摻雜濃度與距離各溝槽之側壁之長度之關係曲線。由圖可知,鄰近各溝槽之側壁之各P型擴散摻雜區之摻雜濃度可因進行N型斜角度離子佈植製程與第二熱趨入製程而被降低至接近遠離各溝槽之側壁之各P型擴散摻雜區之摻雜濃度,使由各P型擴散摻雜區與N型半導體基底所構成之超級介面可具有均勻之電洞濃度與電子濃度之分布比例,進而解決超級介面耐壓能力不佳的問題。本發明之N型斜角度離子佈植製程之佈植濃度與深度以及第二熱趨入製程之加熱時間可根據所欲形成之超級介面之耐壓能力來決定。
於本發明之其他實施例中,當各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度小於各P型擴散摻雜區遠離各溝槽之側壁之摻雜濃度時,斜角度離子佈植製程可為P型斜角度離子佈植製程,以於鄰近各溝槽之側壁之各P型擴散摻雜區中植入複數個P型摻雜物。並且,在第二熱趨入製程之後,一濃度提升區會形成於鄰近各溝槽之側壁之各P型擴散摻雜區中,且鄰近各溝槽之側壁之各P型擴散摻雜區之摻雜濃度可被提升至接近遠離各溝槽之側壁之各P型擴散摻雜區之摻雜濃度。藉此,當各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度過低時,利用P型斜角度離子佈植製程與第二熱趨入製程可提升各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度,使超級介面可具有均勻之電洞濃度與電子濃度之分布比例。
以下將進一步說明本實施例利用P型斜角度離子佈植製程與第二熱趨入製程來提升各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度之功效。請參考第10圖,第10圖為各P型擴散摻雜區與N型半導體基底之摻雜濃度以及距離各溝槽之側壁之長度的關係示意圖。如第10圖所示,第四曲線C4
代表未進行P型斜角度離子佈植製程與第二熱趨入製程之前的各P型擴散摻雜區之摻雜濃度與距離各溝槽之側壁之長度的關係曲線;第五曲線C5
代表進行P型斜角度離子佈植製程與第二熱趨入製程之後的各P型擴散摻雜區之摻雜濃度與距離各溝槽之側壁之長度的關係曲線;以及第六曲線C6
代表N型半導體基底之摻雜濃度與距離各溝槽之側壁之長度之關係曲線。由此可知,鄰近各溝槽之側壁之各P型擴散摻雜區之摻雜濃度可因進行P型斜角度離子佈植製程與第二熱趨入製程而被提升,使由各P型擴散摻雜區與N型半導體基底所構成之超級介面可具有均勻之電洞濃度與電子濃度之分布比例,進而解決超級介面耐壓能力不佳的問題。本發明之P型斜角度離子佈植製程之佈植濃度與深度以及第二熱趨入製程之加熱時間可根據所欲形成之超級介面之耐壓能力來決定。
本發明之功率電晶體元件之超級介面結構之製作方法並不以上述實施例為限。下文將繼續揭示本發明之其它實施例或變化形,然為了簡化說明並突顯各實施例或變化形之間的差異,下文中使用相同標號標注相同元件,並不再對重複部分作贅述。
請參考第11圖與第12圖,且一併參考第1圖與第2圖以及第4圖至第8圖。第11圖與第12圖為本發明另一較佳實施例之超級介面結構之製作方法。相較於上述實施例,本實施例之製作方法係利用第二摻雜物來源層來調整P型擴散摻雜區之摻雜濃度。本實施例之製作方法於形成P型擴散摻雜區之步驟之前與上述實施例相同,因此各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度大於各P型擴散摻雜區遠離各溝槽之側壁之摻雜濃度,如第1圖與第2圖所示。接著,如第11圖所示,移除第一摻雜物來源層112,然後於各溝槽中填入一摻雜濃度調整層202。其中,摻雜濃度調整層202係由一第二摻雜物來源層所構成,且第二摻雜物來源層包括複數個第二摻雜物。接著,進行第二熱趨入製程,使第二摻雜物朝P型擴散摻雜區114擴散,以調整鄰近各溝槽110之側壁之各P型擴散摻雜區114之摻雜濃度。然後,如第12圖所示,移除摻雜濃度調整層202。本實施例之後續步驟與上述實施例相同,如第4圖至第8圖所示,因此不再在此贅述。於本實施例中,第二摻雜物來源層係為N型,因此第二摻雜物為N型,且濃度調整區118會形成於鄰近各溝槽110之側壁之各P型擴散摻雜區114中。並且,形成第二摻雜物來源層之材料包括砷矽玻璃或磷矽玻璃,但不限於此。本發明形成第一摻雜物來源層與第二摻雜物來源層之材料係依據所具有之第一摻雜物與第二摻雜物的導電類型來決定。例如:當第一導電類型為N型,第二導電類型為P型時,形成第一摻雜物來源層112之材料包含有硼矽玻璃,且形成第二摻雜物來源層之材料包括砷矽玻璃或磷矽玻璃。當第一導電類型為P型,且第二導電類型為N型時,形成第一摻雜物來源層112之材料包括砷矽玻璃或磷矽玻璃,且形成第二摻雜物來源層之材料包括硼矽玻璃,但本發明不以此為限。
另外,由於植入各P型擴散摻雜區114之N型第二摻雜物係與各P型擴散摻雜區114之P型第一摻雜物的導電類型不同,因此於各濃度調整區118中,N型第一摻雜物會與各P型擴散摻雜區114中之部分P型第一摻雜物中和,使各濃度調整區118中之P型第一摻雜物的摻雜濃度被調整至接近各P型擴散摻雜區114之P型第一摻雜物的摻雜濃度。藉此,當各P型擴散摻雜區114鄰近各溝槽110之側壁之摻雜濃度過大時,各P型擴散摻雜區114鄰近各溝槽110之側壁之摻雜濃度可被降低至接近各P型擴散摻雜區114之遠離各溝槽110之側壁之摻雜濃度,且由各P型擴散摻雜區114與N型半導體基底102所構成之超級介面可具有均勻之電洞濃度與電子濃度之分布比例,進而可解決超級介面耐壓能力不佳的問題。
於本發明之其他實施例中,形成摻雜濃度調整層之材料亦可包括單晶矽、多晶矽、非晶矽或矽氧化物等未摻雜材料,以於進行第二熱趨入製程時,藉由擴散原理將鄰近各溝槽之側壁之各P型擴散摻雜區的P型第一摻雜物擴散至摻雜濃度調整層中,進而降低鄰近各溝槽之側壁之P型擴散摻雜區的摻雜濃度。
此外,於本發明之其他實施例中,當各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度小於各P型擴散摻雜區遠離各溝槽之側壁之摻雜濃度時,第二摻雜物來源層之第二摻雜物亦可為P型。此時,形成第二摻雜物來源層之材料係與形成第一摻雜物來源層之材料相同,且包括硼矽玻璃,但不限於此。藉此,當各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度過低時,利用填入第二摻雜物來源層與第二熱趨入製程可於鄰近各溝槽之側壁之各P型擴散摻雜區中形成濃度提升區,並提升各P型擴散摻雜區鄰近各溝槽之側壁之摻雜濃度,使超級介面可具有均勻之電洞濃度與電子濃度之分布比例。
綜上所述,本發明利用斜角度離子佈植製程或於溝槽中填入摻雜濃度調整層並搭配熱趨入製程,在各擴散摻雜區鄰近各溝槽之側壁之摻雜濃度過高時降低其摻雜濃度,而在各擴散摻雜區鄰近各溝槽之側壁之摻雜濃度過低時提升其摻雜濃度,藉此由各擴散摻雜區與半導體基底所構成之超級介面可具有均勻之電洞濃度與電子濃度之分布比例,進而可解決超級介面耐壓能力不佳的問題。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100...功率電晶體元件
102...半導體基底
102a...基材
102b...磊晶層
104...墊層
106...硬遮罩層
108...開口
110...溝槽
112...第一摻雜物來源層
114...擴散摻雜區
116...斜角度離子佈植製程
118...濃度調整區
120...絕緣層
122...閘極絕緣層
124...閘極導電層
126...閘極結構
128...基體摻雜區
130...源極摻雜區
132...介電層
132a...接觸洞
134...接觸摻雜區
136...阻障層
138...源極金屬層
140...汲極金屬層
202...摻雜濃度調整層
C1
...第一曲線
C2
...第二曲線
C3
...第三曲線
C4
...第四曲線
C5
...第五曲線
C6
...第六曲線
第1圖至第8圖為本發明一較佳實施例之功率電晶體元件之製作方法示意圖。
第9圖為各P型擴散摻雜區與N型半導體基底之摻雜濃度以及與各溝槽之側壁間之距離示意圖。
第10圖為各P型擴散摻雜區與N型半導體基底之摻雜濃度以及與各溝槽之側壁間之距離示意圖。
第11圖與第12圖為本發明另一較佳實施例之超級介面結構之製作方法。
102...半導體基底
102a...基材
102b...磊晶層
104...墊層
106...硬遮罩層
108...開口
110...溝槽
114...擴散摻雜區
116...斜角度離子佈植製程
118...濃度調整區
Claims (15)
- 一種具有超級介面之功率電晶體元件之製作方法,包括:提供一半導體基底,具有一第一導電類型;於該半導體基底中形成至少一溝槽;於該溝槽中填入一摻雜物來源層,其中該摻雜物來源層包括複數個摻雜物,且該等摻雜物具有不同於該第一導電類型之一第二導電類型;進行一第一熱趨入製程,將該等摻雜物擴散至該半導體基底中,以於該溝槽之二側之該半導體基底中分別形成二擴散摻雜區,其中各該擴散摻雜區鄰近該溝槽之側壁之摻雜濃度不同於各該擴散摻雜區遠離該溝槽之側壁之摻雜濃度;移除該摻雜物來源層;以及進行一斜角度離子佈植(tilt-angle ion implantation)製程與一第二熱趨入製程,以調整鄰近該溝槽之側壁之各該擴散摻雜區之摻雜濃度。
- 如請求項1所述之具有超級介面之功率電晶體元件之製作方法,其中各該擴散摻雜區鄰近該溝槽之側壁之摻雜濃度大於各該擴散摻雜區遠離該溝槽之側壁之摻雜濃度,且該斜角度離子佈植製程係於鄰近該溝槽之側壁之各該擴散摻雜區中植入複數個具有該第一導電類型之摻雜物。
- 如請求項1所述之具有超級介面之功率電晶體元件之製作方法,其中各該擴散摻雜區鄰近該溝槽之側壁之摻雜濃度小於各該擴散摻雜區遠離該溝槽之側壁之摻雜濃度,且該斜角度離子佈植製程係於鄰近該溝槽之側壁之各該擴散摻雜區中植入複數個具有該第二導電類型之離子。
- 如請求項1所述之具有超級介面之功率電晶體元件之製作方法,其中該第二導電類型為P型,且形成該摻雜物來源層之材料包括硼矽玻璃(boron-silicate glass,BSG)。
- 如請求項1所述之具有超級介面之功率電晶體元件之製作方法,其中該第二導電類型為N型,且形成該摻雜物來源層之材料包括砷矽玻璃(arsenic silicate glass,ASG)或磷矽玻璃(phosphor silicate glass,PSG)。
- 如請求項1所述之具有超級介面之功率電晶體元件之製作方法,其中於該斜角度離子佈植製程與該第二熱趨入製程之後,該製作方法另包括:於該溝槽中形成一絕緣層;於該溝槽之至少一該側之該半導體基底上形成一閘極結構;於該閘極結構之二側的該半導體基底中分別形成二基體摻雜區,且各該基體摻雜區分別與各該擴散摻雜區相接觸,其中該等基體摻雜區具有該第二導電類型;以及於各該基體摻雜區中分別形成一源極摻雜區。
- 一種具有超級介面之功率電晶體元件之製作方法,包括:提供一半導體基底,具有一第一導電類型;於該半導體基底中形成至少一溝槽;於該溝槽中填入一第一摻雜物來源層,其中該第一摻雜物來源層包括複數個第一摻雜物,且該等第一摻雜物具有不同於該第一導電類型之一第二導電類型;進行一第一熱趨入製程,將該等第一摻雜物擴散至該半導體基底中,以於該溝槽之二側之該半導體基底中分別形成二擴散摻雜區,其中各該擴散摻雜區鄰近該溝槽之側壁之摻雜濃度不同於各該擴散摻雜區遠離該溝槽之側壁之摻雜濃度;移除該第一摻雜物來源層;於該溝槽中填入一摻雜濃度調整層,並進行一第二熱趨入製程,以調整鄰近該溝槽之側壁之各該擴散摻雜區之摻雜濃度;以及移除該摻雜濃度調整層。
- 如請求項7所述之具有超級介面之功率電晶體元件之製作方法,其中該摻雜濃度調整層係由一第二摻雜物來源層所構成,且該第二摻雜物來源層包括複數個具有該第一導電類型之第二摻雜物。
- 如請求項8所述之具有超級介面之功率電晶體元件之製作方法,其中該第一導電類型為N型,該第二導電類型為P型,形成該第一摻雜物來源層之材料包括硼矽玻璃,且形成該第二摻雜物來源層之材料包括砷矽玻璃(arsenic silicate glass,ASG)或磷矽玻璃(phosphor silicate glass,PSG)。
- 如請求項8所述之具有超級介面之功率電晶體元件之製作方法,其中該第一導電類型為P型,該第二導電類型為N型,形成該第一摻雜物來源層之材料包括砷矽玻璃或磷矽玻璃,且形成該第二摻雜物來源層之材料包括硼矽玻璃。
- 如請求項7所述之具有超級介面之功率電晶體元件之製作方法,其中該摻雜濃度調整層係由一第二摻雜物來源層所構成,且該第二摻雜物來源層包括複數個具有該第二導電類型之第二摻雜物。
- 如請求項11所述之具有超級介面之功率電晶體元件之製作方法,其中該第二導電類型為P型,且形成該第一摻雜物來源層與該第二摻雜物來源層之材料分別包括硼矽玻璃。
- 如請求項11所述之具有超級介面之功率電晶體元件之製作方法,其中該第二導電類型為N型,且形成該第一摻雜物來源層與該第二摻雜物來源層之材料分別包括砷矽玻璃或磷矽玻璃。
- 如請求項7所述之具有超級介面之功率電晶體元件之製作方法,其中形成該摻雜濃度調整層之材料包括單晶矽、多晶矽、非晶矽或矽氧化物。
- 如請求項7所述之具有超級介面之功率電晶體元件之製作方法,其中於移除該摻雜濃度調整層之後,該製作方法另包括:於該溝槽中形成一絕緣層;於該溝槽之至少一該側之該半導體基底上形成一閘極結構;於該閘極結構之二側的該半導體基底中分別形成二基體摻雜區,且各該基體摻雜區分別與各該擴散摻雜區相接觸,其中該等基體摻雜區具有該第二導電類型;以及於各該基體摻雜區中分別形成一源極摻雜區。
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