TWI462295B - 溝渠型功率電晶體元件及其製作方法 - Google Patents

溝渠型功率電晶體元件及其製作方法 Download PDF

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TWI462295B
TWI462295B TW100141614A TW100141614A TWI462295B TW I462295 B TWI462295 B TW I462295B TW 100141614 A TW100141614 A TW 100141614A TW 100141614 A TW100141614 A TW 100141614A TW I462295 B TWI462295 B TW I462295B
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layer
region
type
epitaxial layer
power transistor
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TW201320339A (zh
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Yung Fa Lin
Shou Yi Hsu
Meng Wei Wu
Main Gwo Chen
Chia Hao Chang
Chia Wei Chen
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Anpec Electronics Corp
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Priority to CN2012100162191A priority patent/CN103107194A/zh
Priority to US13/543,877 priority patent/US8940606B2/en
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Priority to US14/331,202 priority patent/US20140327039A1/en
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Description

溝渠型功率電晶體元件及其製作方法
本發明係關於一種溝渠型功率電晶體元件及其製作方法，尤指一種具有超級介面之溝渠型功率電晶體元件及其製作方法。
功率電晶體元件常應用於電源管理的部分，例如，切換式電源供應器、電腦中心或周邊電源管理IC、背光板電源供應器或馬達控制等等用途，其種類包含有絕緣閘雙極性電晶體(insulated gate bipolar transistor，IGBT)、金氧半場效電晶體(metal-oxide-semiconductor field-effect transistor，MOSFET)與雙載子接面電晶體(bipolar junction transistor，BJT)等元件。
請參考第1圖，第1圖係為習知溝渠型功率電晶體元件之剖面示意圖。如第1圖所示，習知溝渠型功率電晶體元件10包含一N型基材12、一N型磊晶層14、複數個溝渠16、一閘極絕緣層18、複數個閘極20以及一源極金屬層22。N型磊晶層14設置於N型基材12上，且各溝渠16係位於N型磊晶層14上。閘極絕緣層18覆蓋於各溝渠16之表面，且各閘極20填充於各溝渠16中。並且，閘極絕緣層18將各閘極20與源極金屬層22電性隔離。N型磊晶層14上另形成複數個P型基體摻雜區24，且各P型基體摻雜區24上另形成一N型源極摻雜區26，而各P型基體摻雜區24中另佈植一P型接觸摻雜區28。各P型接觸摻雜區28係藉由一接觸插塞30電性連接至源極金屬層22。此外，習知溝渠型功率電晶體元件10之汲極金屬層32係設置於N型基材12之下表面。
為了提高溝渠型功率電晶體元件之耐壓能力，已發展出在N型基材上形成P型磊晶層與N型磊晶層沿水平方向依序交替設置之結構，這樣的功率電晶體元件又稱為超級介面功率電晶體元件。然而，溝渠型功率電晶體元件之閘極與作為汲極之N型磊晶層具有較大之重疊面積，且其間之閘極絕緣層具有較小之厚度，造成較高的米勒電容，進而導致較高的切換損失(switching loss)，影響元件效能。
有鑑於此，降低溝渠型功率電晶體元件之米勒電容實為業界努力之目標。
本發明之主要目的之一在於提供一種溝渠型功率電晶體元件及其製作方法，以降低米勒電容，並增加耐壓。
為達上述之目的，本發明提供一種溝渠型功率電晶體元件，包括一基底、一磊晶層、一第一擴散摻雜區、一源極摻雜區、一閘極結構、一第二擴散摻雜區以及一終端導電層。基底具有一第一導電類型，且基底具有一主動區以及一終端區。磊晶層設於基底上，且具有不同於第一導電類型之一第二導電類型，其中磊晶層具有至少一第一穿孔以及至少一第二穿孔，分別貫穿磊晶層，第一穿孔位於主動區，且第二穿孔位於終端區。第一擴散摻雜區設於第一穿孔一側之磊晶層中，且與基底相接觸，其中第一擴散摻雜區具有第一導電類型。源極摻雜區設於第一擴散摻雜區之正上方之磊晶層中，且源極摻雜區具有第一導電類型。閘極結構設於第一擴散摻雜區與源極摻雜區之間的第一穿孔中。第二擴散摻雜區設於第二穿孔一側之磊晶層中，且與基底相接觸，其中第二擴散摻雜區具有第一導電類型。終端導電層設於第二擴散摻雜區上方之第二穿孔中。
為達上述之目的，本發明提供一種溝渠型功率電晶體元件之製作方法。首先，提供一基底，且基底具有一第一導電類型，其中基底具有一主動區以及一終端區。然後，於基底上形成一磊晶層，且磊晶層具有不同於第一導電類型之一第二導電類型。接著，於磊晶層中形成至少一第一穿孔與至少一第二穿孔，貫穿磊晶層，其中第一穿孔位於主動區，且第二穿孔位於終端區。隨後，於第一穿孔與第二穿孔中分別填入一摻質來源層。之後，於第一穿孔一側之磊晶層中形成一第一擴散摻雜區以及於第二穿孔一側之磊晶層中形成一第二擴散摻雜區，且於第一穿孔中形成一閘極結構，其中第一擴散摻雜區與第二擴散摻雜區具有第一導電類型。接下來，於第一穿孔之一側的磊晶層中形成一源極摻雜區，且源極摻雜區位於第一擴散摻雜區之上方，其中源極摻雜區具有第一導電類型，且閘極結構位於第一擴散摻雜區與源極摻雜區之間。
綜上所述，本發明藉由於第一穿孔中填入具有絕緣特性的摻質來源層，且利用熱驅入製程將其中具有導電特性之摻質擴散至磊晶層中，以形成在垂直方向上與閘極導電層部分重疊的第一擴散摻雜區，且與具有第二導電類型之磊晶層形成一超級介面。此外，第一穿孔之底部填有具有絕緣特性之摻質來源層，藉此可減少溝渠型功率電晶體元件之閘極與汲極之間的寄生電容，進而降低米勒電容以及切換損失，且提升元件效能。
請參考第2圖至第9圖，第2圖至第9圖為本發明一較佳實施例之溝渠型功率電晶體元件之製作方法示意圖，其中第9圖為本發明較佳實施例之溝渠型功率電晶體元件之剖面示意圖。如第2圖所示，首先提供具有一第一導電類型之一基底102，且基底102具有用於設置主動元件之一主動區(active region)102a以及用於設置終端結構(termination structure)之一終端區(termination region)102b。然後，利用一磊晶製程，於基底102上形成一磊晶層104，且磊晶層104具有不同於第一導電類型之一第二導電類型。隨後，進行一沉積製程，於磊晶層104上形成一氧化層(圖未示)。接著，進行一第二導電類型之離子佈植製程與一熱驅入製程，以於磊晶層104中形成一井區106，且井區106具有第二導電類型。然後，移除氧化層，並於磊晶層104上形成一硬遮罩層108，例如氮化矽(Si3 N4 )或二氧化矽(SiO2 )，且硬遮罩層108具有至少一第一開口108a與至少一第二開口108b。第一開口108a位於主動區102a中，且第二開口108b位於終端區102b中。本實施例以第一導電類型為P型且第二導電類型為N型為例來作描述，但不限於此，第一導電類型與第二導電類型亦可互換。P型基底102可為矽基板或矽晶圓，其可作為溝渠型功率電晶體元件之汲極。並且，本實施例之N型井區106係用於調整溝渠型功率電晶體元件之通道區的濃度，以控制溝渠型功率電晶體元件之臨界電壓(threshold voltage)。本發明並不限需形成N型井區106，而亦可未形成氧化層與N型井區。此外，第一開口108a與第二開口108b之數量不限為單一個，亦可分別為複數個。
如第3圖所示，以硬遮罩層108為遮罩，對第一開口108a與第二開口108b所曝露出之N型磊晶層104進行一蝕刻製程，以於N型磊晶層104中形成至少一第一穿孔104a與至少一第二穿孔104b，貫穿N型磊晶層104。第一穿孔104a係對應第一開口108a，且位於主動區102a中。第二穿孔104b對應第二開口108b，且位於終端區102b中。並且，第一穿孔104a與第二穿孔104b係藉由第一開口108a與第二開口108b所形成，因此其數量亦不限為單一個，而可分別為複數個。此外，於本實施例中，第一穿孔與第二穿孔延伸至P型基底中。
如第4圖所示，去除硬遮罩層108，然後，於第一穿孔104a與第二穿孔104b中分別填入包含有複數個P型摻質的一摻質來源層110。接著利用研磨回蝕刻方法去除N型磊晶層104上方之摻質來源層110，以及第一穿孔104a與第二穿孔104b中之部分摻質來源層110，使摻質來源層110之上表面高於N型井區106之底部。於本實施例中，形成摻質來源層110之材料包含有硼矽玻璃(Boron silicate glass，BSG)，但不限於此。並且，本發明之摻質來源層110之上表面並不限高於N型井區106之底部，亦可約略與N型井區106之底部位於同一平面或稍微低於N型井區106之底部。於本發明之其他實施例中，於填入摻質來源層之步驟之前亦可選擇性地於第一穿孔與第二穿孔的表面形成一緩衝層，其中緩衝層可利用熱氧化製程來形成，且其組成包含有氧化矽。並且，於填入摻質來源層之步驟之後另可選擇性地進行一N型離子佈植製程，以調整鄰近第一穿孔兩側之N型井區之摻雜濃度，進而控制溝渠型功率電晶體元件之臨界電壓。
如第5圖所示，然後，進行一熱氧化製程，於N型磊晶層104上方以及第一穿孔104a與第二穿孔104b之側壁形成一第三絕緣層114。同時，在進行熱氧化製程中，位於摻質來源層110中之P型摻質亦會受到熱氧化製程影響而擴散至N型磊晶層104中，以於各第一穿孔104a兩側之N型磊晶層104中分別形成一P型第一擴散摻雜區116，且於各第二穿孔104b兩側之N型磊晶層104中分別形成一P型第二擴散摻雜區118。藉此，P型第一擴散摻雜區116與P型第二擴散摻雜區118可與N型磊晶層104相接觸，以分別形成一PN接面，亦即超級介面，且PN接面係約略垂直N型基底102。並且，第一穿孔104a中之摻質來源層110成為一第一絕緣層110a，且第二穿孔104b中之摻質來源層110成為一第二絕緣層110b。隨後，利用一微影蝕刻製程移除位於終端區102b之第三絕緣層114，且進行一沉積製程，於終端區102b之N型磊晶層104與第二絕緣層110b上以及主動區102a之第一絕緣層110a與第三絕緣層114上形成一導電層122，且導電層122填入第一穿孔104a與第二穿孔104b中。於本實施例中，P型第一擴散摻雜區116係與P型基底102相接觸，而可作為溝渠型功率電晶體元件之汲極。並且，第三絕緣層114係由氧化矽所構成，但本發明並不限利用熱氧化製程來形成第三絕緣層114，且形成第三絕緣層114之步驟與形成P型第一擴散摻雜區與P型第二擴散摻雜區之步驟不限同時進行。於本發明之其他實施例中，第三絕緣層114亦可利用沉積製程搭配微影暨蝕刻製程來形成，且其材料亦不限由氧化矽所構成，而可為其他絕緣材料。並且，形成P型第一擴散摻雜區116以及P型第二擴散摻雜區118之步驟包括一熱驅入製程，將P型摻質擴散至N型磊晶層104中。另外，導電層122可為例如多晶矽等導電材料所構成。
如第6圖所示，然後，進行一回蝕刻製程或一化學機械研磨製程(chemical mechanical polishing，CMP)，移除位於第一穿孔104a與第二穿孔104b外之第三絕緣層114以及導電層122，以於第一穿孔104a中形成一閘極絕緣層114a以及一閘極導電層122a，且於第二穿孔104b中形成一終端導電層122b，其中位於第一穿孔104a中之閘極絕緣層114a與閘極導電層122a係構成一閘極結構124，且閘極絕緣層114a位於閘極導電層122a與N型井區106之間。於本實施例中，位於第一穿孔104a之閘極導電層122a係藉由閘極絕緣層114a以及第一絕緣層110a與P型第一擴散摻雜區116以及N型磊晶層104電性隔離，而作為溝渠型功率電晶體元件之閘極。值得注意的是，閘極導電層122a之下方係為第一絕緣層110a，從閘極導電層122a延伸至P型基底102，因此可大幅減少溝渠型功率電晶體元件之閘極與汲極之間的寄生電容，進而降低米勒電容以及切換損失(switching loss)，且提升元件效能。並且，位於終端區102b之終端導電層122b、第二擴散摻雜區118以及N型磊晶層104係構成一終端結構，且終端導電層122b可作為一耦合導體(coupling conductor)，使終端區102b之電壓維持平緩下降之趨勢，並且使電壓截止在特定區域。
如第7圖所示，接著，於N型磊晶層104上形成一圖案化光阻層126，以暴露出第一穿孔104a兩側之N型磊晶層104之一部分以及閘極結構124。然後，進行一P型離子佈植製程，以於第一穿孔104a兩側之N型磊晶層104中分別形成二P型源極摻雜區128，作為溝渠型功率電晶體元件之源極，其中各P型源極摻雜區128係為於各P型第一擴散摻雜區116之正上方之N型磊晶層104中。並且，閘極結構124係位於各P型第一擴散摻雜區116與其相對應之P型源極摻雜區128之間的第一穿孔104a中，且位於各P型第一擴散摻雜區116與其相對應之P型源極摻雜區128之間且鄰近閘極絕緣層114a的N型井區106係作為溝渠型功率電晶體元件之通道區，約略垂直P型基底102。由此可知，本實施例之功率電晶體元件係為一垂直型功率電晶體元件。
如第8圖所示，其後，移除圖案化光阻層126，並於N型磊晶層104與閘極結構124上覆蓋一介電層130。接著，進行一微影暨蝕刻製程，於主動區102a之介電層130中形成二接觸洞132，且各接觸洞分別暴露出N型磊晶層104以及各P型源極摻雜區128之一部分。繼以進行一N型離子佈植製程，於各接觸洞132所暴露出之N型磊晶層104中形成一N型接觸摻雜區134，且各N型接觸摻雜區134與各P型源極摻雜區128相接觸。接著，進行退火(anneal)處理，以活化N型接觸摻雜區134之N型摻質。其中，上述N型接觸摻雜區134可提升金屬與半導體層接面之導電性，以利電流於接面之傳輸。
如第9圖所示，接下來，於介電層130上與各接觸洞132中形成一金屬層。然後，進行一微影暨蝕刻製程，移除中終端區102b之金屬層，以於主動區102a中形成一源極金屬層136。並且，於P型基底102下形成一汲極金屬層138。於本實施例中，形成源極金屬層136之步驟可包含進行電漿濺鍍或電子束沉積等製程，且源極金屬層136可包括鈦、氮化鈦、鋁、鎢等金屬或金屬化合物，但不限於此。至此已完成本實施例之溝渠型功率電晶體元件100。於本發明之其他實施例中，於形成源極金屬層之前亦可先於接觸洞中形成接觸插塞，或先於接觸洞底部之N型磊晶層上形成一阻障層(圖未示)，其組成可包含鈦、氮化鈦、鉭、氮化鉭等金屬或金屬化合物。阻障層乃用以避免接觸洞內之金屬層電遷移(electro migration)或擴散至N型磊晶層。值得一提的是，本實施例之溝渠型功率電晶體元件100係為P型功率電晶體元件，相較於N型功率電晶體元件而言，擁有較佳的順向偏壓安全操作區間以及抗單粒子燒毀之特性。且本實施例具有超級介面之P型溝渠型功率電晶體元件100亦可以有效提高耐壓以及降低開啟電阻(Rdson)。
綜上所述，本發明藉由於第一穿孔中填入具有絕緣特性的摻質來源層，且利用熱驅入製程將其中具有導電特性之摻質擴散至磊晶層中，以形成超級介面。並且，具有絕緣特性的摻質來源層可在閘極導電層之下方形成一厚絕緣層，藉此可減少溝渠型功率電晶體元件之閘極與汲極之間的寄生電容，進而降低米勒電容以及切換損失，且提升元件效能。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10．．．溝渠型功率電晶體元件
12．．．N型基材
14．．．N型磊晶層
16．．．溝渠
18．．．閘極絕緣層
20．．．閘極
22．．．源極金屬層
24．．．P型基體摻雜區
26．．．N型源極摻雜區
28．．．P型接觸摻雜區
30．．．接觸插塞
32．．．汲極金屬層
100．．．溝渠型功率電晶體元件
102．．．基底
102a．．．主動區
102b．．．終端區
104．．．磊晶層
104a．．．第一穿孔
104b．．．第二穿孔
106．．．井區
108．．．硬遮罩層
108a．．．第一開口
108b．．．第二開口
110．．．摻質來源層
110a．．．第一絕緣層
110b．．．第二絕緣層
114．．．第三絕緣層
114a．．．閘極絕緣層
116．．．第一擴散摻雜區
118．．．第二擴散摻雜區
122．．．導電層
122a．．．閘極導電層
122b．．．終端導電層
124．．．閘極結構
126．．．圖案化光阻層
128．．．源極摻雜區
130．．．介電層
132．．．接觸洞
134．．．接觸摻雜區
136．．．源極金屬層
138．．．汲極金屬層
第1圖係為習知溝渠型功率電晶體元件之剖面示意圖。
第2圖至第9圖為本發明一較佳實施例之溝渠型功率電晶體元件之製作方法示意圖。
100．．．溝渠型功率電晶體元件
102．．．基底
102a．．．主動區
102b．．．終端區
104．．．磊晶層
104a．．．第一穿孔
104b．．．第二穿孔
106．．．井區
110a．．．第一絕緣層
110b．．．第二絕緣層
114a．．．閘極絕緣層
116．．．第一擴散摻雜區
118．．．第二擴散摻雜區
122a．．．閘極導電層
122b．．．終端導電層
124．．．閘極結構
128．．．源極摻雜區
130．．．介電層
132．．．接觸洞
134．．．接觸摻雜區
136．．．源極金屬層
138．．．汲極金屬層

Claims (12)

  1. 一種溝渠型功率電晶體元件，包括：一基底，具有一第一導電類型，且該基底具有一主動區以及一終端區；一磊晶層，設於該基底上，且具有不同於該第一導電類型之一第二導電類型，其中該磊晶層具有至少一第一穿孔以及至少一第二穿孔，分別貫穿該磊晶層，該第一穿孔位於該主動區，且該第二穿孔位於該終端區；一第一擴散摻雜區，設於該第一穿孔一側之該磊晶層中，且與該基底相接觸，其中該第一擴散摻雜區具有該第一導電類型，且該第一擴散摻雜區與該磊晶層相接觸；一源極摻雜區，設於該第一擴散摻雜區之正上方之該磊晶層中，且該源極摻雜區具有該第一導電類型；一閘極結構，設於該第一擴散摻雜區與該源極摻雜區之間的該第一穿孔中；一第二擴散摻雜區，設於該第二穿孔一側之該磊晶層中，且與該基底相接觸，其中該第二擴散摻雜區具有該第一導電類型；以及一終端導電層，設於該第二擴散摻雜區上方之該第二穿孔中。
  2. 如請求項1所述之溝渠型功率電晶體元件，另包括一第一絕緣層，設於該閘極結構下之該第一穿孔中，且電性絕緣該第一擴散摻雜區與該閘極結構。
  3. 如請求項1所述之溝渠型功率電晶體元件，其中該閘極結構包括一閘極導電層以及一閘極絕緣層，且該閘極絕緣層設於該閘極導電層與該磊晶層之間。
  4. 如請求項1所述之溝渠型功率電晶體元件，另包括一井區，設於該第一擴散摻雜區與該第二擴散摻雜區上之該磊晶層中，且該井區具有該第二導電類型。
  5. 如請求項1所述之溝渠型功率電晶體元件，另包括一第二絕緣層，設於該終端導電層下之該第二穿孔中。
  6. 如請求項1所述之溝渠型功率電晶體元件，其中該第一導電類型係為P型，且該第二導電類型係為N型。
  7. 一種溝渠型功率電晶體元件之製作方法，包括：提供一基底，且該基底具有一第一導電類型，其中該基底具有一主動區以及一終端區；於該基底上形成一磊晶層，且該磊晶層具有不同於該第一導電類型之一第二導電類型；於該磊晶層中形成至少一第一穿孔與至少一第二穿孔，貫穿該磊晶層，其中該第一穿孔位於該主動區，且該第二穿孔位於該終端區； 於該第一穿孔與該第二穿孔中分別填入一摻質來源層，其中該摻質來源層包含有具有該第一導電類型之複數個摻質；進行一熱驅入製程，將該等摻質擴散至該磊晶層中，以於該第一穿孔一側之該磊晶層中形成一第一擴散摻雜區以及於該第二穿孔一側之該磊晶層中形成一第二擴散摻雜區，並於該第一穿孔中形成一第一絕緣層以及於該第二穿孔中形成一第二絕緣層，其中該第一擴散摻雜區與該第二擴散摻雜區具有該第一導電類型；於該第一穿孔中形成一閘極結構；以及於該第一穿孔之一側的該磊晶層中形成一源極摻雜區，且該源極摻雜區位於該第一擴散摻雜區之上方，其中該源極摻雜區具有該第一導電類型，且該閘極結構位於該第一擴散摻雜區與該源極摻雜區之間。
  8. 如請求項7所述之溝渠型功率電晶體元件之製作方法，其中形成該閘極結構之步驟包括：於該磊晶層上以及該第一穿孔與該第二穿孔之側壁上形成一第三絕緣層；移除位於該終端區之該第三絕緣層；於該第三絕緣層上以及該終端區之該磊晶層上形成一導電層，且該導電層填入該第一穿孔與該第二穿孔中；以及移除位於該第一穿孔與該第二穿孔外之該第三絕緣層以及該導電層，以於該第一穿孔中形成該閘極結構，且於該第二穿孔中 形成一終端導電層。
  9. 如請求項8所述之溝渠型功率電晶體元件之製作方法，其中該第三絕緣層與該第一擴散摻雜區以及該第二擴散摻雜區係同時形成。
  10. 如請求項7所述之溝渠型功率電晶體元件之製作方法，其中該摻質來源層包含有硼矽玻璃(Boron silicate glass，BSG)。
  11. 如請求項7所述之溝渠型功率電晶體元件之製作方法，其中形成該磊晶層之步驟與形成該第一穿孔與該第二穿孔之步驟之間，該製作方法另包括於該磊晶層中形成一井區，且該井區具有該第二導電類型。
  12. 如請求項7所述之溝渠型功率電晶體元件之製作方法，其中該第一導電類型係為P型，且該第二導電類型係為N型。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760662B (zh) * 2011-04-29 2014-12-31 茂达电子股份有限公司 半导体功率装置的制作方法
TWI441261B (zh) * 2011-05-13 2014-06-11 Anpec Electronics Corp 半導體功率元件的製作方法
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
TW201503366A (zh) * 2013-07-08 2015-01-16 Anpec Electronics Corp 溝渠式功率半導體元件及其製作方法
JP6229501B2 (ja) * 2014-01-08 2017-11-15 富士通株式会社 半導体装置
US9385222B2 (en) * 2014-02-14 2016-07-05 Infineon Technologies Ag Semiconductor device with insert structure at a rear side and method of manufacturing
CN104779276B (zh) * 2014-03-26 2020-01-21 上海提牛机电设备有限公司 一种具有超结结构的igbt及其制备方法
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
US10103140B2 (en) * 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
CN106449744B (zh) * 2016-12-02 2019-09-24 株洲中车时代电气股份有限公司 一种具有栅极内嵌二极管的沟槽栅igbt及其制备方法
US10658409B2 (en) * 2017-11-17 2020-05-19 Taiwan Semiconductor Manufacturing Company Ltd. U. Semiconductor structure and method of manufacturing the same
CN109671626B (zh) * 2018-12-12 2021-09-28 吉林华微电子股份有限公司 具有负反馈电容的igbt器件及制作方法
CN111584365B (zh) * 2020-04-29 2024-01-30 北京时代民芯科技有限公司 一种低米勒电容槽栅vdmos器件制造方法
CN112802841B (zh) * 2021-04-08 2021-07-09 成都蓉矽半导体有限公司 一种具有密勒钳位功能的功率mosfet
TWI836689B (zh) * 2022-11-01 2024-03-21 世界先進積體電路股份有限公司 半導體裝置及其形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050059214A1 (en) * 2003-09-16 2005-03-17 International Business Machines Corporation Method and structure of vertical strained silicon devices
US20080311715A1 (en) * 2007-06-12 2008-12-18 Promos Technologies Inc. Method for forming semiconductor device
US20090020810A1 (en) * 2006-01-05 2009-01-22 Bruce Douglas Marchant Method of Forming Power Device Utilizing Chemical Mechanical Planarization
US20090140327A1 (en) * 2007-12-03 2009-06-04 Takashi Hirao Semiconductor device and manufacturing method of the same
US20110053326A1 (en) * 2009-08-27 2011-03-03 Vishay-Siliconix Super junction trench power mosfet device fabrication

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW587338B (en) * 2003-05-06 2004-05-11 Mosel Vitelic Inc Stop structure of trench type DMOS device and its formation method
CN103094348B (zh) * 2005-06-10 2016-08-10 飞兆半导体公司 场效应晶体管
US8390058B2 (en) * 2009-06-12 2013-03-05 Aplha and Omega Semiconductor Incorporated Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions
US9425306B2 (en) 2009-08-27 2016-08-23 Vishay-Siliconix Super junction trench power MOSFET devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050059214A1 (en) * 2003-09-16 2005-03-17 International Business Machines Corporation Method and structure of vertical strained silicon devices
US20090020810A1 (en) * 2006-01-05 2009-01-22 Bruce Douglas Marchant Method of Forming Power Device Utilizing Chemical Mechanical Planarization
US20080311715A1 (en) * 2007-06-12 2008-12-18 Promos Technologies Inc. Method for forming semiconductor device
US20090140327A1 (en) * 2007-12-03 2009-06-04 Takashi Hirao Semiconductor device and manufacturing method of the same
US20110053326A1 (en) * 2009-08-27 2011-03-03 Vishay-Siliconix Super junction trench power mosfet device fabrication

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