CN103107194A - 沟槽型功率晶体管组件及其制作方法 - Google Patents

沟槽型功率晶体管组件及其制作方法 Download PDF

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CN103107194A
CN103107194A CN2012100162191A CN201210016219A CN103107194A CN 103107194 A CN103107194 A CN 103107194A CN 2012100162191 A CN2012100162191 A CN 2012100162191A CN 201210016219 A CN201210016219 A CN 201210016219A CN 103107194 A CN103107194 A CN 103107194A
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perforation
diffusing
epitaxial loayer
doping district
power transistor
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林永发
徐守一
吴孟韦
陈面国
张家豪
陈家伟
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Anpec Electronics Corp
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Abstract

本发明公开了一种沟槽型功率晶体管组件包括一基底、一外延层、一扩散掺杂区、一源极掺杂区以及一栅极结构。基底、扩散掺杂区与源极掺杂区具有一第一导电类型，且基底具有一有源区以及一终端区。外延层设于基底上，且具有一第二导电类型，其中外延层具有位于有源区的一穿孔。扩散掺杂区设于穿孔一侧的外延层中，且与基底相接触。源极掺杂区设于扩散掺杂区的正上方的外延层中，且栅极结构设于扩散掺杂区与源极掺杂区之间的穿孔中。

Description

沟槽型功率晶体管组件及其制作方法
技术领域
本发明是涉及一种沟槽型功率晶体管组件及其制作方法，特别涉及一种具有超级接口的沟槽型功率晶体管组件及其制作方法。
背景技术
功率晶体管组件常应用于电源管理的部分，例如，切换式电源供应器、计算机中心或周边电源管理IC、背光板电源供应器或马达控制等等用途，其种类包含有绝缘闸双极性晶体管(insulated gate bipolar transistor，IGBT)、金氧半场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)与双极结型晶体管(bipolar junction transistor，BJT)等组件。
请参考图1，图1为现有沟槽型功率晶体管组件的剖面示意图。如图1所示，现有沟槽型功率晶体管组件10包含一N型基材12、一N型外延层14、多个沟槽16、一栅极绝缘层18、多个栅极20以及一源极金属层22。N型外延层14设置于N型基材12上，且各沟槽16位于N型外延层14上。栅极绝缘层18覆盖于各沟槽16的表面，且各栅极20填充于各沟槽16中。并且，栅极绝缘层18将各栅极20与源极金属层22电隔离。N型外延层14上还形成多个P型基体掺杂区24，且各P型基体掺杂区24上还形成一N型源极掺杂区26，而各P型基体掺杂区24中还植入一P型接触掺杂区28。各P型接触掺杂区28通过一接触插塞30电连接至源极金属层22。此外，现有沟槽型功率晶体管组件10的漏极金属层32是设置于N型基材12的下表面。
为了提高沟槽型功率晶体管组件的耐压能力，已发展出在N型基材上形成P型外延层与N型外延层沿水平方向依序交替设置的结构，这样的功率晶体管组件又称为超级接口功率晶体管组件。然而，沟槽型功率晶体管组件的栅极与作为漏极的N型外延层具有较大的重叠面积，且其间的栅极绝缘层具有较小的厚度，造成较高的米勒电容，进而导致较高的切换损失(switchingloss)，影响组件效能。
有鉴于此，降低沟槽型功率晶体管组件的米勒电容实为本领域的技术人员所努力的目标。
发明内容
本发明的主要目的在于提供一种沟槽型功率晶体管组件及其制作方法，以降低米勒电容，并增加耐压。
为达上述的目的，本发明提供一种沟槽型功率晶体管组件，包括一基底、一外延层、一第一扩散掺杂区、一源极掺杂区、一栅极结构、一第二扩散掺杂区以及一终端导电层。基底具有一第一导电类型，且基底具有一有源区以及一终端区。外延层设于基底上，且具有不同于第一导电类型的一第二导电类型，其中外延层具有至少一第一穿孔以及至少一第二穿孔，分别贯穿外延层，第一穿孔位于有源区，且第二穿孔位于终端区。第一扩散掺杂区设于第一穿孔一侧的外延层中，且与基底相接触，其中第一扩散掺杂区具有第一导电类型。源极掺杂区设于第一扩散掺杂区的正上方的外延层中，且源极掺杂区具有第一导电类型。栅极结构设于第一扩散掺杂区与源极掺杂区之间的第一穿孔中。第二扩散掺杂区设于第二穿孔一侧的外延层中，且与基底相接触，其中第二扩散掺杂区具有第一导电类型。终端导电层设于第二扩散掺杂区上方的第二穿孔中。
为达上述的目的，本发明提供一种沟槽型功率晶体管组件的制作方法。首先，提供一基底，且基底具有一第一导电类型，其中基底具有一有源区以及一终端区。然后，于基底上形成一外延层，且外延层具有不同于第一导电类型的一第二导电类型。接着，于外延层中形成至少一第一穿孔与至少一第二穿孔，贯穿外延层，其中第一穿孔位于有源区，且第二穿孔位于终端区。随后，于第一穿孔与第二穿孔中分别填入一掺质来源层。之后，于第一穿孔一侧的外延层中形成一第一扩散掺杂区以及于第二穿孔一侧的外延层中形成一第二扩散掺杂区，且于第一穿孔中形成一栅极结构，其中第一扩散掺杂区与第二扩散掺杂区具有第一导电类型。接下来，于第一穿孔的一侧的外延层中形成一源极掺杂区，且源极掺杂区位于第一扩散掺杂区的上方，其中源极掺杂区具有第一导电类型，且栅极结构位于第一扩散掺杂区与源极掺杂区之间。
综上所述，本发明通过在第一穿孔中填入具有绝缘特性的掺质来源层，且利用热驱入工艺将其中具有导电特性的掺质扩散至外延层中，以形成在垂直方向上与栅极导电层部分重叠的第一扩散掺杂区，且与具有第二导电类型的外延层形成一超级接口。此外，第一穿孔的底部填有具有绝缘特性的掺质来源层，借此可减少沟槽型功率晶体管组件的栅极与漏极之间的寄生电容，进而降低米勒电容以及切换损失，且提升组件效能。
附图说明
图1为现有沟槽型功率晶体管组件的剖面示意图。
图2至图9为本发明一优选实施例的沟槽型功率晶体管组件的制作方法示意图。
其中，附图标记说明如下：
10  沟槽型功率晶体管组件      12    N型基材
14  N型外延层                 16    沟槽
18  栅极绝缘层                20    栅极
22  源极金属层                24    P型基体掺杂区
26  N型源极掺杂区             28    P型接触掺杂区
30  接触插塞                  32    漏极金属层
100     沟槽型功率晶体管组件    102    基底
102a    有源区                  102b   终端区
104     外延层                  104a   第一穿孔
104b    第二穿孔                106    井区
108     硬掩模层                108a   第一开口
108b    第二开口                110    掺质来源层
110a    第一绝缘层              110b   第二绝缘层
114     第三绝缘层              114a   栅极绝缘层
116     第一扩散掺杂区          118    第二扩散掺杂区
122     导电层                  122a   栅极导电层
122b    终端导电层              124    栅极结构
126     图案化光阻层            128    源极掺杂区
130     介电层                  132    接触洞
134     接触掺杂区              136    源极金属层
138     漏极金属层
具体实施方式
请参考图2至图9，图2至图9为本发明一优选实施例的沟槽型功率晶体管组件的制作方法示意图，其中第9图为本发明优选实施例的沟槽型功率晶体管组件的剖面示意图。如图2所示，首先提供具有一第一导电类型的一基底102，且基底102具有用于设置主动组件的一有源区(active region)102a以及用于设置终端结构(termination structure)的一终端区(terminationregion)102b。然后，利用一外延工艺，于基底102上形成一外延层104，且外延层104具有不同于第一导电类型的一第二导电类型。随后，进行一沉积工艺，于外延层104上形成一氧化层(图未示)。接着，进行一第二导电类型的离子注入工艺与一热驱入工艺，以于外延层104中形成一井106，且井区106具有第二导电类型。然后，移除氧化层，并于外延层104上形成一硬掩模层108，例如氮化硅(Si3N4)或二氧化硅(SiO2)，且硬掩模层108具有至少一第一开口108a与至少一第二开口108b。第一开口108a位于有源区102a中，且第二开口108b位于终端区102b中。本实施例以第一导电类型为P型且第二导电类型为N型为例来作描述，但不限于此，第一导电类型与第二导电类型也可互换。P型基底102可为硅基板或硅晶圆，其可作为沟槽型功率晶体管组件的漏极。并且，本实施例的N型井区106是用于调整沟槽型功率晶体管组件的信道区的浓度，以控制沟槽型功率晶体管组件的临界电压(thresholdvoltage)。本发明并不限需形成N型井区106，而也可未形成氧化层与N型井区。此外，第一开口108a与第二开口108b的数量不限为单一个，也可分别为多个。
如图3所示，以硬掩模层108为掩模，对第一开口108a与第二开口108b所曝露出的N型外延层104进行一蚀刻工艺，以于N型外延层104中形成至少一第一穿孔104a与至少一第二穿孔104b，贯穿N型外延层104。第一穿孔104a对应第一开口108a，且位于有源区102a中。第二穿孔104b对应第二开口108b，且位于终端区102b中。并且，第一穿孔104a与第二穿孔104b是通过第一开口108a与第二开口108b所形成，因此其数量也不限为单一个，而可分别为多个。此外，于本实施例中，第一穿孔与第二穿孔延伸至P型基底中。
如图4所示，去除硬掩模层108，然后，于第一穿孔104a与第二穿孔104b中分别填入包含有多个P型掺质的一掺质来源层110。接着利用研磨回蚀刻方法去除N型外延层104上方的掺质来源层110，以及第一穿孔104a与第二穿孔104b中的部分掺质来源层110，使掺质来源层110的上表面高于N型井区106的底部。于本实施例中，形成掺质来源层110的材料包含有硼硅玻璃(Boron silicate glass，BSG)，但不限于此。并且，本发明的掺质来源层110的上表面并不限高于N型井区106的底部，也可约略与N型井区106的底部位于同一平面或稍微低于N型井区106的底部。于本发明的其它实施例中，于填入掺质来源层的步骤之前也可选择性地于第一穿孔与第二穿孔的表面形成一缓冲层，其中缓冲层可利用热氧化工艺来形成，且其组成包含有氧化硅。并且，于填入掺质来源层的步骤之后另可选择性地进行一N型离子注入工艺，以调整邻近第一穿孔两侧的N型井区的掺杂浓度，进而控制沟槽型功率晶体管组件的临界电压。
如图5所示，然后，进行一热氧化工艺，于N型外延层104上方以及第一穿孔104a与第二穿孔104b的侧壁形成一第三绝缘层114。同时，在进行热氧化工艺中，位于掺质来源层110中的P型掺质也会受到热氧化工艺影响而扩散至N型外延层104中，以于各第一穿孔104a两侧的N型外延层104中分别形成一P型第一扩散掺杂区116，且于各第二穿孔104b两侧的N型外延层104中分别形成一P型第二扩散掺杂区118。借此，P型第一扩散掺杂区116与P型第二扩散掺杂区118可与N型外延层104分别形成一PN接面，即超级接口，且PN接面约略垂直N型基底102。并且，第一穿孔104a中的掺质来源层110成为一第一绝缘层110a，且第二穿孔104b中的掺质来源层110成为一第二绝缘层110b。随后，利用一微影蚀刻工艺移除位于终端区102b的第三绝缘层114，且进行一沉积工艺，于终端区102b的N型外延层104与第二绝缘层110b上以及有源区102a的第一绝缘层110a与第三绝缘层114上形成一导电层122，且导电层122填入第一穿孔104a与第二穿孔104b中。于本实施例中，P型第一扩散掺杂区116与P型基底102相接触，而可作为沟槽型功率晶体管组件的漏极。并且，第三绝缘层114是由氧化硅所构成，但本发明并不限利用热氧化工艺来形成第三绝缘层114，且形成第三绝缘层114的步骤与形成P型第一扩散掺杂区与P型第二扩散掺杂区的步骤不限同时进行。于本发明的其它实施例中，第三绝缘层114也可利用沉积工艺搭配光刻工艺来形成，且其材料也不限由氧化硅所构成，而可为其它绝缘材料。并且，形成P型第一扩散掺杂区116以及P型第二扩散掺杂区118的步骤包括一热驱入工艺，将P型掺质扩散至N型外延层104中。另外，导电层122可为例如多晶硅等导电材料所构成。
如图6所示，然后，进行一回蚀刻工艺或一化学机械研磨工艺(chemicalmechanical polishing，CMP)，移除位于第一穿孔104a与第二穿孔104b外的第三绝缘层114以及导电层122，以于第一穿孔104a中形成一栅极绝缘层114a以及一栅极导电层122a，且于第二穿孔104b中形成一终端导电层122b，其中位于第一穿孔104a中的栅极绝缘层114a与栅极导电层122a构成一栅极结构124，且栅极绝缘层114a位于栅极导电层122a与N型井区106之间。于本实施例中，位于第一穿孔104a的栅极导电层122a是通过栅极绝缘层114a以及第一绝缘层110a与P型第一扩散掺杂区116以及N型外延层104电隔离，而作为沟槽型功率晶体管组件的栅极。值得注意的是，栅极导电层122a的下方为第一绝缘层110a，从栅极导电层122a延伸至P型基底102，因此可大幅减少沟槽型功率晶体管组件的栅极与漏极之间的寄生电容，进而降低米勒电容以及切换损失(switching loss)，且提升组件效能。并且，位于终端区102b的终端导电层122b、第二扩散掺杂区118以及N型外延层104构成一终端结构，且终端导电层122b可作为一耦合导体(coupling conductor)，使终端区102b的电压维持平缓下降的趋势，并且使电压截止在特定区域。
如图7所示，接着，于N型外延层104上形成一图案化光阻层126，以暴露出第一穿孔104a两侧的N型外延层104的一部分以及栅极结构124。然后，进行一P型离子注入工艺，以于第一穿孔104a两侧的N型外延层104中分别形成两个P型源极掺杂区128，作为沟槽型功率晶体管组件的源极，其中各P型源极掺杂区128为于各P型第一扩散掺杂区116的正上方的N型外延层104中。并且，栅极结构124位于各P型第一扩散掺杂区116与其相对应的P型源极掺杂区128之间的第一穿孔104a中，且位于各P型第一扩散掺杂区116与其相对应的P型源极掺杂区128之间且邻近栅极绝缘层114a的N型井区106是作为沟槽型功率晶体管组件的信道区，约略垂直P型基底102。由此可知，本实施例的功率晶体管组件为一垂直型功率晶体管组件。
如图8所示，其后，移除图案化光阻层126，并于N型外延层104与栅极结构124上覆盖一介电层130。接着，进行一光刻工艺，于有源区102a的介电层130中形成两个接触洞132，且各接触洞分别暴露出N型外延层104以及各P型源极掺杂区128的一部分。继以进行一N型离子注入工艺，于各接触洞132所暴露出的N型外延层104中形成一N型接触掺杂区134，且各N型接触掺杂区134与各P型源极掺杂区128相接触。接着，进行退火(anneal)处理，以活化N型接触掺杂区134的N型掺质。其中，上述N型接触掺杂区134可提升金属与半导体层接面的导电性，以利电流于接面的传输。
如图9所示，接下来，于介电层130上与各接触洞132中形成一金属层。然后，进行一光刻工艺，移除中终端区102b的金属层，以于行源区102a 中形成一源极金属层136。并且，于P型基底102下形成一漏极金属层138。于本实施例中，形成源极金属层136的步骤可包含进行等离子体溅镀或电子束沉积等工艺，且源极金属层136可包括钛、氮化钛、铝、钨等金属或金属化合物，但不限于此。至此已完成本实施例的沟槽型功率晶体管组件100。于本发明的其它实施例中，于形成源极金属层之前也可先于接触洞中形成接触插塞，或先于接触洞底部的N型外延层上形成一阻障层(图未示)，其组成可包含钛、氮化钛、钽、氮化钽等金属或金属化合物。阻障层乃用以避免接触洞内的金属层电迁移(electro migration)或扩散至N型外延层。值得一提的是，本实施例的沟槽型功率晶体管组件100为P型功率晶体管组件，相较于N型功率晶体管组件而言，拥有优选的顺向偏压安全操作区间以及抗单粒子烧毁的特性。且本实施例具有超级接口的P型沟槽型功率晶体管组件100也可以有效提高耐压以及降低开启电阻(Rdson)。
综上所述，本发明通过于第一穿孔中填入具有绝缘特性的掺质来源层，且利用热驱入工艺将其中具有导电特性的掺质扩散至外延层中，以形成超级接口。并且，具有绝缘特性的掺质来源层可在栅极导电层的下方形成一厚绝缘层，借此可减少沟槽型功率晶体管组件的栅极与漏极之间的寄生电容，进而降低米勒电容以及切换损失，且提升组件效能。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。凡在本发明的精神和原则的内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围的内。

Claims (14)

1.一种沟槽型功率晶体管组件，其特征在于，包括：
一基底，具有一第一导电类型，且所述基底具有一有源区以及一终端区；
一外延层，设于所述基底上，且具有不同于所述第一导电类型的一第二导电类型，其中所述外延层具有至少一第一穿孔以及至少一第二穿孔，分别贯穿所述外延层，所述第一穿孔位于所述有源区，且所述第二穿孔位于所述终端区；
一第一扩散掺杂区，设于所述第一穿孔一侧的所述外延层中，且与所述基底相接触，其中所述第一扩散掺杂区具有所述第一导电类型；
一源极掺杂区，设于所述第一扩散掺杂区的正上方的所述外延层中，且所述源极掺杂区具有所述第一导电类型；
一栅极结构，设于所述第一扩散掺杂区与所述源极掺杂区之间的所述第一穿孔中；
一第二扩散掺杂区，设于所述第二穿孔一侧的所述外延层中，且与所述基底相接触，其中所述第二扩散掺杂区具有所述第一导电类型；以及
一终端导电层，设于所述第二扩散掺杂区上方的所述第二穿孔中。
2.如权利要求1所述的沟槽型功率晶体管组件，其特征在于，还包括一第一绝缘层，设于所述栅极结构下的所述第一穿孔中，且电绝缘所述第一扩散掺杂区与所述栅极结构。
3.如权利要求1所述的沟槽型功率晶体管组件，其特征在于，所述栅极结构包括一栅极导电层以及一栅极绝缘层，且所述栅极绝缘层设于所述栅极导电层与所述外延层之间。
4.如权利要求1所述的沟槽型功率晶体管组件，其特征在于，还包括一井区，
设于所述第一扩散掺杂区与所述第二扩散掺杂区上的所述外延层中，且所述井区具有所述第二导电类型。
5.如权利要求1所述的沟槽型功率晶体管组件，其特征在于，还包括一第二绝缘层，设于所述终端导电层下的所述第二穿孔中。
6.如权利要求1所述的沟槽型功率晶体管组件，其特征在于，所述第一导电类型为P型，且所述第二导电类型为N型。
7.一种沟槽型功率晶体管组件的制作方法，其特征在于，包括：
提供一基底，且所述基底具有一第一导电类型，其中所述基底具有一有源区以及一终端区；
于所述基底上形成一外延层，且所述外延层具有不同于所述第一导电类型的一第二导电类型；
于所述外延层中形成至少一第一穿孔与至少一第二穿孔，贯穿所述外延层，其中所述第一穿孔位于所述有源区，且所述第二穿孔位于所述终端区；
于所述第一穿孔与所述第二穿孔中分别填入一掺质来源层；
于所述第一穿孔一侧的所述外延层中形成一第一扩散掺杂区以及于所述第二穿孔一侧的所述外延层中形成一第二扩散掺杂区，其中所述第一扩散掺杂区与所述第二扩散掺杂区具有所述第一导电类型；
于所述第一穿孔中形成一栅极结构；以及
于所述第一穿孔的一侧的所述外延层中形成一源极掺杂区，且所述源极掺杂区位于所述第一扩散掺杂区的上方，其中所述源极掺杂区具有所述第一导电类型，且所述栅极结构位于所述第一扩散掺杂区与所述源极掺杂区之间。
8.如权利要求7所述的沟槽型功率晶体管组件的制作方法，其特征在于，形成所述第一扩散掺杂区与所述第二扩散掺杂区的步骤包括于所述第一穿孔中形成一第一绝缘层以及于所述第二穿孔中形成一第二绝缘层。
9.如权利要求7所述的沟槽型功率晶体管组件的制作方法，其特征在于，形成所述栅极结构的步骤包括：
于所述外延层上以及所述第一穿孔与所述第二穿孔的侧壁上形成一第三
绝缘层；
移除位于所述终端区的所述第三绝缘层；
于所述第三绝缘层上以及所述终端区的所述外延层上形成一导电层，且所述导电层填入所述第一穿孔与所述第二穿孔中；以及
移除位于所述第一穿孔与所述第二穿孔外的所述第三绝缘层以及所述导
电层，以于所述第一穿孔中形成所述栅极结构，且于所述第二穿孔中形
成一终端导电层。
10.如权利要求9所述的沟槽型功率晶体管组件的制作方法，其特征在于，所述第三绝缘层与所述第一扩散掺杂区以及所述第二扩散掺杂区是同时形成。
11.如权利要求7所述的沟槽型功率晶体管组件的制作方法，其特征在于，所述掺质来源层包含有具有所述第一导电类型的多个掺质，且形成所述第一扩散掺杂区与所述第二扩散掺杂区的步骤包括进行一热驱入工艺，将所述掺质扩散至所述外延层中，以形成所述第一扩散掺杂区与所述第二扩散掺杂区。
12.如权利要求7所述的沟槽型功率晶体管组件的制作方法，其特征在于，所述掺质来源层包含有硼硅玻璃。
13.如权利要求7所述的沟槽型功率晶体管组件的制作方法，其特征在于，形成所述外延层的步骤与形成所述第一穿孔与所述第二穿孔的步骤之间，所述制作方法另包括于所述外延层中形成一井区，且所述井区具有所述第二导电类型。
14.如权利要求7所述的沟槽型功率晶体管组件的制作方法，其特征在于，所述第一导电类型为P型，且所述第二导电类型为N型。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282645A (zh) * 2013-07-08 2015-01-14 茂达电子股份有限公司 沟渠式功率半导体器件及其制作方法
CN104766882A (zh) * 2014-01-08 2015-07-08 富士通株式会社 半导体器件
CN108417625A (zh) * 2014-02-14 2018-08-17 英飞凌科技股份有限公司 具有背侧插入结构的半导体器件及其制造方法
CN109671626A (zh) * 2018-12-12 2019-04-23 吉林华微电子股份有限公司 具有负反馈电容的igbt器件及制作方法
CN112802841A (zh) * 2021-04-08 2021-05-14 成都蓉矽半导体有限公司 一种具有密勒钳位功能的功率mosfet

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102760662B (zh) * 2011-04-29 2014-12-31 茂达电子股份有限公司 半导体功率装置的制作方法
TWI441261B (zh) * 2011-05-13 2014-06-11 Anpec Electronics Corp 半導體功率元件的製作方法
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
CN104779276B (zh) * 2014-03-26 2020-01-21 上海提牛机电设备有限公司 一种具有超结结构的igbt及其制备方法
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
KR102098996B1 (ko) 2014-08-19 2020-04-08 비쉐이-실리코닉스 초접합 금속 산화물 반도체 전계 효과 트랜지스터
US10103140B2 (en) * 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
CN106449744B (zh) * 2016-12-02 2019-09-24 株洲中车时代电气股份有限公司 一种具有栅极内嵌二极管的沟槽栅igbt及其制备方法
US10658409B2 (en) * 2017-11-17 2020-05-19 Taiwan Semiconductor Manufacturing Company Ltd. U. Semiconductor structure and method of manufacturing the same
CN111584365B (zh) * 2020-04-29 2024-01-30 北京时代民芯科技有限公司 一种低米勒电容槽栅vdmos器件制造方法
TWI836689B (zh) * 2022-11-01 2024-03-21 世界先進積體電路股份有限公司 半導體裝置及其形成方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222458A1 (en) * 2003-05-06 2004-11-11 Mosel Vitelic, Inc. Termination structure for trench DMOS device and method of making the same
US20050059214A1 (en) * 2003-09-16 2005-03-17 International Business Machines Corporation Method and structure of vertical strained silicon devices
US20080311715A1 (en) * 2007-06-12 2008-12-18 Promos Technologies Inc. Method for forming semiconductor device
US20090020810A1 (en) * 2006-01-05 2009-01-22 Bruce Douglas Marchant Method of Forming Power Device Utilizing Chemical Mechanical Planarization
US20090140327A1 (en) * 2007-12-03 2009-06-04 Takashi Hirao Semiconductor device and manufacturing method of the same
CN101536163A (zh) * 2005-06-10 2009-09-16 飞兆半导体公司 电荷平衡场效应晶体管
US20110053326A1 (en) * 2009-08-27 2011-03-03 Vishay-Siliconix Super junction trench power mosfet device fabrication

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8390058B2 (en) * 2009-06-12 2013-03-05 Aplha and Omega Semiconductor Incorporated Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions
US9425306B2 (en) 2009-08-27 2016-08-23 Vishay-Siliconix Super junction trench power MOSFET devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222458A1 (en) * 2003-05-06 2004-11-11 Mosel Vitelic, Inc. Termination structure for trench DMOS device and method of making the same
US20050059214A1 (en) * 2003-09-16 2005-03-17 International Business Machines Corporation Method and structure of vertical strained silicon devices
CN101536163A (zh) * 2005-06-10 2009-09-16 飞兆半导体公司 电荷平衡场效应晶体管
US20090020810A1 (en) * 2006-01-05 2009-01-22 Bruce Douglas Marchant Method of Forming Power Device Utilizing Chemical Mechanical Planarization
US20080311715A1 (en) * 2007-06-12 2008-12-18 Promos Technologies Inc. Method for forming semiconductor device
US20090140327A1 (en) * 2007-12-03 2009-06-04 Takashi Hirao Semiconductor device and manufacturing method of the same
US20110053326A1 (en) * 2009-08-27 2011-03-03 Vishay-Siliconix Super junction trench power mosfet device fabrication

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282645A (zh) * 2013-07-08 2015-01-14 茂达电子股份有限公司 沟渠式功率半导体器件及其制作方法
CN104766882A (zh) * 2014-01-08 2015-07-08 富士通株式会社 半导体器件
CN108417625A (zh) * 2014-02-14 2018-08-17 英飞凌科技股份有限公司 具有背侧插入结构的半导体器件及其制造方法
CN109671626A (zh) * 2018-12-12 2019-04-23 吉林华微电子股份有限公司 具有负反馈电容的igbt器件及制作方法
CN112802841A (zh) * 2021-04-08 2021-05-14 成都蓉矽半导体有限公司 一种具有密勒钳位功能的功率mosfet

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