CN108701713A - 在垂直功率半导体装置中的源极－栅极区域架构 - Google Patents

在垂直功率半导体装置中的源极－栅极区域架构 Download PDF

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Publication number
CN108701713A
CN108701713A CN201680067249.1A CN201680067249A CN108701713A CN 108701713 A CN108701713 A CN 108701713A CN 201680067249 A CN201680067249 A CN 201680067249A CN 108701713 A CN108701713 A CN 108701713A
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metal
source region
conduction type
body regions
region
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T·E·哈林顿
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D3 Semiconductor LLC
D3 Semiconductor Co Ltd
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D3 Semiconductor Co Ltd
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明揭示一种具有到源极及本体区域的经改进接触的垂直漂移金属氧化物半导体VDMOS晶体管及一种制造所述VDMOS晶体管的方法。所述源极区域到相反类型的本体区域中的掩蔽离子植入界定本体接触区域的位置，随后使用毯覆式植入而植入所述本体接触区域。所述源极区域及本体接触区域的表面是硅化物包层，且沉积及平坦化上覆绝缘体层。接触开口经形成穿过所述平坦化绝缘体层，在所述接触开口内形成导电插塞以接触所述金属硅化物及因此所述装置的所述源极及本体区域。金属导体整体经形成到所要厚度且接触所述导电插塞以将偏置提供到所述源极及本体区域。

Description

在垂直功率半导体装置中的源极－栅极区域架构
背景技术
本发明涉及半导体功率装置的领域。所揭示的实施例涉及垂直功率晶体管的表面结构。
如所属领域中已知，半导体功率切换装置理想地能够凭借最小切换时间及最小切换功率消耗在接通状态中时以最小电压降传导大电流而在关断状态中时以最小电流传导阻挡大反向电压。还寻求制造良率的改进及制造成本的减小。通过装置架构的创新而非如在低功率半导体装置(例如数字逻辑及存储器装置)的情况中那样通过装置特征大小的缩小而在现代功率晶体管中作出朝向这些理想属性的极大进展。
现在在许多功率应用中广泛使用垂直功率装置。这些装置在通过装置表面与其衬底之间的漂移区域垂直地传导电流的意义上是垂直的。此漂移区域的长度在关断状态中可吸收大耗尽区域且因此建立高反向击穿电压，这实现高电压操作。熟知类型的垂直功率装置包含垂直漂移金属氧化物半导体(VDMOS)场效晶体管、绝缘栅极双极性晶体管(IGBT)与闸控功率二极管，其全部包含足以支持所要高击穿电压的漂移区域。VDMOS装置由于其快速切换速度而变得尤其有吸引力，且因而尤其适合于实施于切换模式的电力供应器中。
图1a以横截面说明常规n沟道垂直漂移MOS晶体管的构造的实例。图1a的VDMOS2具有在n+衬底4处的漏极端子及由n型外延层6提供的漂移区域，所述漂移区域上覆于衬底4且延伸到装置的表面，如所展示。在n型外延层6的表面处的p型本体区域8充当VDMOS本体区域，在所述本体区域内的一或多个n+区域10充当VDMOS 2的源极。栅极电介质11与栅极电极12上覆于p型本体区域8在源极区域10与n型外延层6处的漏极之间的部分。将偏置施加到n+源极区域10及p型本体区域8(通常在p+接触区域处，未展示)，使得VDMOS 2的本体节点被偏置在源极电势下。其它导体(未展示)接触栅极电极12及衬底4以分别提供栅极偏置及漏极偏置。如在任何n沟道MOS晶体管中，通过在栅极电极12处的超过晶体管阈值电压的电压结合足够漏极到源极偏置而将垂直功率VDMOS 2偏置到接通状态中。在典型功率应用中的漏极到源极偏置通常非常高(例如，高达从几百到高于一千伏特)。如图1a中展示，接通状态的源极-漏极电流Ids自源极区域10沿着p型本体区域8的本体区域中的反转层横向传导且垂直通过外延层6到晶体管漏极处的衬底4中。VDMOS 2的接通电阻包含p型本体区域8中的沟道电阻Rch，但由于n型外延层6的厚度及相对轻掺杂剂浓度，所述接通电阻通常由n型外延层6的电阻Repi主导。虽然外延层6的掺杂浓度的增加将减小电阻Repi且因此减小VDMOS 2的总体接通电阻，但VDMOS 2的击穿电压与其n型外延层6的厚度(即，VDMOS“漂移”长度)直接相关且与更轻度掺杂的外延层6的掺杂剂浓度逆相关。由于典型VDMOS装置在关断状态中必须耐受高漏极到源极电压(例如，大约几百伏特)，因此需要接通电阻与关断状态的击穿电压之间的折衷。
也如所属领域中已知，“超级结”VDMOS晶体管解决此折衷。图1b也针对n沟道装置的情况说明此常规超级结VDMOS 2’的实例。就表面结构(p型本体区域8、n+源极区域10、栅极电极12等)来说，超级结VDMOS 2’与图1a的非超级结VDMOS 2类似地构造。然而，与图1a的非超级结VDMOS 2相比，超级结VDMOS 2’的外延区域填充有形成到外延层6’中的p型掺杂“柱”9。例如可在外延层6’硅的形成期间在其中在层6’的部分的外延之后执行p型柱植入的多步骤外延工艺中通过离子植入构造这些p型柱9，使得每一柱9形成为若干垂直对准片段。p型本体区域8及n+源极区域10通常与栅极电极12自对准，其中p型本体区域8通常在n+源极植入之前植入，且接收专用驱入退火以便在栅极电极12下方比其对应n+源极区域10更远地延伸，其中p型本体区域8通常稍微延伸到n型外延区域的表面区域中。p型本体区域8的掺杂剂浓度是针对所要MOSFET特性(例如阈值电压及穿通)优化，而p型柱9的掺杂剂浓度是针对关断状态中的电荷平衡优化且通常将比本体区域8更轻度地掺杂。在接通状态中，VDMOS 2’以相同于上文针对非超级结VDMOS 2描述的方式传导源极-漏极电流Ids，在此情况中电流经传导通过由n型外延层6’在p型柱9之间的部分呈现的n型漂移区域。然而，在关断状态中，p型柱9及外延层6’的n型漂移区域在典型高漏极到源极电压下本质上将完全耗尽，在此情况下，延伸深入到结构中的柱9的额外p型材料导致对应量的电荷也从n型外延层6’耗尽以便获得电荷平衡。根据此超级结构造在关断状态中源自柱9的此额外电荷消除使外延层6’能够具有更高掺杂剂浓度及因此更低接通状态电阻Repi而并未不利地影响关断状态中的击穿电压。
图1a及1b的常规VDMOS装置中的栅极电极是平面结构，其安置于半导体的表面附近且上覆于栅极电介质层。相比之下，一些常规超级结及非超级结VDMOS装置经构造具有沟槽栅极电极。如所属领域中已知，沟槽栅极装置的栅极电极以通过栅极电介质与周围半导体绝缘的方式安置于蚀刻到装置的表面中的沟槽内。沟槽栅极VDMOS装置的沟道区域经垂直定向，此垂直定向通过所述沟道区域的源极-漏极电流。
图2a针对平面栅极电极情况以横截面说明到图1b的常规VDMOS装置2’的源极及本体区域的偏置连接的物理结构。非超级结装置(例如图1a的VDMOS装置2)通常具有类似偏置连接结构。在图2的实例中，通过实现为上覆在栅极电极12上方的绝缘体层13的单个金属层级金属导体的源极金属14进行到n+源极区域10及本体区域8的偏置连接。如所属领域中已知，侧壁绝缘体可沿着栅极电极12的边缘存在。接触开口经蚀刻穿过绝缘体层13，在所述接触开口处源极金属14接触源极区域10及本体区域8。
如在垂直功率集成电路的技术中为常规的，VDMOS装置2’的多个晶体管结构并联连接，其中衬底4充当用于全部晶体管结构的漏极，且其中源极金属14针对全部结构并联连接本体区域8及源极区域10。在俯视(即，平面)图中，源极金属14可因此呈现为在VDMOS装置2’的作用区域上方的单个连续片。由VDMOS装置2’传导的大源极/漏极电流需要源极金属14的厚度Tmet显著厚于低电压模拟及逻辑集成电路中的金属导体。举例来说，大约几微米(例如，2到10μm)的源极金属厚度在现代垂直功率装置中是常见的。
在图2a的常规源极-栅极架构中，以相对于栅极电极12自行对准的方式植入源极区域10，如上文中提及。因此，为了在此常规构造中在源极金属14与p型本体区域8之间进行接触，穿过绝缘体13的接触开口经过蚀刻到下伏外延硅中，其中所述蚀刻延伸到完全穿过源极区域10且到下伏本体区域8中的深度Dct，如图2a中展示。由于到单晶硅中的此蚀刻，经沉积源极金属14将与源极区域10及还与本体区域8物理接触。
此常规源极-栅极架构呈现对垂直功率装置的性能及可扩缩性的限制。一个此限制是存在于栅极电极12与源极金属14之间的寄生栅极到源极电容。如所属领域中已知，MOS晶体管中的栅极到源极电容可限制装置的切换速度，且因而应最小化到可行程度。参考图2b中展示的VDMOS 2’的细节视图，寄生栅极到源极电容Cgs存在于栅极电极12的顶表面及侧边缘两者处。
VDMOS 2’的栅极到源极电容Cgs与栅极电极12的顶表面与上覆源极金属14之间的绝缘体层13的厚度Tinsul成反比地变化。因此，为了最大化切换性能，可期望尽可能增加此厚度Tinsul。然而，再次参考图2a的视图，绝缘体层13的厚度Tinsul的增加不利地影响经沉积源极金属14针对给定接触宽度Wct与源极区域10及本体区域8可靠地接触的能力。此困难由VDMOS 2’的大源极-漏极电流所需的经增加源极金属厚度Tmet加剧。更具体来说，如所属领域中已知，针对绝缘体层13的给定厚度Tinsul，源极金属14到具有小于经沉积薄膜的厚度Tmet的两倍的宽度(即，接触宽度Wct)的接触开口中的沉积可导致经沉积金属的自我阴蔽(self-shadowing)或甚至“面包条现象(bread-loafing)”，其中随着源极金属14下降到接触开口中，源极金属14的经沉积厚度变薄。因此，减小在接触内的源极金属14的阶梯覆盖，从而使VDMOS装置2’在其操作寿命期间易受源极金属14的电迁移影响，借此增加装置失效且降低装置可靠性。因此，在这些常规栅极-源极架构中，可通过针对给定接触宽度Wct增加绝缘体厚度Tinsul而减少栅极到源极电容的程度是受限制的。
相反，金属厚度Tmet与绝缘体厚度Tinsul之间的此相互作用还限制将功率装置按比例调整为较小几何形状的能力。在集成电路的表面处源极与栅极结构的间距不仅取决于栅极宽度而且取决于接触宽度Wct。但由于接触宽度Wct的缩小使减小绝缘体厚度Tinsul及源极金属厚度Tmet中的一者或两者成为必要，因此垂直功率装置结构的按比例调整必然以增加的寄生栅极到源极电容Cgs或减小的电流能力为代价。
发明内容
所揭示的实施例提供一种垂直功率装置结构及其制造方法，其中可优化栅极到源极电容而不显著影响金属导体可靠性。
所揭示的实施例提供此结构及方法，其提供经改进的可制造性。
所揭示的实施例提供此结构及方法，其可按比例调整到较小几何形状而不显著牺牲电流能力及装置性能。
所揭示的实施例提供其中可独立优化栅极到源极电容及装置间距的此结构及方法。
所属领域的一般技术人员在参考以下说明书连同其图式之后将明白所揭示的实施例的其它目的及优点。
根据某些实施例，一种垂直漂移金属氧化物半导体(VDMOS)晶体管构造于半导体装置的表面处。掺杂到第一导电类型的源极区域安置于所述半导体装置的表面处第二导电类型的本体区域内。栅极电极上覆于所述源极区域之间的相应本体区域及邻近本体区域之间的漂移区域的部分。所述第二导电类型的本体接触区域在每一本体区域内安置在源极区域之间。金属硅化物包层安置于所述本体接触区域及所述邻近源极区域的表面处。平坦化绝缘层上覆于所述栅极电极，其中在所述绝缘层中的接触开口中形成金属接触插塞以接触所述金属硅化物包层。金属导体上覆于所述平坦化绝缘层且接触所述金属接触插塞。
根据某些实施例，一种制造VDMOS晶体管的方法包含在第一导电类型的半导体的表面附近形成彼此隔开的栅极电极及在所述表面处形成通过下伏于所述栅极电极的表面的位置彼此隔开的第二导电类型的掺杂本体区域。接着植入第一导电类型的掺杂剂以将第一导电类型的源极区域界定到所述本体区域中，其中所述植入经掩蔽以界定所述源极区域中的间隙。接着植入第二导电类型的掺杂剂以在间隙位置处形成本体接触区域。接着执行所述源极区域及所述本体接触区域的表面的金属硅化物包层。整体安置且平坦化绝缘体层。形成穿过所述绝缘体层到所述包覆源极区域及本体接触区域的接触开口，且在所述接触开口中形成导体插塞。接着形成金属导体以接触所述导体插塞。
附图说明
图1a及1b分别是常规非超级结VDMOS晶体管及超级结VDMOS晶体管的横截面视图。
图2a及2b是常规超级结VDMOS晶体管中的源极及本体区域接触的横截面视图。
图3a是根据实施例构造的超级结VDMOS晶体管的部分的横截面视图。
图3b是根据所述实施例的图3a的VDMOS晶体管的部分的平面视图。
图4是说明根据实施例制造图3a及3b的超级结VDMOS晶体管的方法的流程图。
图5a到5h是图3a及3b的超级结VDMOS晶体管的部分在根据图4的实施例的制造的每一个阶段的横截面图。
图6a是根据实施例构造的绝缘栅极双极性晶体管(IGBT)的部分的横截面视图。
图6b是根据实施例构造的闸控功率二极管的部分的横截面视图。
具体实施方式
本说明书中描述的一或多个实施例实施为超级结类型的垂直漂移金属氧化物半导体(VDMOS)晶体管结构，因为预期此实施方案在所述背景内容中尤其有利。然而，还预期本发明的概念可有利地应用到其它应用，例如其它垂直功率装置(例如非超级结VDMOS装置、垂直绝缘栅极双极性晶体管(IGBT)及垂直闸控功率二极管)。因此，应理解，以下描述仅通过实例提供且不希望限于如所主张的本发明的真实范围。
图3a及3b分别以横截面视图及平面视图说明根据本发明的优选实施例的超级结VDMOS 20的构造中的各种特征的布置。此实施例将针对n沟道VDMOS晶体管的实例描述且因而将描述为形成于n型硅衬底中，其中n型外延硅生长于所述衬底上方，当然预期所属领域的技术人员在参考本说明书之后将容易能够在无过度实验的情况下使这些实施例适于替代类型的功率装置，例如沟槽栅极VDMOS晶体管、非超级结VDMOS装置、p沟道VDMOS晶体管、IGBT与闸控垂直功率二极管。
图3a说明如部分制造在集成电路中的VDMOS 20的部分。如上文提及，VDMOS 20制造于充当晶体管的漏极节点的相对重度掺杂的n+衬底24处，在所述n+衬底24上形成较轻度掺杂的n型外延层26的漂移区域。n型外延层26延伸到单晶硅的表面。在此超级结构造中，p型掺杂“柱”29形成到外延层26中且如图3a中展示那样彼此隔开，其中由外延层26提供的n型半导体的区域与柱29交错。如所属领域中已知，可在外延层26的形成期间例如在其中在层26的部分的外延之后执行p型柱植入的多步骤外延工艺中通过离子植入构造这些p型柱29，使得每一柱29形成为若干垂直对准片段。
在此实施例中，如对于平面栅极VDMOS装置典型，p型本体区域28在外延层26的表面处安置于柱29的顶部上。p型本体区域28充当n沟道VDMOS晶体管20的本体区域。n+源极区域30安置于对应本体区域28内且如本文中将描述那样将通过导体接收源极偏置。栅极电介质31及栅极电极32上覆于p型本体区域28在源极区域30与n型外延层26的表面部分之间的相应部分。在此实例中，(例如)氧化硅或氮化硅的侧壁绝缘体细丝36沿着栅极电极32的侧壁安置。
根据此实施例，p+本体接触区域35在本体区域28内安置在(在每一例子中)存在于所述相同本体区域28中的源极区域30之间的位置处。如从图3a显而易见，在本体区域28内的本体接触区域35的任一侧上的源极区域30结合所述本体区域28的任一侧上的不同栅极电极32操作。p+本体接触区域35经充分重度掺杂以提供到本体区域28的良好欧姆接触。在此实施例中，源极区域30及本体接触区域35的表面包覆有金属硅化物34s(例如硅化钛或硅化钴)且因而电连接在一起使得源极区域30及本体区域28处在相同电势。如下文将结合VDMOS 20的制造描述那样，栅极电极32可包覆有可与金属硅化物34s同时形成的金属硅化物34g。侧壁绝缘体细丝36协助维持栅极包层34g与源极包层34s的分离且还协助控制装置的阈值电压，如在下文中将论述。
在此实施例中，如图3a中展示，绝缘体层33安置于包含栅极电极32及源极区域30的VDMOS 20的作用结构上方。此绝缘体层33(其可为氧化硅、氮化硅、有机电介质或其它电介质材料或其组合)具有大体上平面且因此未遵循下伏结构的形貌的上表面。通过绝缘体层33中的接触开口进行与源极区域30及本体区域28的接触，钨或另一合适金属或金属化合物的导电插塞38安置到所述接触开口中。在其中钨是导电插塞38的材料的此实例中，沿着绝缘体33中的这些接触开口的侧壁且在硅化物膜34s处开口的底部处安置势垒层37。如所属领域中已知，势垒层37可由具有适当厚度及组合物的一或多个金属或导电金属化合物构成以防止导电插塞38的材料迁移到下伏硅中。
还在此实施例中，源极金属40安置于绝缘体层33的表面处且与导电插塞28的顶部接触。源极金属40具有功率装置(例如VDMOS 20)中的金属导体的常规构造，通常包含铝、铜或适合于支持预期由装置传导的电流的金属的组合。
图3b以平面视图说明图3a的集成电路的部分，其中在源极区域30、本体接触区域35与栅极电极32的包覆之前且因此在绝缘体层33及源极金属40的沉积之前的时间点制造VDMOS 20。如从图3b显而易见，在图3a中的横截面中展示的各种结构布置为跨其中形成VDMOS 20的集成电路裸片的内部延伸的平行“条带”。在图3b的视图中显而易见的结构包含栅极电极32、源极区域30及本体接触区域35(虽然存在于此点处，但为了清楚起见，在图3b中未展示侧壁绝缘体细丝36)。图3b还以阴影说明导电插塞38的位置及形状，导电插塞38安置于穿过上覆绝缘体层33的接触开口中，如图3a中展示。当完成此实例实施方案的制造时，预期源极金属40将作为单个导体(即，呈单个金属片的形状)上覆于图3b中展示的结构的整个部分，其中所述单个导体进行与全部导电插塞38的顶部的接触。因此，源极区域30(及本体区域28)将并联连接，正如衬底24(图3a)提供用于VDMOS 20的单个漏极节点。在此实施例中，由于绝缘体层33及导电插塞38的上表面大体上平面，因此沉积于所述结构上方的源极金属40还将具有大体上平坦上表面，随后可在所述上表面上沉积钝化电介质层(未展示)。
图3a及3b中展示的结构以及本体区域38及柱29(图3b中不可见)布置于裸片的中央“核心”区域内，所述核心区域是VDMOS 20的表面的功能性作用区域。预期图3a中展示的结构将完全跨此核心区域延伸，其中提供与图3b中展示的若干结构并联的更多(例如，多达大约几百个)类似结构。如所属领域中已知且例如在2015年10月2日申请的共同待决且共同转让的序列号为14/873,831的美国申请案(所述申请案以引用的方式并入本文中)中描述那样，此实施例中的VDMOS晶体管20通常还将包含包围此“核心”区域的终止区域。如在上文并入的序列号为14/873,831的美国申请案中描述那样，所述终止区域包含终止结构(例如场板、护环、非作用柱及类似者)以基本上通过将电场从垂直(在核心处)平滑扭曲到水平(在裸片的外边缘处)同时防止峰值电场达到临界电场及引起装置击穿而横向维持关断状态的漏极到源极电压。
替代呈平行条带的形式的图3a及3b的结构，p型柱29及VDMOS 20的其它对应元件可布置为“单元”阵列。在2015年8月25日颁布的与本申请案共同转让且以引用的方式并入本文中的第9,117,899号美国专利针对沟槽栅极VDMOS晶体管的情况描述此单元类型几何形状的实例。预期所属领域的技术人员在参考本说明书之后可容易在无过度实验的情况下使图3a及3b中展示且上文中描述的实例适于此“单元”类型的结构。
根据此实施例的垂直功率装置的结构提供性能、按比例调整、可制造性及可靠性方面的重要优点。特定来说，此结构使绝缘体层33的厚度Tinsul的参数与源极金属40的厚度Tmet的参数分离，使得可选择这些厚度中的每一者而不受另一者显著限制。更具体来说，在此实施例中，栅极电极32上方的绝缘体层33的厚度Tinsul可经选择以最小化栅极到源极电容Cgs而不受源极金属40进行与源极区域30及本体区域28的可靠接触的能力限制。相反，在此实施例中，源极金属40的厚度Tmet可经选择以支持在接通状态中时由VDMOS 20传导的高电流而不受到源极/本体接触开口中的阶梯覆盖或所述接触开口的宽度或绝缘体层33的厚度Tinsul限制，从而避免源极金属40的厚度Tmet与绝缘体层33的厚度Tinsul之间的折衷。另外，可相对于常规结构显著改进VDMOS 20的切换性能及电流容量。源极区域30、本体接触区域35与栅极电极32的硅化物包层还通过减小所述结构及接触的电阻而改进装置性能。
为了类似原因，本发明的此实施例提供更可制造且可靠结构，其中极大消除在其到硅的接触处的源极金属的薄化。另外，此实施例通过消除如在例如上文关于图2a及2b描述的常规结构中必需的蚀刻穿过源极区域以便进行与本体区域的接触的需要而提供显著更可制造结构。
此实施例还实现VDMOS 20的装置大小的进一步按比例调整。如在常规结构(其中由于针对所要源极金属厚度接触开口太窄而发生金属沉积的阴蔽)中，在此构造中，穿过绝缘体33的接触开口的宽度不受源极金属40的厚度Tmet限制。根据此实施例，接触间距不受源极金属40的厚度Tmet影响，且因而可独立选择两个参数。此外，通过消除源极金属40的阶梯覆盖问题而增强VDMOS 20的潜在可靠性。且由于源极金属40的顶表面如图3a中展示那样是大体上平面，因此归因于在所述表面处缺乏形貌阶梯而还增强上覆钝化层的完整性。
预期所属领域的技术人员在参考本说明书之后将明白根据此实施例的VDMOS晶体管的结构的这些及其它优点。
现在结合图5a到5h参考图4，现在将描述根据本发明的实施例的制造VDMOS 20的方法。此方法开始于过程50，其中根据如所属领域中已知的常规外延，将n型漂移外延层26外延形成到n+衬底24上。针对其中VDMOS 20是超级结装置的此实施例中，过程50将在若干反复中形成外延层26，每一反复包含外延形成选定厚度的n型硅，接着在待形成柱29的位置处掩蔽植入p型掺杂剂(例如，硼)且(任选地)退火经植入掺杂剂。柱植入彼此对准以便形成从外延层26的表面延伸到所要深度的p型掺杂剂的多个柱；这些柱29通过层26的n型外延硅的区域彼此分离，如上文中描述。
接着，根据此实施例，在过程52中形成VDMOS 20的栅极结构。以常规方式，可通过外延层26(及本体区域28)的表面的热氧化而形成栅极电介质31；替代地，栅极电介质31可为二氧化硅、氮化硅、另一合适栅极电介质材料或这些材料的组合的沉积层。接着以常规方式通过以下步骤形成栅极电极32：沉积所要栅极材料(例如多晶硅)层，接着进行光刻图案化及蚀刻以在所要位置处且按所要尺寸界定栅极电极32。
在过程53中，通过离子植入接着驱入退火而在外延层26的表面处形成本体区域28。如在过程53中植入的掺杂剂(例如，硼)与栅极电极32的边缘自对准，且将由于驱入退火而在栅极电极32下方横向扩散。VDMOS 20的最终沟道长度将取决于在过程53中植入的p型本体区域掺杂剂横向扩散超过随后n型源极植入扩散的距离。过程53的植入还与柱29对准使得本体区域28与对应柱29形成连续p型区域。本体区域28的掺杂剂浓度可不同于柱29的掺杂剂浓度且通常将针对所要晶体管特性优化。另外，如由上文描述的图3a所示，本体区域28的横向边界可不同于对应下伏柱29的横向边界。
在过程52、53中形成栅极电极32及本体区域28之后，在过程54中光刻界定p+本体接触区域35在栅极电极32之间的本体区域的表面处的位置。可以常规方式执行过程54，例如包含施配光致抗蚀剂、光刻暴露光致抗蚀剂以界定所要图案及使暴露光致抗蚀剂显影以选择性移除不充当最终掩模的部分。图5a说明在过程54之后的制造中的点的VDMOS 20的结构，具体来说其中光致抗蚀剂掩模特征55保留于栅极电极32之间的空间内的位置处。在过程56中，在所述掩模特征55的任一侧上的本体区域28的表面的暴露位置30’接收n型掺杂剂(例如，砷、磷)的离子植入，如图5a中展示；通过后续驱入退火而将经植入掺杂剂扩散到所要轮廓。在所述退火及其它后续热过程之后，可以所属领域中熟知的常规方式选择过程56的源极植入的剂量及能量以导致所要掺杂剂轮廓；举例来说，此源极植入可为以通常在5E15到1E16个原子/cm2的范围中的剂量及在30到200KeV的范围中的能量的磷或砷植入。在此实施例中，作为在额外植入之后的单个热过程执行此源极植入的退火，如在下文中将描述；替代地，可在紧接在源极植入过程56之后的此点执行退火。
在源极植入过程56之后，在过程58中移除光致抗蚀剂掩模特征55。如在针对垂直功率装置的技术中典型那样，接着在过程60中可以足以提供本体区域28及下伏源极区域30内的最终重度掺杂p型区域的剂量及能量执行p型植入。此“p基”区域减少VDMOS20中的寄生SCR触发且引起结构的闭锁的趋势，如所属领域中已知。在此实例中，在后续植入之后的单个退火中执行此p基植入的退火；替代地，可在此植入过程60之后执行退火以驱入p基植入及还可能源极植入。
接着执行过程62以沿着栅极电极32的侧边缘形成侧壁绝缘体细丝36。可以常规方式(例如)通过以下步骤执行过程62：沉积所要电介质材料(例如，氧化硅、氮化硅)，接着进行各向异性蚀刻以清除栅极电极32及本体区域28的表面同时使细丝36留在适当位置中。
接着，在过程64中执行离子植入p型掺杂剂(例如，硼)以形成p+本体接触区域35，如在图5b中展示。由于在过程60中移除掩模特征55，因此过程64的植入将重度掺杂每一本体区域28中的源极区域30之间的间隙。此植入将具有经选择足以使本体接触区域35提供良好欧姆接触的剂量及能量，例如具有通常在1E15个原子/cm2到5E15个原子/cm2的范围中的剂量及通常在20到200KeV的范围中的能量的硼或BF2植入。然而，此p+本体接触区域植入的剂量应小于随后n+源极植入的剂量以允许n+源极植入在最终n+源极区域30中占主导地位。在此离子植入之后，执行高温退火以退火在过程64中植入的掺杂剂及可能还在过程56及60中植入的掺杂剂以导致源极区域30及本体接触区域35(及通过p基植入60形成的本体区域28的重度掺杂部分)的所要掺杂剂轮廓。
根据此实施例在过程53的本体区域植入之后且在过程64的本体接触植入之前，在过程62中沿着栅极电极32形成侧壁绝缘体细丝36实现对最终VDMOS 20的阈值电压的增强控制。更具体来说，侧壁绝缘体细丝36的宽度Wsw使在过程62中植入n型植入位置30’内的p+本体接触区域掺杂剂与下伏于栅极电极32的p型本体区域28的横向扩散边缘的边缘隔开。此间隔促进对下伏于栅极电极32的沟道区域中具体来说在本体区域28在源极区域35与n型外延层26之间的部分内的掺杂剂浓度的控制。
根据此实施例，在过程66中执行对源极区域30、本体接触区域35及可能栅极电极32的暴露表面的硅化。熟知自对准直接反应硅化(“硅化金属沉积”)技术可用于包覆这些结构。因而，硅化过程66包含与半导体材料及还绝缘体材料两者接触的金属的整体沉积。适合于硅化的金属的实例包含钛、钴及类似者，如图5c中展示。在金属沉积之后，硅化过程66继续在合适氛围(例如，氮)中高温退火装置，在所述退火期间，与硅接触的沉积金属的部分将反应以形成金属硅化物，且与绝缘体材料(二氧化硅或氮化硅，例如侧壁绝缘体细丝36)接触的经沉积金属的部分将不反应或将形成不同金属化合物(例如，氮化钛)。接着通过毯覆式蚀刻完成硅化过程66以从绝缘体结构移除金属化合物同时使金属硅化物特征留在适当位置中，例如在图5d中通过在源极区域30及本体接触区域35处的金属硅化物34s及在栅极电极32处的金属硅化物34g所展示。侧壁绝缘体细丝36有助于使栅极电极32的表面处的金属硅化物34g与源极区域30处的金属硅化物34s分离以避免这些结构的短接。如上文中论述，金属硅化物34s提供源极区域30与本体接触区域35之间的电接触使得源极区域30及本体区域28在VDMOS 20的操作中将处在相同电势。图5d还说明由上文中描述的植入后退火(以及硅化过程66自身的高温退火)所致的源极区域30及本体接触区域35的轮廓。
在硅化过程66之后，接着在过程68中整体沉积绝缘体层33。在此实施例中，绝缘体层33由以常规方式通过化学气相沉积而沉积的二氧化硅形成；替代地，可在过程68中沉积如适合于绝缘体层33的功能的其它材料。在沉积时，绝缘体层33通常与下伏拓扑共形，尤其如图5d中展示那样由栅极电极32呈现的拓扑。根据此实施例，在过程68中，(例如)通过化学机械抛光(CMP)或通过等离子体回蚀工艺而将绝缘体层33的上表面平坦化到如图5e中展示的其最终厚度Tinsul。
在过程70中，以常规方式光刻图案化及蚀刻接触开口使之穿过绝缘体层33以暴露源极区域30及本体接触区域35处的硅化物膜34s的位置。在其中厚度Tinsul显著大于接触开口的宽度的所述实施方案中，优选可通过常规等离子体蚀刻执行过程70的接触蚀刻。图5f说明在接触蚀刻过程70之后VDMOS 20的结构。
在过程72中，在表面上方沉积用于形成导电插塞38的导电材料。例如钨、钛及这些及类似金属的合金的金属通常用作导电插塞的金属且在此实施例中可充当导电插塞38。针对例如钨的金属，在过程72中首先沉积一或多个势垒层37以抑制来自导电插塞38的金属原子扩散到有源半导体中是有用的；合适势垒层的实例包含例如钛的金属及例如氮化钛的金属氮化物。如图5g中展示，在引起材料粘着到绝缘体33中的接触开口的侧壁以及沉积到硅化物膜34s的暴露部分及平坦化绝缘体层33的顶表面上的条件下整体沉积势垒层37。在势垒层37的沉积之后，导电插塞38的金属经整体沉积，从而填充穿过绝缘体层33的接触开口的剩余部分且延伸于绝缘体层33的顶表面处的势垒层37上方，如图5g中展示。预期可针对选定金属通过如所属领域中已知的常规方法实行金属沉积过程72。在过程74中，在除了接触开口处以外的全部区域中移除插塞金属38。过程74可通过插塞金属38及势垒层37的化学机械抛光(CMP)执行而停止在绝缘体层33的顶表面处以导致如图5h中展示的结构。替代地，过程74可通过CMP或通过回蚀(在任一情况中停止在下伏势垒层37上)而仅移除插塞金属38。
在过程74之后，接着在过程76中沉积、光刻图案化及蚀刻源极金属40。除了如上文描述那样充当VDMOS 20的“核心”区域内的源极金属40之外，此相同金属层还可充当接触栅极电极32的导体(即，充当“栅极金属”)且还充当集成电路的终止区域及周边中的等电势环中的金属。由于在过程68中平坦化绝缘体层33的上表面，源极金属40将在其顶表面处展现最小垂直形貌变化。针对现代垂直功率装置(例如VDMOS 20)，预期源极金属40的厚度Tmet将是至少约2μm厚且将通常厚达若干μm(例如，大约4μm到5μm，其中使用上限通常约10μm)。接着在过程80中在源极金属40的顶表面上方沉积钝化层，其中执行光刻图案化及蚀刻以敞开焊垫及类似者。
在过程80中，预期在此实施方案中的源极金属40的平坦化通过提供用于钝化金属(例如具有所要性质的氮化硅)的沉积的平面表面而进一步改进VDMOS 20的可靠性。因此，经沉积钝化材料在拓扑步骤较少经受破裂且因此可具有经改进的完整性。
根据此实施例的制造VDMOS 20的方法提供结合可制造性的特定优点。可制造性的一个此优点是消除如上文关于2a描述的蚀刻穿过n+源极区域以进行与所述源极区域及本体区域两者的同时接触。到下伏硅中的此定时蚀刻在实际上高度可变化，从而导致到本体区域的偏置接触及所得电性能的广泛变化。相比之下，根据此实施例无需蚀刻到下伏半导体中，但代替性地可使用到在源极区域及本体接触区域的表面处的金属硅化物膜的端点蚀刻可靠地进行与装置本体区域的源极接触。因此极大减少在以此方式构造的VDMOS装置的群体当中的所得接触的变化。
另外，通过此实施例的制造方法提供上文论述的性能、可靠性及可扩缩性的优点而不极大复杂化制造过程。仅需要单个额外光刻操作，具体来说在掩蔽源极植入中界定本体接触区域的位置；此额外光刻步骤还在某种程度上是非关键的，只要关注对准或大小即可，这是因为在源极区域之间精确放置本体接触区域并非尤其关键。因此，以消除绝缘体层厚度、源极金属厚度及接触间距之间的相依性的方式提供到源极及本体区域的极佳接触。可以实现装置的按比例调整的方式减少装置的栅极到源极电容而不显著影响源极金属的电流传导能力。
预期本发明的实施例可类似地应用到包含绝缘栅极双极性晶体管(IGBT)及垂直闸控功率二极管的其它垂直功率装置。图6a通过类似于针对VDMOS 20的图3a的横截面视图的横截面视图说明根据实施例构造的IGBT 80的实例；类似结构特征由相同参考数字展示且将不进一步进行描述。在此实例中，IGBT 80如下那样不同于VDMOS 20：a)p柱未下伏于p型本体区域28；及b)由于垂直IGBT 80具有在半导体的底部处的p+集电极端子82，因此IGBT80通常将构造于块状(即，非外延)n型半导体衬底26(而非如在VDMOS 20的情况中的n+衬底24)上。在此构造中，在制造顶表面组件之后且在机械研磨或化学蚀刻以薄化衬底之后将p+集电极82植入到n型衬底26的底侧中；接着将退火结构以电活化p+集电极植入。金属导体40使p+区域35(如在VDMOS 20中，其提供到p本体区域28的电接触)及n+区域30(现为IGBT 80的发射极)与经供能以形成沟道的栅极电极32连接。IGBT 80的表面结构在其它方面与上文中描述的VDMOS 20的表面结构基本上相同。如在VDMOS 20的情况中，根据此实施例的IGBT80获得上文中论述的性能、可靠性及可扩缩性的优点。
图6b说明根据另一实施例的垂直闸控二极管90的构造；再次，与图3a的VDMOS 20类似的结构由相同参考数字指代。此实施例的二极管90与VDMOS 20类似地构造，其中n型外延层26如先前那样形成于n+衬底24上，且取决于二极管90是否需要采用电荷平衡装置构造而在本体区域28下方可或可不包含p型柱29。n+衬底24提供用于二极管90的阴极连接，而金属导体40充当阳极与栅极连接。根据此实施例的垂直二极管90通过在栅极硅化物34g(与栅极电极32)与源极硅化物34s之间提供局部连接84而不同于上文描述的VDMOS 20。根据此实施例，通过掩蔽侧壁绝缘体细丝36的表面的部分使其免受用于在金属硅化物34s、34g的直接反应硅化(即，作为图4的过程66的部分)之后移除未反应金属的蚀刻而获得局部连接84。在经掩蔽位置处的剩余金属可未经反应(例如，钛或钴金属)或是硅化物金属的导电化合物(例如氮化钛，针对在硅化反应中在氮氛围中反应的钛金属的情况)或所述导电物种的组合。此局部连接84通过最小化(一方面)p+区域35与n+区域30之间，另一方面p+区域35与栅极电极32之间的电阻而实现优越装置瞬时导通(transient on-turn)性能。另外，此构造获得上文结合本发明的其它实施例论述的可靠性及可扩缩性的优点。
虽然在本说明书中已描述一或多个实施例，当然预期这些实施例的修改及替代，所属领域的一般技术人员在参考本说明书及其图式之后将明白能够获得本发明的一或多个优点及益处的此类修改及替代例。预期此类修改及替代例在如本文中随后主张的本发明的范围内。

Claims (24)

1.一种集成电路，其包括：
第一导电类型的半导体衬底；
所述第一导电类型的外延层，其上覆于所述衬底，所述外延层具有比所述衬底更轻的掺杂剂浓度；
多个栅极电极，其安置于所述外延层的表面附近且彼此隔开；
第二导电类型的多个本体区域，其在栅极电极之间的位置处安置到所述外延层的所述表面中；
在每一本体区域内，所述第一导电的第一源极区域及第二源极区域安置于所述本体区域的表面处；
在每一经掺杂本体区域内，所述第二导电类型的本体接触区域安置于所述第一源极区域与所述第二源极区域之间的所述表面处；
金属硅化物包层，其在每一本体区域的所述第一源极区域及所述第二源极区域的至少一部分及所述本体接触区域的表面处；
绝缘层，其上覆于所述栅极电极且具有平坦化表面；
多个导电插塞，其通过所述绝缘层中的接触开口接触所述金属硅化物包层；及
金属导体，其安置于所述绝缘层上方且与所述多个导电插塞接触。
2.根据权利要求1所述的集成电路，其进一步包括：
所述第二导电类型的多个柱，其各自形成到所述外延层中下伏于所述本体区域中的一者的位置处且与所述本体区域中的一者接触。
3.根据权利要求1所述的集成电路，其中所述第一源极区域及所述第二源极区域各自具有相对于所述栅极电极中的一者自对准的边缘。
4.根据权利要求1所述的集成电路，其进一步包括：
栅极电介质层，其安置于每一栅极电极与所述外延层的所述表面之间；
侧壁绝缘体元件，其沿着每一栅极电极的每一侧安置。
5.根据权利要求1所述的集成电路，其中所述导电插塞包括：
一或多个势垒金属层，其沿着所述接触开口的侧及底部安置；及
金属插塞，其经安置邻近所述势垒金属。
6.根据权利要求5所述的集成电路，其中所述势垒金属包括钛且所述金属插塞包括钨。
7.根据权利要求1所述的集成电路，其中所述金属硅化物包层还安置于每一栅极电极的表面处。
8.根据权利要求7所述的集成电路，其进一步包括：
侧壁绝缘体元件，其沿着每一栅极电极的每一侧安置。
9.根据权利要求8所述的集成电路，其进一步包括：
局部互连件，其安置于所述侧壁绝缘体元件的表面上且在安置于所述栅极电极处的所述金属硅化物包层与安置于所述第一源极区域及所述第二源极区域的至少一部分及所述本体接触区域的所述表面处的所述金属硅化物包层之间形成电接触。
10.一种制造垂直功率装置的方法，其包括：
在第一导电类型的半导体的表面附近形成彼此隔开的多个栅极电极；
在所述表面处形成第二导电类型的多个本体区域，所述多个本体区域通过下伏于所述栅极电极的表面的位置彼此隔开；
将所述第一导电类型的第一源极区域及第二源极区域形成到每一本体区域中；
将所述第一源极区域与所述第二源极区域之间的位置处的所述第二导电类型的本体接触区域形成到每一本体区域中；
沉积与所述源极区域及本体接触区域接触的金属；
接着加热所述金属以在所述源极区域及本体接触区域的表面处形成金属硅化物；
整体沉积绝缘体材料；
平坦化所述绝缘体材料；
形成穿过所述平坦化绝缘体材料的接触开口；
在所述接触开口中形成多个导电插塞使其与所述源极区域及本体接触区域的所述表面处的所述金属硅化物电接触；及
接着形成与所述多个导电插塞电接触的金属导体。
11.根据权利要求10所述的方法，其中形成所述第一源极区域及所述第二源极区域的所述步骤包括：
掩蔽每一本体区域在邻近栅极电极之间的位置处的部分以暴露在所述经掩蔽部分的相对侧上的表面位置；及
将所述第一导电类型的掺杂剂植入到所述本体区域的所述暴露表面位置中。
12.根据权利要求11所述的方法，其中形成所述本体接触区域的所述步骤包括：
在植入所述第一导电类型的掺杂剂的所述步骤之后，将所述第二导电类型的掺杂剂植入到所述本体区域中；及
接着退火所述第二导电类型的所述经植入掺杂剂。
13.根据权利要求12所述的方法，其进一步包括：
在植入所述第一导电类型的掺杂剂的所述步骤之后且在形成所述本体接触区域的所述步骤之前，以经选择以在所述本体区域内下伏于所述源极区域的位置处提供所述第二导电类型的较高掺杂剂浓度的剂量及能量将所述第二导电类型的掺杂剂植入到所述本体区域中。
14.根据权利要求12所述的方法，其中形成所述本体区域的所述步骤包括：
以相对于所述栅极电极的自对准方式将所述第二导电类型的掺杂剂植入到所述表面中；及
接着加热所述半导体；
且所述方法进一步包括：
在植入所述第一导电类型的掺杂剂的所述步骤之后且在形成所述本体接触区域的所述步骤之前，在所述栅极电极的侧边缘上形成侧壁绝缘体细丝。
15.根据权利要求10所述的方法，其中形成多个导电插塞的所述步骤包括：
整体沉积势垒金属；
整体沉积导电金属；及
从所述绝缘层的表面移除所述导电金属，使所述导电金属仅留在所述接触开口中。
16.根据权利要求15所述的方法，其中所述势垒金属包括钛；
且其中所述导电金属包括钨。
17.根据权利要求10所述的方法，其中形成金属导体的所述步骤包括：
将金属整体沉积到至少约2μm且小于约10μm的所要厚度；及
移除所述经沉积金属的选定部分以界定各自与所述导电插塞中的一或多者电接触的一或多个金属导体。
18.根据权利要求17所述的方法，其进一步包括：
在形成金属导体的所述步骤之后，沉积绝缘钝化层。
19.根据权利要求10所述的方法，其进一步包括：
在形成所述本体区域的所述步骤之前，在所述第一导电类型的衬底上方形成所述第一导电类型的外延层；
其中在所述外延层的表面处形成所述本体区域。
20.根据权利要求19所述的方法，其中形成所述外延层的所述步骤包括：
外延形成所述外延层的部分；
接着使用所述第二导电类型的掺杂剂植入所述外延层的多个选定部分；及
重复多次所述外延形成及植入步骤以在所述第一导电类型的所述外延层内形成所述第二导电类型的经掺杂材料的多个柱。
21.根据权利要求10所述的方法，其进一步包括：
在形成所述本体区域的所述步骤之前，在所述第一导电类型的衬底上方形成所述第一导电类型的外延层。
22.根据权利要求10所述的方法，其中沉积与所述源极区域及所述本体接触区域接触的金属的所述步骤还沉积与所述栅极电极接触的所述金属；
其中所述加热步骤还在所述栅极电极的所述表面处形成金属硅化物；
且所述方法进一步包括：
在沉积与所述源极区域及本体接触区域接触的金属的所述步骤之前，沿着所述栅极电极的侧形成侧壁绝缘体元件；及
在所述加热步骤之后，移除所述非硅化金属。
23.根据权利要求22所述的方法，其进一步包括：
在所述加热步骤之后且在移除所述非硅化金属的所述步骤之前，掩蔽上覆于侧壁绝缘体元件的所述非硅化金属的位置。
24.一种集成电路，其包括：
第一导电类型的半导体衬底；
多个栅极电极，其安置于所述衬底的顶表面附近且彼此隔开；
第二导电类型的多个本体区域，其在栅极电极之间的位置处安置到所述衬底的所述表面中；
在每一本体区域内，所述第一导电的第一源极区域及第二源极区域安置于所述本体区域的表面处；
在每一经掺杂本体区域内，所述第二导电类型的本体接触区域安置于所述第一源极区域与所述第二源极区域之间的所述表面处；
金属硅化物包层，其在每一本体区域的所述第一源极区域及所述第二源极区域的至少一部分及所述本体接触区域的所述表面处；
绝缘层，其上覆于所述栅极电极且具有平坦化表面；
多个导电插塞，其通过所述绝缘层中的接触开口接触所述金属硅化物包层；
金属导体，其安置于所述绝缘层上方且与所述多个导电插塞接触；及
第二导电类型的集极区域，其在所述衬底的底表面处且与所述衬底的所述第一导电类型材料形成冶金结。
CN201680067249.1A 2015-10-01 2016-01-28 在垂直功率半导体装置中的源极－栅极区域架构 Pending CN108701713A (zh)

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