JP2007027193A - 半導体装置およびその製造方法、ならびに非絶縁型dc/dcコンバータ - Google Patents
半導体装置およびその製造方法、ならびに非絶縁型dc/dcコンバータ Download PDFInfo
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Abstract
【解決手段】 SJ構造を有する低耐圧の縦型トレンチMOSFETにおいて、電流経路であるN型エピタキシャル層2と、半導体表面からN型エピタキシャル層2内に延在するトレンチ構造とを有し、トレンチ構造の下側のN型エピタキシャル層2内に、フローティングなP型領域3が形成されている。このP型領域3は、トレンチ構造の下部に、P型の不純物イオンをイオン打ち込みすることで形成される。このように、微細なトレンチゲートの下に、イオン打ち込みによりP型領域3を形成することで、イオン打ち込みのエネルギーを低エネルギー化でき、微細なSJ構造を作製できる。
【選択図】 図1
Description
図1は、本発明の実施の形態1のSJ構造を有する低耐圧の縦型トレンチMOSFETの構造の一例を示す。
図6は、本発明の実施の形態2のSJ構造を有する低耐圧の縦型トレンチMOSFETの構造の一例を示す。
図8は、本発明の実施の形態3のSJ構造を有する低耐圧の縦型トレンチMOSFETの構造の一例を示す。
図10は、本発明の実施の形態4の、SJ構造を有する低耐圧の縦型トレンチMOSFETを用いた非絶縁型DC/DCコンバータの構成の一例を示す。
Claims (22)
- 電流経路である第1導電型の第1半導体領域と、半導体表面から前記第1半導体領域内に延在するトレンチ構造とを有する半導体装置であって、
前記トレンチ構造の下側の前記第1半導体領域内に、フローティングな第2導電型の第2半導体領域が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記半導体装置はパワーMOSFETであることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体領域の横方向の長さは、前記トレンチ構造の横方向の長さ+0.5μm以下であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1半導体領域の縦方向の長さは、2μm以上4μm以下であることを特徴とする半導体装置。 - 電流経路である第1導電型の第1半導体領域と、半導体表面から前記第1半導体領域内に延在するトレンチ構造とを有する半導体装置の製造方法であって、
前記トレンチ構造の下側の前記第1半導体領域内に、フローティングな第2導電型の第2半導体領域が形成され、
前記第2半導体領域は、前記トレンチ構造の下部に、第2導電型の不純物イオンをイオン打ち込みすることで形成されることを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記イオン打ち込みは、前記第2導電型の不純物イオンを、打ち込みエネルギーを変えて、複数回イオン打ち込みすることを特徴とする半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記トレンチ構造の下部の前記第1半導体領域には、前記第2導電型の不純物イオンに加えて、第1導電型の不純物イオンもイオン打ち込みすることを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記第1導電型の不純物イオンの打ち込み深さは、前記第2導電型の不純物イオンの打ち込み深さよりも浅いことを特徴とする半導体装置の製造方法。 - 電流経路である第1導電型の第1半導体領域と、前記第1半導体領域の上部の第2導電型の第3半導体領域と、半導体表面から前記第3半導体領域を貫き、前記第1半導体領域内に延在する第1トレンチ構造と、前記第3半導体領域内の第1導電型の第4半導体領域と、半導体表面から前記第3半導体領域内に延在する第2トレンチ構造と、前記第2トレンチ構造の直下で、前記第3半導体領域内の第2導電型の第5半導体領域とを有する半導体装置であって、
前記第2トレンチ構造の下側の前記第1半導体領域内に、第2導電型の第6半導体領域が形成されていることを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記半導体装置はパワーMOSFETであることを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記第1トレンチ構造の下部の第1半導体領域内に、第1導電型の第7半導体領域が形成されることを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記第6半導体領域の横方向の幅は、前記第2トレンチ構造の横方向の幅+0.5μm以内であることを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記第1半導体領域の縦方向の長さは、2μm以上4μm以下であることを特徴とする半導体装置。 - 電流経路である第1導電型の第1半導体領域と、前記第1半導体領域の上部の第2導電型の第3半導体領域と、半導体表面から前記第3半導体領域を貫き、前記第1半導体領域内に延在する第1トレンチ構造と、前記第3半導体領域内の第1導電型の第4半導体領域と、半導体表面から前記第3半導体領域内に延在する第2トレンチ構造と、前記第2トレンチ構造の直下で、前記第3半導体領域内の第2導電型の第5半導体領域とを有する半導体装置の製造方法であって、
前記第2トレンチ構造の下側の前記第1半導体領域内に、第2導電型の第6半導体領域が形成され、
前記第6半導体領域は、前記第2トレンチ構造の下部に、第2導電型の不純物イオンをイオン打ち込みすることで形成されることを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記イオン打ち込みは、前記第2導電型の不純物イオンを、打ち込みエネルギーを変えて、複数回イオン打ち込みすることを特徴とする半導体装置の製造方法。 - 第1導電型の半導体基板と、前記半導体基板上にエピタキシャル成長した第2導電型の第8半導体領域と、前記第8半導体領域の上部の第2導電型の第9半導体領域と、半導体表面から前記第9半導体領域を貫き、前記第8半導体領域内に延在するゲート構造とを有する半導体装置であって、
前記ゲート構造の下部に、前記ゲート構造から前記半導体基板に延在する第1導電型の第10半導体領域が形成されていることを特徴とする半導体装置。 - 請求項16記載の半導体装置において、
前記半導体装置はパワーMOSFETであることを特徴とする半導体装置。 - 請求項16記載の半導体装置において、
前記第10半導体領域の横方向の幅は、前記ゲート構造の横方向の幅+0.5μm以内であることを特徴とする半導体装置。 - 請求項16記載の半導体装置において、
前記第8半導体領域の縦方向の長さは、2μm以上4μm以下であることを特徴とする半導体装置。 - 第1導電型の半導体基板と、前記半導体基板上にエピタキシャル成長した第2導電型の第8半導体領域と、前記第8半導体領域の上部の第2導電型の第9半導体領域と、半導体表面から前記第9半導体領域を貫き、前記第8半導体領域内に延在するゲート構造とを有する半導体装置の製造方法であって、
前記ゲート構造の下部に、前記ゲート構造から前記半導体基板に延在する第1導電型の第10半導体領域が形成され、
前記第10半導体領域は、前記ゲート構造の下部に、第1導電型の不純物イオンをイオン打ち込みすることで形成されることを特徴とする半導体装置の製造方法。 - 請求項20記載の半導体装置の製造方法において、
前記イオン打ち込みは、前記第1導電型の不純物イオンを、打ち込みエネルギーを変えて、複数回イオン打ち込みすることを特徴とする半導体装置の製造方法。 - 請求項2、10または17記載のパワーMOSFETを、ローサイドスイッチとして使用することを特徴とする非絶縁型DC/DCコンバータ。
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