TW201725728A - 在垂直功率半導體裝置中之源極－閘極區域架構 - Google Patents

在垂直功率半導體裝置中之源極－閘極區域架構 Download PDF

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TW201725728A
TW201725728A TW105129978A TW105129978A TW201725728A TW 201725728 A TW201725728 A TW 201725728A TW 105129978 A TW105129978 A TW 105129978A TW 105129978 A TW105129978 A TW 105129978A TW 201725728 A TW201725728 A TW 201725728A
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contact
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TW105129978A
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湯瑪士Ｅ 三世 海靈頓
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Ｄ３半導體責任有限公司
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  • Crystallography & Structural Chemistry (AREA)
  • Composite Materials (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明揭示一種具有至源極及本體區域之經改良接觸之垂直漂移金屬氧化物半導體(VDMOS)電晶體及一種製造該VDMOS電晶體之方法。該等源極區域至相反類型之本體區域中之一遮罩離子植入界定本體接觸區域之位置，隨後使用一毯覆式植入而植入該等本體接觸區域。該等源極區域及本體接觸區域之表面係矽化物包層，且沈積及平坦化一上覆絕緣體層。接觸開口經形成穿過該平坦化絕緣體層，在該等接觸開口內形成導電插塞以接觸該金屬矽化物及因此該裝置之該等源極及本體區域。一金屬導體整體經形成至所要厚度且接觸該等導電插塞以將偏壓提供至該等源極及本體區域。

Description

在垂直功率半導體裝置中之源極－閘極區域架構
本發明係關於半導體功率裝置之領域。所揭示之實施例係關於垂直功率電晶體之表面結構。
如此項技術中已知，半導體功率切換裝置理想地能夠憑藉最小切換時間及最小切換功率消耗在接通狀態中時以最小電壓降傳導大電流而在關斷狀態中時以最小電流傳導阻擋大反向電壓。亦尋求製造良率之改良及製造成本之減小。透過裝置架構之創新而非如在低功率半導體裝置(諸如數位邏輯及記憶體裝置)之情況中般透過裝置特徵大小之縮小而在現代功率電晶體中極大地作出朝向此等理想屬性之進展。 現在在許多功率應用中廣泛使用垂直功率裝置。此等裝置在透過裝置表面與其基板之間之一漂移區域垂直地傳導電流之意義上係垂直。此漂移區域之長度在關斷狀態中可吸收一大空乏區域且因此建立一高反向崩潰電壓，此實現高電壓操作。熟知類型之垂直功率裝置包含垂直漂移金屬氧化物半導體(VDMOS)場效電晶體、絕緣閘極雙極性電晶體(IGBT)及閘控功率二極體，其等全部包含足以支援所要高崩潰電壓之一漂移區域。VDMOS裝置由於其等之快速切換速度而變得尤其有吸引力，且因而尤其適合於實施於切換模式之電源供應器中。 圖1a以橫截面繪示一習知n通道垂直漂移MOS電晶體之構造之一實例。圖1a之VDMOS 2具有在n+基板4處之一汲極終端及由n型磊晶層6提供之一漂移區域，該漂移區域上覆於基板4且延伸至裝置之表面，如所展示。在n型磊晶層6之表面處之p型本體區域8充當VDMOS本體區域，在該本體區域內之一或多個n+區域10充當VDMOS 2之源極。閘極介電質11及閘極電極12上覆於源極區域10與n型磊晶層6處之汲極之間之p型本體區域8之部分。將偏壓施加至n+源極區域10及p型本體區域8 (通常在p+接觸區域處，未展示)，使得以源極電位加偏壓於VDMOS 2之本體節點。其他導體(未展示)接觸閘極電極12及基板4以分別提供閘極偏壓及汲極偏壓。如在任何n通道MOS電晶體中，藉由在閘極電極12處之超過電晶體臨限值電壓之一電壓結合一足夠汲極至源極偏壓而將垂直功率VDMOS 2加偏壓至接通狀態中。在典型功率應用中之汲極至源極偏壓通常非常高(例如，高達自幾百至高於一千伏特)。如圖1a中展示，接通狀態之源極-汲極電流Ids自源極區域10沿著p型本體區域8之本體區域中之一反轉層橫向傳導且垂直通過磊晶層6至電晶體汲極處之基板4中。VDMOS 2之接通電阻包含p型本體區域8中之通道電阻Rch ，但由於n型磊晶層6之厚度及相對輕摻雜劑濃度，該接通電阻通常由n型磊晶層6之電阻Repi 主導。雖然磊晶層6之摻雜濃度之一增加將減小電阻Repi 且因此減小VDMOS 2之總體接通電阻，但VDMOS 2之崩潰電壓與其之n型磊晶層6之厚度(即，VDMOS 「漂移」長度)直接相關且與更輕度摻雜之磊晶層6之摻雜劑濃度逆相關。由於典型VDMOS裝置在關斷狀態中必須耐受高汲極至源極電壓(例如，大約幾百伏特)，因此需要接通電阻與關斷狀態之崩潰電壓之間之一折衷。 亦如此項技術中已知，「超級接面」 VDMOS電晶體解決此折衷。圖1b亦針對一n通道裝置之情況繪示此一習知超級接面VDMOS 2’之一實例。就關注表面結構(p型本體區域8、n+源極區域10、閘極電極12等)而言，超級接面VDMOS 2'與圖1a之非超級接面VDMOS 2類似地建構。然而，與圖1a之非超級接面VDMOS 2相比，超級接面VDMOS 2’之磊晶區域塡充有形成至磊晶層6’中之p型摻雜「柱」9。例如可在磊晶層6’矽之形成期間在其中在層6’之一部分之磊晶之後執行一p型柱植入之一多步驟磊晶程序中藉由離子植入建構此等p型柱9，使得各柱9形成為若干垂直對準片段。p型本體區域8及n+源極區域10通常與閘極電極12自對準，其中p型本體區域8通常在n+源極植入之前植入，且接收一專用驅入退火以便在閘極電極12下方延伸遠於其對應n+源極區域10，其中p型本體區域8通常稍微延伸至n型磊晶區域之表面區域中。p型本體區域8之摻雜劑濃度係針對所要MOSFET特性(諸如臨限值電壓及穿通)最佳化，而p型柱9之摻雜劑濃度係針對關斷狀態中之電荷平衡最佳化且通常將比本體區域8更輕度地摻雜。在接通狀態中，VDMOS 2’以相同於上文針對非超級接面VDMOS 2描述之方式傳導源極-汲極電流Ids，在此情況中電流經傳導通過由p型柱9之間之n型磊晶層6’之部分呈現之n型漂移區域。然而，在關斷狀態中，p型柱9及磊晶層6’之n型漂移區域在典型高汲極至源極電壓下基本上將完全空乏，在此情況下，延伸深至結構中之柱9之額外p型材料導致對應量之電荷亦自n型磊晶層6’空乏以便獲得電荷平衡。根據此超級接面構造在關斷狀態中源自柱9之此額外電荷消除使磊晶層6’能夠具有一更高摻雜劑濃度及因此一更低接通狀態電阻Repi 而並未不利地影響關斷狀態中之崩潰電壓。 圖1a及圖1b之習知VDMOS裝置中之閘極電極係平面結構，其等安置於半導體之表面附近且上覆於閘極介電層。相比之下，一些習知超級接面及非超級接面VDMOS裝置經建構具有溝槽閘極電極。如此項技術中已知，一溝槽閘極裝置之閘極電極以藉由一閘極介電質與周圍半導體絕緣之一方式安置於蝕刻至裝置之表面中之一溝槽內。溝槽閘極VDMOS裝置之通道區域經垂直定向，此垂直定向通過該通道區域之源極-汲極電流。 圖2a針對平面閘極電極情況以橫截面繪示至圖1b之習知VDMOS裝置2’之源極及本體區域之偏壓連接之實體結構。非超級接面裝置(諸如圖1a之VDMOS裝置2)通常具有一類似偏壓連接結構。在圖2之實例中，藉由實現為上覆在閘極電極12上方之絕緣體層13之一單一金屬層級金屬導體之源極金屬14製成至n+源極區域10及本體區域8之偏壓連接。如此項技術中已知，一側壁絕緣體可沿著閘極電極12之邊緣存在。接觸開口經蝕刻穿過絕緣體層13，在該等接觸開口處源極金屬14接觸源極區域10及本體區域8。 如在垂直功率積體電路之技術中習知，VDMOS裝置2’之多個電晶體結構並聯連接，其中基板4充當用於全部電晶體結構之汲極，且其中連接本體區域8及源極區域10之源極金屬14用於全部並聯結構。在一俯視(即，平面)圖中，源極金屬14可因此呈現為在VDMOS裝置2’之作用區域上方之一單一連續片。由VDMOS裝置2’傳導之大源極/汲極電流需要源極金屬14之厚度Tmet 顯著厚於低電壓類比及邏輯積體電路中之金屬導體。舉例而言，大約幾微米(例如，2至10 μm)之一源極金屬厚度在現代垂直功率裝置中係常見的。 在圖2a之習知源極-閘極架構中，以相對於閘極電極12自行對準之一方式植入源極區域10，如上文中提及。因此，為了在此習知構造中製成源極金屬14與p型本體區域8之間之接觸，穿過絕緣體13之接觸開口經過蝕刻至下伏磊晶矽中，其中該蝕刻延伸至完全穿過源極區域10且至下伏本體區域8中之一深度Dct ，如圖2a中展示。由於至單晶矽中之此蝕刻，經沈積源極金屬14將與源極區域10及亦本體區域8實體接觸。 此習知源極-閘極架構呈現對垂直功率裝置之效能及可擴縮性之限制。一個此限制係存在於閘極電極12與源極金屬14之間之寄生閘極至源極電容。如此項技術中已知，一MOS電晶體中之閘極至源極電容可限制裝置之切換速度，且因而應最小化至可行程度。參考圖2b中展示之VDMOS 2’之細節視圖，寄生閘極至源極電容Cgs存在於閘極電極12之頂表面及側邊緣兩者處。 VDMOS 2'之閘極至源極電容Cgs隨著閘極電極12之頂表面與上覆源極金屬14之間之絕緣體層13之厚度Tinsul 成反比地變動。因此，為了最大化切換效能，可期望儘可能增加此厚度Tinsul 。然而，再次參考圖2a之視圖，絕緣體層13之厚度Tinsul 之增加不利地影響針對一給定接觸寬度Wct 經沈積源極金屬14與源極區域10及本體區域8可靠地接觸之能力。此困難由VDMOS 2’之大源極-汲極電流所需之經增加源極金屬厚度Tmet 加劇。更具體言之，如此項技術中已知，針對絕緣體層13之一給定厚度Tinsul ，源極金屬14至具有小於經沈積薄膜之厚度Tmet 之兩倍之一寬度(即，接觸寬度Wct )之一接觸開口中之沈積可導致經沈積金屬之自我陰蔽(self-shadowing)或甚至「麵包條現象(bread-loafing)」，其中隨著源極金屬14下降至接觸開口中，源極金屬14之經沈積厚度變薄。因此，減小在接觸內之源極金屬14之階梯覆蓋，從而使VDMOS裝置2’在其操作壽命期間易受源極金屬14之電遷移影響，藉此增加裝置失效且減少裝置可靠性。因此，在此等習知閘極-源極架構中，可藉由針對一給定接觸寬度Wct 增加絕緣體厚度Tinsul 而減少閘極至源極電容之程度係限制的。 相反的，金屬厚度Tmet 與絕緣體厚度Tinsul 之間之此相互作用亦限制將功率裝置按比例調整為較小幾何形狀之能力。在積體電路之表面處源極及閘極結構之間距不僅取決於閘極寬度而且取決於接觸寬度Wct 。但由於接觸寬度Wct 之縮小使減小絕緣體厚度Tinsul 及源極金屬厚度Tmet 之一者或兩者成為必要，因此垂直功率裝置結構之按比例調整必然以增加之寄生閘極至源極電容Cgs或減小之電流能力為代價。
所揭示之實施例提供一種垂直功率裝置結構及其製造方法，其中可最佳化閘極至源極電容而不顯著影響金屬導體可靠性之垂直功率裝置結構。 所揭示之實施例提供此一結構及方法，其提供經改良之可製造性。 所揭示之實施例提供此一結構及方法，其可按比例調整至較小幾何形狀而不顯著犧牲電流能力及裝置效能。 所揭示之實施例提供其中可獨立最佳化閘極至源極電容及裝置間距之此一結構及方法。 一般技術者在參考以下說明書連同其圖式之後將明白所揭示之實施例之其他目的及優點。 根據某些實施例，一種垂直漂移金屬氧化物半導體(VDMOS)電晶體建構於一半導體裝置之一表面處。摻雜至一第一導電類型之源極區域安置於該半導體裝置之表面處一第二導電類型之本體區域內。閘極電極上覆於該等源極區域之間之各自本體區域及鄰近本體區域之間之一漂移區域之部分。該第二導電類型之一本體接觸區域安置於各本體區域內源極區域之間。金屬矽化物包層安置於該本體接觸區域及該等鄰近源極區域之表面處。一平坦化絕緣層上覆於該等閘極電極，其中在該絕緣層中之接觸開口中形成一金屬接觸插塞以接觸該金屬矽化物包層。一金屬導體上覆於該平坦化絕緣層且接觸該等金屬接觸插塞。 根據某些實施例，一種製造一VDMOS電晶體之方法包含在一第一導電類型之一半導體之一表面附近形成彼此隔開之閘極電極及在該表面處形成藉由下伏於該等閘極電極之表面之位置彼此隔開之一第二導電類型之摻雜本體區域。接著植入第一導電類型之摻雜劑以將第一導電類型之源極區域界定至該等本體區域中，其中該植入經遮罩以界定該等源極區域中之間隙。接著植入第二導電類型之摻雜劑以在間隙位置處形成本體接觸區域。接著執行該等源極區域及該等本體接觸區域之表面之金屬矽化物包層。整體安置且平坦化一絕緣體層。形成穿過該絕緣體層至該等包覆源極區域及本體接觸區域之接觸開口，且在該等接觸開口中形成導體插塞。接著形成金屬導體以接觸該等導體插塞。
相關申請案之交叉參考 本申請案根據35 U.S.C. §119(e)規定主張2015年10月1日申請之臨時申請案第62/236,009號之優先權，該案以引用的方式併入本文中。 關於聯邦sponsored政府資助的研究或開發之陳述 不適用。 本說明書中描述之一或多項實施例實施為超級接面類型之一垂直漂移金屬氧化物半導體(VDMOS)電晶體結構，因為預期此實施方案在該背景內容中尤其有利。然而，亦預期本發明之概念可有利地應用至其他應用，例如其他垂直功率裝置(諸如非超級接面VDMOS裝置、垂直絕緣閘極雙極性電晶體(IGBT)及垂直閘控功率二極體)。因此，應理解，以下描述僅藉由實例提供且不旨在限於如所主張之本發明之真實範疇。 圖3a及圖3b分別以橫截面視圖及平面視圖繪示根據本發明之一較佳實施例之超級接面VDMOS 20之構造中之各種特徵之配置。此實施例將針對一n通道VDMOS電晶體之實例描述且因而將描述為形成於一n型矽基板中，其中n型磊晶矽生長於該基板上方，當然預期熟習此項技術者在參考本說明書之後將容易能夠在無不當實驗之情況下使此等實施例適於替代類型之功率裝置，諸如溝槽閘極VDMOS電晶體、非超級接面VDMOS裝置、p通道VDMOS電晶體、IGBT及閘控垂直功率二極體。 圖3a繪示如部分製造在一積體電路中之VDMOS 20之一部分。如上文提及，VDMOS 20製造於充當電晶體之汲極節點之相對重度摻雜之n+基板24處，在該n+基板24上形成較輕度摻雜之n型磊晶層26之一漂移區域。n型磊晶層26延伸至單晶矽之表面。在此超級接面構造中，p型摻雜「柱」29形成至磊晶層26中且如圖3a中展示般彼此隔開，其中由磊晶層26提供之n型半導體之區域與柱29交錯。如此項技術中已知，可在磊晶層26之形成期間例如在其中在層26之一部分之磊晶之後執行一p型柱植入之一多步驟磊晶程序中藉由離子植入建構此等p型柱29，使得各柱29形成為若干垂直對準片段。 在此實施例中，如對於平面閘極VDMOS裝置典型，p型本體區域28安置於磊晶層26之表面處柱29之頂部上。p型本體區域28充當n通道VDMOS電晶體20之本體區域。n+源極區域30安置於對應本體區域28內且如本文中將描述般將透過導體接收源極偏壓。閘極介電質31及閘極電極32上覆於源極區域30之間之p型本體區域28之各自部分及n型磊晶層26之表面部分。在此實例中，(例如)氧化矽或氮化矽之側壁絕緣體細絲36沿著閘極電極32之側壁安置。 根據此實施例，p+本體接觸區域35安置於本體區域28內(在各例項中)存在於該相同本體區域28中之源極區域30之間之一位置處。如自圖3a顯而易見，在一本體區域28內之一本體接觸區域35之任一側上之源極區域30結合該本體區域28之任一側上之不同閘極電極32操作。p+本體接觸區域35經充分重度摻雜以提供至本體區域28之良好歐姆接觸。在此實施例中，源極區域30及本體接觸區域35之表面包覆有金屬矽化物34s (諸如矽化鈦或矽化鈷)且因而電連接在一起使得源極區域30及本體區域28處在相同電位。如下文將結合VDMOS 20之製造描述般，閘極電極32可包覆有可與金屬矽化物34s同時形成之金屬矽化物34g。側壁絕緣體細絲36協助維持閘極包層34g與源極包層34s之分離且亦協助控制裝置之臨限值電壓，如在下文中將論述。 在此實施例中，如圖3a中展示，絕緣體層33安置於包含閘極電極32及源極區域30之VDMOS 20之作用結構上方。此絕緣體層33(其可係氧化矽、氮化矽、有機介電質或其他介電材料或其等之組合)具有實質上平面且因此未遵循下伏結構之形貌之一上表面。透過絕緣體層33中之接觸開口製成對源極區域30及本體區域28之接觸，鎢或另一適合金屬或金屬化合物之導電插塞38安置至該等接觸開口中。在其中鎢係導電插塞38之材料之此實例中，沿著絕緣體33中之此等接觸開口之側壁且在矽化物膜34s處開口之底部處安置障壁層37。如此項技術中已知，障壁層37可由具有適當厚度及組合物之一或多個金屬或導電金屬化合物構成以防止導電插塞38之材料遷移至下伏矽中。 亦在此實施例中，源極金屬40安置於絕緣體層33之表面處且與導電插塞38之頂部接觸。源極金屬40具有功率裝置(諸如VDMOS 20)中之金屬導體之習知構造，通常包含鋁、銅或適合於支援預期由裝置傳導之電流之金屬之一組合。 圖3b以平面視圖繪示圖3a之積體電路之一部分，其中在源極區域30、本體接觸區域35及閘極電極32之包覆之前且因此在絕緣體層33及源極金屬40之沈積之前之一時間點製造VDMOS 20。如自圖3b顯而易見，在圖3a中之橫截面中展示之各種結構配置為跨其中形成VDMOS 20之積體電路晶粒之內部延伸之平行「條帶」。在圖3b之視圖中顯而易見之結構包含閘極電極32、源極區域30及本體接觸區域35 (雖然存在於此點處，但為了清楚起見，在圖3b中未展示側壁絕緣體細絲36)。圖3b亦以陰影繪示導電插塞38之位置及形狀，導電插塞38安置於穿過上覆絕緣體層33之接觸開口中，如圖3a中展示。當完成此例示性實施方案之製造時，預期源極金屬40將作為一單一導體(即，呈單一金屬片之形狀)上覆於圖3b中展示之結構之整個部分，其中該單一導體製成至全部導電插塞38之頂部之接觸。因此，源極區域30 (及本體區域28)將並聯連接，正如基板24 (圖3a)提供用於VDMOS 20之一單一汲極節點。在此實施例中，由於絕緣體層33及導電插塞38之上表面實質上平面，故沈積於該等結構上方之源極金屬40亦將具有一實質上平坦上表面，隨後可在該上表面上沈積一鈍化介電層(未展示)。 圖3a及圖3b中展示之結構以及本體區域28及柱29 (圖3b中不可見)配置於晶粒之一中央「核心」區域內，該核心區域係VDMOS 20之表面之一功能性作用區域。預期圖3a中展示之結構將跨此核心區域完全延伸，其中提供與圖3b中展示之若干結構並聯之更多(例如，多達大約幾百個)類似結構。如此項技術中已知且例如在2015年10月2日申請之同在申請中且共同讓與之美國申請案S.N. 14/873,831 (該案以引用的方式併入本文中)中描述般，此實施方案中之VDMOS電晶體20通常亦將包含包圍此「核心」區域之一終止區域。如在上文併入之美國申請案S.N. 14/873,831中描述般，該終止區域包含終止結構(諸如場板、護環、非作用柱及類似者)以基本上藉由將電場自垂直(在核心處)平滑扭曲至水平(在晶粒之外邊緣處)同時防止峰值電場達到臨界電場及引起裝置崩潰而橫向維持關斷狀態之汲極至源極電壓。 替代呈平行條帶之形式之圖3a及圖3b之結構，p型柱29及VDMOS 20之其他對應元件可配置為一「單元」陣列。在2015年8月25日頒布之與本申請案共同讓與且以引用的方式併入本文中之美國專利第9,117,899號針對一溝槽閘極VDMOS電晶體之情況描述此一單元類型幾何形狀之一實例。預期熟習此項技術者在參考本說明書之後可容易在無不當實驗之情況下使圖3a及圖3b中展示且上文中描述之實例適於此一「單元」類型之結構。 根據此實施例之一垂直功率裝置之結構提供效能、按比例調整、可製造性及可靠性方面之重要優點。特定言之，此結構使絕緣體層33之厚度Tinsul 之參數與源極金屬40之厚度Tmet 之參數分離，使得可選擇此等厚度之各者而不受另一者顯著限制。更具體言之，在此實施例中，閘極電極32上方之絕緣體層33之厚度Tinsul 可經選擇以最小化閘極至源極電容Cgs而不受源極金屬40製成至源極區域30及本體區域28之一可靠接觸之能力限制。相反的，在此實施例中，源極金屬40之厚度Tmet 可經選擇以支援在接通狀態中時由VDMOS 20傳導之高電流而不受至源極/本體接觸開口中之階梯覆蓋或該等接觸開口之寬度或絕緣體層33之厚度Tinsul 限制，從而避免源極金屬40之厚度Tmet 與絕緣體層33之厚度Tinsul 之間之一折衷。另外，可相對於習知結構顯著改良VDMOS 20之切換效能及電流容量。源極區域30、本體接觸區域35及閘極電極32之矽化物包層亦藉由減小該等結構及接觸之電阻而改良裝置效能。 為了類似原因，本發明之此實施例提供一更可製造且可靠結構，其中極大消除在其至矽之接觸處之源極金屬之薄化。另外，此實施例藉由消除如在諸如上文關於圖2a及圖2b描述之習知結構中必需之蝕刻穿過源極區域以便製成至本體區域之接觸之需要而提供一顯著更可製造結構。 此實施例亦實現VDMOS 20之裝置大小之進一步按比例調整。如在習知結構(其中由於針對所要源極金屬厚度接觸開口太窄而發生金屬沈積之陰蔽)中，在此構造中，穿過絕緣體33之接觸開口之寬度不受源極金屬40之厚度Tmet 限制。根據此實施例，接觸間距不受源極金屬40之厚度Tmet 影響，且因而可獨立選擇兩個參數。此外，藉由消除源極金屬40之階梯覆蓋問題而增強VDMOS 20之潛在可靠性。且由於源極金屬40之頂表面如圖3a中展示般係實質上平面，故歸因於在該表面處缺乏形貌階梯而亦增強上覆鈍化層之完整性。 預期熟習此項技術者在參考本說明書之後將明白根據此實施例之一VDMOS電晶體之結構之此等及其他優點。 現在結合圖5a至圖5h參考圖4，現在將描述根據本發明之一實施例之製造VDMOS 20之一方法。此方法開始於程序50，其中根據如此項技術中已知之習知磊晶，將n型漂移磊晶層26磊晶形成至n+基板24上。針對其中VDMOS 20係一超級接面裝置之此實施例中，程序50將在若干反覆中形成磊晶層26，各反覆包含磊晶形成一選定厚度之n型矽，接著在欲形成柱29之位置處遮罩植入p型摻雜劑(例如，硼)且(視情況)退火經植入摻雜劑。柱植入彼此對準以便形成自磊晶層26之表面延伸至所要深度之p型摻雜劑之多個柱；此等柱29藉由層26之n型磊晶矽之區域彼此分離，如上文中描述。 接著，根據此實施例，在程序52中形成VDMOS 20之閘極結構。以習知方式，可藉由磊晶層26 (及本體區域28)之表面之熱氧化而形成閘極介電質31；替代地，閘極介電質31可係二氧化矽、氮化矽、另一適合閘極介電材料或此等材料之一組合之一沈積層。接著以習知方式藉由以下步驟形成閘極電極32：沈積一所要閘極材料(諸如多晶矽)層，接著進行光微影圖案化及蝕刻以在所要位置處且按所要尺寸界定閘極電極32。 在程序53中，藉由離子植入接著驅入退火而在磊晶層26之表面處形成本體區域28。如在程序53中植入之摻雜劑(例如，硼)與閘極電極32之邊緣自對準，且將由於驅入退火而在閘極電極32下方橫向擴散。VDMOS 20之最終通道長度將取決於在程序53中植入之p型本體區域摻雜劑橫向擴散超過隨後n型源極植入擴散之距離。程序53之植入亦與柱29對準使得本體區域28與對應柱29形成連續p型區域。本體區域28之摻雜劑濃度可不同於柱29之摻雜劑濃度且通常將針對所要電晶體特性最佳化。另外，如由上文描述之圖3a所示，本體區域28之橫向邊界可不同於對應下伏柱29之橫向邊界。 在程序52、53中形成閘極電極32及本體區域28之後，在程序54中光微影界定p+本體接觸區域35在閘極電極32之間之本體區域之表面處之位置。可以習知方式執行程序54，例如包含施配光阻劑、光微影曝露光阻劑以界定所要圖案及使曝露光阻劑顯影以選擇性移除不充當最終遮罩之部分。圖5a繪示在程序54之後之製造中之一點之VDMOS 20之結構，具體言之其中光阻劑遮罩特徵55保留於閘極電極32之間之空間內之位置處。在程序56中，在該等遮罩特徵55之任一側上之本體區域28之表面之曝露位置30’接收n型摻雜劑(例如，砷、磷)之離子植入，如圖5a中展示；藉由一後續驅入退火而將經植入摻雜劑擴散至所要輪廓。在該退火及其他後續熱程序之後，可以此項技術中熟知之習知方式選擇程序56之源極植入之劑量及能量以導致所要摻雜劑輪廓；舉例而言，此源極植入可係以通常在5E15個原子/cm2 至1E16個原子/cm2 之範圍中之一劑量及在30 KeV至200 KeV之範圍中之一能量之磷或砷植入。在此實施例中，作為在額外植入之後之一單一熱程序執行此源極植入之退火，如在下文中將描述；替代地，可在緊接在源極植入程序56之後之此點執行一退火。 在源極植入程序56之後，在程序58中移除光阻劑遮罩特徵55。如在針對垂直功率裝置之技術中典型般，接著在程序60中可以足以提供本體區域28及下伏源極區域30內之一最終重度摻雜p型區域之一劑量及能量執行一p型植入。此「p基」區域減少VDMOS 20中之寄生SCR觸發且引起結構之閉鎖之傾勢，如此項技術中已知。在此實例中，在一後續植入之後之一單一退火中執行此p基植入之退火；替代地，可在此植入程序60之後執行一退火以驅入p基植入及可能亦源極植入。 接著執行程序62以沿著閘極電極32之側邊緣形成側壁絕緣體細絲36。可以習知方式(例如)藉由以下步驟執行程序62：沈積所要介電材料(例如，氧化矽、氮化矽)，接著進行各向異性蝕刻以清除閘極電極32及本體區域28之表面同時使細絲36留在適當位置中。 接著，在程序64中執行離子植入p型摻雜劑(例如，硼)以形成p+本體接觸區域35，如在圖5b中展示。由於在程序60中移除遮罩特徵55，故程序64之植入將重度摻雜各本體區域28中之源極區域30之間之間隙。此植入將具有經選擇足以使本體接觸區域35提供良好歐姆接觸之一劑量及能量，例如具有通常在1E15個原子/cm2 至5E15個原子/cm2 之範圍中之一劑量及通常在20 KeV至200 KeV之範圍中之一能量之硼或BF2 植入。然而，此p+本體接觸區域植入之劑量應小於n+源極植入之劑量以容許n+源極植入在n+源極區域30中占主導地位。在此離子植入之後，執行一高溫退火以退火在程序64中植入之摻雜劑及可能亦在程序56及60中植入之摻雜劑以導致源極區域30及本體接觸區域35 (及藉由p基植入60形成之本體區域28之重度摻雜部分)之所要摻雜劑輪廓。 根據此實施例在程序53之本體區域植入之後且在程序64之本體接觸植入之前，在程序62中沿著閘極電極32形成側壁絕緣體細絲36實現對最終VDMOS 20之臨限值電壓之增強控制。更具體言之，側壁絕緣體細絲36之寬度Wsw 使在程序62中植入n型植入位置30’內之p+本體接觸區域摻雜劑與下伏於閘極電極32之p型本體區域28之橫向擴散邊緣之邊緣隔開。此間隔促進對下伏於閘極電極32之通道區域中具體言之在源極區域35與n型磊晶層26之間之本體區域28之部分內之摻雜劑濃度之控制。 根據此實施例，在程序66中執行對源極區域30、本體接觸區域35及可能閘極電極32之曝露表面之矽化。熟知自對準直接反應矽化(「矽化金屬沈積」)技術可用於包覆此等結構。因而，矽化程序66包含與半導體材料及亦絕緣體材料兩者接觸之一金屬之整體沈積。適合於矽化之金屬之實例包含鈦、鈷及類似者，如圖5c中展示。在金屬沈積之後，矽化程序66繼續在一適合氛圍(例如，氮)中高溫退火裝置，在該退火期間，與矽接觸之沈積金屬之部分將反應以形成金屬矽化物，且與絕緣體材料(二氧化矽或氮化矽，諸如側壁絕緣體細絲36)接觸之經沈積金屬之部分將不反應或將形成一不同金屬化合物(例如，氮化鈦)。接著藉由一毯覆式蝕刻完成矽化程序66以自絕緣體結構移除金屬化合物同時使金屬矽化物特徵留在適當位置中，諸如在圖5d中藉由在源極區域30及本體接觸區域35處之金屬矽化物34s及在閘極電極32處之金屬矽化物34g所展示。側壁絕緣體細絲36有助於使閘極電極32之表面處之金屬矽化物34g與源極區域30處之金屬矽化物34s分離以避免此等結構之短路。如上文中論述，金屬矽化物34s提供源極區域30與本體接觸區域35之間之一電接觸使得源極區域30及本體區域28在VDMOS 20之操作中將處在相同電位。圖5d亦繪示由上文中描述之植入後退火(以及矽化程序66自身之高溫退火)所致之源極區域30及本體接觸區域35之輪廓。 在矽化程序66之後，接著在程序68中整體沈積絕緣體層33。在此實施例中，絕緣體層33由以習知方式藉由化學氣相沈積而沈積之二氧化矽形成；替代地，可在程序68中沈積如適合於絕緣體層33之功能之其他材料。在沈積時，絕緣體層33通常保形於下伏拓樸，尤其如圖5d中展示般由閘極電極32呈現之拓撲。根據此實施例，在程序68中，(例如)藉由化學機械拋光(CMP)或藉由一電漿回蝕程序而將絕緣體層33之上表面平坦化至如圖5e中展示之其最終厚度Tinsul 。 在程序70中，以習知方式光微影圖案化及蝕刻接觸開口使之穿過絕緣體層33以曝露源極區域30及本體接觸區域35處之矽化物膜34s之位置。在其中厚度Tinsul 顯著大於接觸開口之寬度之該等實施方案中，較佳可藉由一習知電漿蝕刻執行程序70之接觸蝕刻。圖5f繪示在接觸蝕刻程序70之後VDMOS 20之結構。 在程序72中，在表面上方沈積用於形成導電插塞38之導電材料。諸如鎢、鈦及此等及類似金屬之合金之金屬通常用作導電插塞之金屬且在此實施例中可充當導電插塞38。針對諸如鎢之金屬，在程序72中首先沈積一或多個障壁層37以抑制來自導電插塞38之金屬原子擴散至作用半導體中係有用的；適合障壁層之實例包含諸如鈦之金屬及諸如氮化鈦之金屬氮化物。如圖5g中展示，在引起材料黏著至絕緣體33中之接觸開口之側壁以及沈積至矽化物膜34s之曝露部分及平坦化絕緣體層33之頂表面上之條件下整體沈積障壁層37。在障壁層37之沈積之後，導電插塞38之金屬經整體沈積，從而塡充穿過絕緣體層33之接觸開口之剩餘部分且延伸於絕緣體層33之頂表面處之障壁層37上方，如圖5g中展示。預期可針對選定金屬藉由如此項技術中已知之習知方法實行金屬沈積程序72。在程序74中，在除了接觸開口處以外之全部區域中移除插塞金屬38。程序74可藉由插塞金屬38及障壁層37之化學機械拋光(CMP)執行而停止在絕緣體層33之頂表面處以導致如圖5h中展示之結構。替代地，程序74可藉由CMP或藉由回蝕(在任一情況中停止在下伏障壁層37上)而僅移除插塞金屬38。 在程序74之後，接著在程序76中沈積、光微影圖案化及蝕刻源極金屬40。除了如上文描述般充當VDMOS 20之「核心」區域內之源極金屬40之外，此相同金屬層亦可充當接觸閘極電極32之導體(即，充當「閘極金屬」)且亦充當積體電路之終止區域及周邊中之等電位環中之金屬。由於在程序68中平坦化絕緣體層33之上表面，源極金屬40將在其頂表面處展現最小垂直形貌變動。針對現代垂直功率裝置(諸如VDMOS 20)，預期源極金屬40之厚度Tmet 將係至少約2 μm厚且將通常厚達若干μm (例如，大約4 μm至5 μm，其中一使用上限通常約10 μm)。接著在程序78中在源極金屬40之頂表面上方沈積一鈍化層，其中執行光微影圖案化及蝕刻以敞開銲墊及類似者。 在程序78中，預期在此實施方案中之源極金屬40之平坦化藉由提供用於鈍化金屬(諸如具有所要性質之氮化矽)之沈積之一平面表面而進一步改良VDMOS 20之可靠性。因此，經沈積鈍化材料在拓撲步驟較少經受破裂且因此可具有經改良之完整性。 根據此實施例之製造VDMOS 20之方法提供結合可製造性之特定優點。可製造性之一個此優點係消除如上文關於2a描述之蝕刻穿過n+源極區域以製成至該等源極區域及本體區域兩者之同時接觸。至下伏矽中之此一定時蝕刻在實務上高度可變動，從而導致至本體區域之偏壓接觸及所得電效能之廣泛變動。相比之下，根據此實施例無需蝕刻至下伏半導體中，但代替性地可使用至在源極區域及一本體接觸區域之表面處之一金屬矽化物膜之一端點蝕刻可靠地製成至裝置本體區域之源極接觸。因此極大減少在以此方式建構之VDMOS裝置之一群體當中之所得接觸之變動。 另外，藉由此實施例之製造方法提供上文論述之效能、可靠性及可擴縮性之優點而不極大複雜化製造程序。僅需要一單一額外光微影操作，具體言之在遮罩源極植入中界定本體接觸區域之位置；此額外光微影步驟亦在某種程度上係非關鍵的，只要關注對準或大小即可，此係因為在源極區域之間精確放置本體接觸區域並非尤其關鍵。因此，以消除絕緣體層厚度、源極金屬厚度及接觸間距之間之相依性之一方式提供至源極及本體區域之極佳接觸。可以實現裝置之按比例調整之一方式減少裝置之閘極至源極電容而不顯著影響源極金屬之電流傳導能力。 預期本發明之實施例可類似地應用至包含絕緣閘極雙極性電晶體(IGBT)及垂直閘控功率二極體之其他垂直功率裝置。圖6a藉由類似於針對VDMOS 20之圖3a之橫截面視圖之一橫截面視圖繪示根據一實施例建構之IGBT 80之一實例；類似結構特徵由相同元件符號展示且將不進一步描述。在此實例中，IGBT 80如下般不同於VDMOS 20：a) p柱未下伏於p型本體區域28；及b)由於垂直IGBT 80具有在半導體之底部處之一p+集極終端82，故IGBT 80通常將建構於塊狀(即，非磊晶) n型半導體基板26 (而非如在VDMOS 20之情況中之n+基板24)上。在此構造中，在製造頂表面組件之後且在機械研磨或化學蝕刻以薄化基板之後將p+集極82植入至n型基板26之底側中；接著將退火結構以電活化p+集極植入。金屬導體40使p+區域35 (如在VDMOS 20中，其提供至p本體區域28之電接觸)及n+區域30 (現為IGBT 80之發極)與經供能以形成一通道之閘極電極32連接。IGBT 80之表面結構在其他方面與上文中描述之VDMOS 20之表面結構基本上相同。如在VDMOS 20之情況中，根據此實施例之IGBT 80獲得上文中論述之效能、可靠性及可擴縮性之優點。 圖6b繪示根據另一實施例之垂直閘控二極體90之構造；又，與圖3a之VDMOS 20類似之結構由相同元件符號指代。此實施例之二極體90與VDMOS 20類似地建構，其中n型磊晶層26如先前般形成於n+基板24上，且取決於二極體90是否需要採用一電荷平衡裝置構造而在本體區域28下方可或可不包含p型柱29。n+基板24提供用於二極體90之陰極連接，而金屬導體40充當陽極及閘極連接。根據此實施例之垂直二極體90藉由在閘極矽化物34g (及閘極電極32)與源極矽化物34s之間提供一局部連接84而不同於上文描述之VDMOS 20。根據此實施例，藉由遮罩側壁絕緣體細絲36之表面之部分使之免受用於在金屬矽化物34s、34g之直接反應矽化(即，作為圖4之程序66之部分)之後移除未反應金屬之蝕刻而獲得局部連接84。在經遮罩位置處之剩餘金屬可未經反應(例如，鈦或鈷金屬)或係矽化物金屬之一導電化合物(例如氮化鈦，針對在矽化反應中在氮氛圍中反應之鈦金屬之情況)或該等導電物種之一組合。此局部連接84藉由最小化(一方面)p+區域35與n+區域30之間，另一方面p+區域35與閘極電極32之間之電阻而實現優越裝置暫態導通(transient turn-on)效能。另外，此構造獲得上文結合本發明之其他實施例論述之可靠性及可擴縮性之優點。 雖然在本說明書中已描述一或多項實施例，當然預期此等實施例之修改及替代，一般技術者在參考本說明書及其圖式之後將明白能夠獲得本發明之一或多個優點及益處之此等修改及替代例。預期此等修改及替代例係在如本文中隨後主張之本發明之範疇內。
2‧‧‧非超級接面垂直漂移金屬氧化物半導體(VDMOS) 2’‧‧‧超級接面垂直漂移金屬氧化物半導體(VDMOS) 4‧‧‧n+基板 6‧‧‧n型磊晶層 6’‧‧‧磊晶層 8‧‧‧p型本體區域 9‧‧‧p型摻雜柱 10‧‧‧n+源極區域 11‧‧‧閘極介電質 12‧‧‧閘極電極 13‧‧‧絕緣體層 14‧‧‧源極金屬 20‧‧‧垂直漂移金屬氧化物半導體(VDMOS)/n通道垂直漂移金屬氧化物半導體(VDMOS)電晶體 24‧‧‧n+基板 26‧‧‧n型磊晶層 28‧‧‧p型本體區域 29‧‧‧p型摻雜柱 30‧‧‧n+源極區域 30’‧‧‧曝露位置/n型植入位置 31‧‧‧閘極介電質 32‧‧‧閘極電極 33‧‧‧絕緣體層 34g‧‧‧金屬矽化物/閘極包層 34s‧‧‧金屬矽化物/源極包層/矽化物膜 35‧‧‧p+本體接觸區域 36‧‧‧側壁絕緣體細絲 37‧‧‧障壁層 38‧‧‧導電插塞 40‧‧‧源極金屬 50‧‧‧程序 52‧‧‧程序 53‧‧‧程序 54‧‧‧程序 55‧‧‧程序 56‧‧‧程序 58‧‧‧程序 60‧‧‧程序 62‧‧‧程序 64‧‧‧程序 66‧‧‧程序 68‧‧‧程序 70‧‧‧程序 72‧‧‧程序 74‧‧‧程序 76‧‧‧程序 78‧‧‧程序 80‧‧‧絕緣閘極雙極性電晶體(IGBT) 82‧‧‧p+集極終端 84‧‧‧局部連接 90‧‧‧垂直閘控二極體 Cgs‧‧‧寄生閘極至源極電容 Dct‧‧‧深度 Ids‧‧‧源極-汲極電流 Rch‧‧‧通道電阻 Repi‧‧‧n型磊晶層之電阻 Tmet‧‧‧源極金屬之厚度 Tinsul‧‧‧絕緣體層之厚度 Wct‧‧‧接觸寬度 Wsw‧‧‧側壁絕緣體之寬度
圖1a及圖1b分別係習知非超級接面VDMOS電晶體及超級接面VDMOS電晶體之橫截面視圖。 圖2a及圖2b係一習知超級接面VDMOS電晶體中之源極及本體接觸區域之橫截面視圖。 圖3a係根據一實施例建構之一超級接面VDMOS電晶體之一部分之一橫截面視圖。 圖3b係根據該實施例之圖3a之VDMOS電晶體之一部分之一平面視圖。 圖4係繪示根據一實施例製造圖3a及圖3b之超級接面VDMOS電晶體之一方法之一流程圖。 圖5a至圖5h係圖3a及圖3b之超級接面VDMOS電晶體之一部分在根據圖4之實施例之製造之各個階段之橫截面圖。 圖6a係根據一實施例建構之一絕緣閘極雙極性電晶體(IGBT)之一部分之一橫截面視圖。 圖6b係根據一實施例建構之一閘控功率二極體之一部分之一橫截面視圖。
20‧‧‧垂直漂移金屬氧化物半導體(VDMOS)
24‧‧‧n+基板
26‧‧‧n型磊晶層
28‧‧‧p型本體區域
29‧‧‧p型摻雜柱
30‧‧‧n+源極區域
31‧‧‧閘極介電質
32‧‧‧閘極電極
33‧‧‧絕緣體層
34g‧‧‧金屬矽化物/閘極包層
34s‧‧‧金屬矽化物/源極包層
35‧‧‧p+本體接觸區域
36‧‧‧側壁絕緣體細絲
37‧‧‧障壁層
38‧‧‧導電插塞
40‧‧‧源極金屬
Tmet‧‧‧源極金屬之厚度
Tinsul‧‧‧絕緣體層之厚度

Claims (24)

  1. 一種積體電路，其包括： 一第一導電類型之一半導體基板； 該第一導電類型之一磊晶層，其上覆於該基板，該磊晶層具有比該基板更輕之一摻雜劑濃度； 複數個閘極電極，其等安置於該磊晶層之表面附近且彼此隔開； 一第二導電類型之複數個本體區域，其等安置至閘極電極之間之位置處該磊晶層之該表面中； 在各本體區域內，該第一導電類型之第一源極區域及第二源極區域安置於該本體區域之表面處； 在各經摻雜本體區域內，該第二導電類型之一本體接觸區域安置於該表面處該第一源極區域與該第二源極區域之間； 一金屬矽化物包層，其在各本體區域之該第一源極區域及該第二源極區域之至少一部分及該本體接觸區域之表面處； 一絕緣層，其上覆於該等閘極電極且具有一平坦化表面； 複數個導電插塞，其等透過該絕緣層中之一接觸開口接觸該金屬矽化物包層；及 一金屬導體，其安置於該絕緣層上方且與該複數個導電插塞接觸。
  2. 如請求項1之積體電路，其進一步包括： 該第二導電類型之複數個柱，其等各形成至該磊晶層中下伏於該等本體區域之一者之一位置處且與該等本體區域之一者接觸。
  3. 如請求項1之積體電路，其中該第一源極區域及該第二源極區域各具有相對於該等閘極電極之一者自對準之一邊緣。
  4. 如請求項1之積體電路，其進一步包括： 一閘極介電層，其安置於各閘極電極與該磊晶層之該表面之間； 一側壁絕緣體元件，其沿著各閘極電極之各側安置。
  5. 如請求項1之積體電路，其中該導電插塞包括： 一或多個障壁金屬層，其等沿著該接觸開口之側及底部安置；及 一金屬插塞，其經安置鄰近該障壁金屬。
  6. 如請求項5之積體電路，其中該障壁金屬包括鈦且該金屬插塞包括鎢。
  7. 如請求項1之積體電路，其中該金屬矽化物包層亦安置於各閘極電極之一表面處。
  8. 如請求項7之積體電路，其進一步包括： 一側壁絕緣體元件，其沿著各閘極電極之各側安置。
  9. 如請求項8之積體電路，其進一步包括： 一局部互連件，其安置於該側壁絕緣體元件之表面上且製成在安置於該閘極電極處之該金屬矽化物包層與安置於該第一源極區域及該第二源極區域之至少一部分及該本體接觸區域之該表面處之該金屬矽化物包層之間之電接觸。
  10. 一種製造一垂直功率裝置之方法，其包括： 在一第一導電類型之一半導體之一表面附近形成彼此隔開之複數個閘極電極； 在該表面處形成一第二導電類型之複數個本體區域，該複數個本體區域藉由下伏於該等閘極電極之表面之位置彼此隔開； 將該第一導電類型之第一源極區域及第二源極區域形成至各本體區域中； 將該第一源極區域與該第二源極區域之間之位置處之該第二導電類型之一本體接觸區域形成至各本體區域中； 沈積與該等源極區域及本體接觸區域接觸之一金屬； 接著加熱該金屬以在該等源極區域及本體接觸區域之表面處形成一金屬矽化物； 整體沈積一絕緣體材料； 平坦化該絕緣體材料； 形成穿過該平坦化絕緣體材料之接觸開口； 在該等接觸開口中形成複數個導電插塞使之與該等源極區域及本體接觸區域之該表面處之該金屬矽化物電接觸；及 接著形成與該複數個導電插塞電接觸之一金屬導體。
  11. 如請求項10之方法，其中形成該第一源極區域及該第二源極區域之該步驟包括： 遮罩各本體區域在鄰近閘極電極之間之一位置處之一部分以曝露在該經遮罩部分之相對側上之表面位置；及 將該第一導電類型之摻雜劑植入至該等本體區域之該等曝露表面位置中。
  12. 如請求項11之方法，其中形成該等本體接觸區域之該步驟包括： 在植入該第一導電類型之摻雜劑之該步驟之後，將該第二導電類型之摻雜劑植入至該等本體區域中；及 接著退火該第二導電類型之該經植入摻雜劑。
  13. 如請求項12之方法，其進一步包括： 在植入該第一導電類型之摻雜劑之該步驟之後且在形成該等本體接觸區域之該步驟之前，依經選擇以在該等本體區域內下伏於該等源極區域之位置處提供該第二導電類型之一較高摻雜劑濃度之一劑量及能量將該第二導電類型之摻雜劑植入至該等本體區域中。
  14. 如請求項12之方法，其中形成該等本體區域之該步驟包括： 以相對於該等閘極電極之一自對準方式將該第二導電類型之摻雜劑植入至該表面中；及 接著加熱該半導體； 且進一步包括： 在植入該第一導電類型之摻雜劑之該步驟之後且在形成該等本體接觸區域之該步驟之前，在該等閘極電極之側邊緣上形成側壁絕緣體細絲。
  15. 如請求項10之方法，其中形成複數個導電插塞之該步驟包括： 整體沈積一障壁金屬； 整體沈積一導電金屬；及 自該絕緣層之表面移除該導電金屬，使該導電金屬僅留在該等接觸開口中。
  16. 如請求項15之方法，其中該障壁金屬包括鈦； 且其中該導電金屬包括鎢。
  17. 如請求項10之方法，其中形成一金屬導體之該步驟包括： 將金屬整體沈積至至少約2 μm且小於約10 μm之一所要厚度；及 移除該經沈積金屬之選定部分以界定各與該等導電插塞之一或多者電接觸之一或多個金屬導體。
  18. 如請求項17之方法，其進一步包括： 在形成一金屬導體之該步驟之後，沈積一絕緣鈍化層。
  19. 如請求項10之方法，其進一步包括： 在形成該等本體區域之該步驟之前，在該第一導電類型之一基板上方形成該第一導電類型之一磊晶層； 其中在該磊晶層之表面處形成該等本體區域。
  20. 如請求項19之方法，其中形成該磊晶層之該步驟包括： 磊晶形成該磊晶層之一部分； 接著使用該第二導電類型之摻雜劑植入該磊晶層之複數個選定部分；及 重複複數次該等磊晶形成及植入步驟以在該第一導電類型之該磊晶層內形成該第二導電類型之經摻雜材料之複數個柱。
  21. 如請求項10之方法，其進一步包括： 在形成該等本體區域之該步驟之前，在該第一導電類型之一基板上方形成該第一導電類型之一磊晶層。
  22. 如請求項10之方法，其中沈積與該等源極區域及該等本體接觸區域接觸之一金屬之該步驟亦沈積與該等閘極電極接觸之該金屬； 其中該加熱步驟亦在該等閘極電極之該表面處形成一金屬矽化物； 且其進一步包括： 在沈積與該等源極區域及本體接觸區域接觸之一金屬之該步驟之前，沿著該等閘極電極之側形成側壁絕緣體元件；及 在該加熱步驟之後，移除該非矽化金屬。
  23. 如請求項22之方法，其進一步包括： 在該加熱步驟之後且在移除該非矽化金屬之該步驟之前，遮罩上覆於側壁絕緣體元件之該非矽化金屬之位置。
  24. 一種積體電路，其包括： 一第一導電類型之一半導體基板； 複數個閘極電極，其等安置於該基板之一頂表面附近且彼此隔開； 一第二導電類型之複數個本體區域，其等安置至該基板之該表面中閘極電極之間之位置處； 在各本體區域內，該第一導電類型之第一源極區域及第二源極區域安置於該本體區域之表面處； 在各經摻雜本體區域內，該第二導電類型之一本體接觸區域安置於該表面處該第一源極區域與該第二源極區域之間； 一金屬矽化物包層，其在各本體區域之該第一源極區域及該第二源極區域之至少一部分及該本體接觸區域之該表面處； 一絕緣層，其上覆於該等閘極電極且具有一平坦化表面； 複數個導電插塞，其等透過該絕緣層中之一接觸開口接觸該金屬矽化物包層； 一金屬導體，其安置於該絕緣層上方且與該複數個導電插塞接觸；及 一第二導電類型之一集極區域，其在該基板之一底表面處且與該基板之該第一導電類型材料形成一冶金接面。
TW105129978A 2015-10-01 2016-09-14 在垂直功率半導體裝置中之源極－閘極區域架構 TW201725728A (zh)

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