TWI728476B - Ｌｄｍｏｓ裝置、包含ｌｄｍｏｓ裝置之積體電路，以及製造該積體電路的方法 - Google Patents

Ｌｄｍｏｓ裝置、包含ｌｄｍｏｓ裝置之積體電路，以及製造該積體電路的方法 Download PDF

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TWI728476B
TWI728476B TW108134232A TW108134232A TWI728476B TW I728476 B TWI728476 B TW I728476B TW 108134232 A TW108134232 A TW 108134232A TW 108134232 A TW108134232 A TW 108134232A TW I728476 B TWI728476 B TW I728476B
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國偉 張
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新加坡商格羅方德半導體私人有限公司
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Abstract

本發明提供橫向擴散金屬氧化物矽(LDMOS)裝置、包括LDMOS裝置的積體電路、以及製造該積體電路的方法。範例LDMOS裝置包括具有表面的基底、覆於該表面和在閘極結構下方的該基底中的通道區域上的該閘極結構、以及在該基底中的汲極區域。該LDMOS裝置復包括設置在該基底的該表面處的該閘極結構與該汲極區域之間的表面絕緣體區域、以及不同於該表面絕緣體區域並且位在該表面絕緣體區域上方的介電阻擋件。並且，該LDMOS裝置包括場效結構。該場效結構包括設置在該基底的該表面上方並且遠離該基底的該表面的場板。該場效結構也包括耦接至該場板並且從該場板朝向該介電阻擋件延伸的導電結構。

Description

LDMOS裝置、包含LDMOS裝置之積體電路，以及製造該積體電路的方法
本揭露大致上是關於積體電路和製造積體電路的方法，尤是關於具有橫向擴散金屬氧化物半導體(LDMOS)裝置的積體電路。
LDMOS電晶體裝置使用在許多應用中，例如用於手機、ADSL驅動器、LED顯示器、LCD顯示器驅動器、用於無線基地台的高功率放大器、以及其它的電源管理。LDMOS裝置典型地依賴形成在絕緣區域(例如，LOCOS(「矽局部氧化」)區域或STI(淺溝槽隔離)區域)下方的淺傳導層，以應付於該LDMOS裝置被偏壓時所施加的較高汲極電壓。
該裝置的導通(on-state)電阻(RDSon)和最大崩潰電壓(BV)是用於LDMOS裝置的兩個重要運作參數，並且決定該裝置可利用的應用。導通電阻通常取決於該裝置的設計/佈局、程序條件、溫度、擴散長度、以及用來製作該裝置的各種材料。崩潰電壓是定義為可施加至二極體(例如，p-n接面)、但尚不致引發該二極體的電流的指數性增加的最大反向電壓。
可運作在接近半導體的理論崩潰電壓的高電壓的LDMOS裝置較佳作為理想的電源半導體裝置。大致上，LDMOS裝置適合於高電壓，因為這種裝置包括在該通道區域與該汲極區域之間的漂移區域。理想上，在最大崩潰電壓的點處，LDMOS電晶體的延伸汲極區域是完全空乏電荷載子。該LDMOS電晶體中的高電場於該延伸的汲極區域完全地空乏時降低，並且LDMOS電晶體中的電場於該延伸的汲極區域完全地空乏時，在該延伸的汲極區域的長度上方均勻地散開。因此，LDMOS電晶體的崩潰電壓於該延伸的汲極區域是完全地空乏時最大。該延伸的汲極區域可藉由輕度摻雜該延伸的汲極的狹長漂流部分而予以空乏。然而，輕度摻雜的漂移區域增加該LDMOS裝置的導通電阻，其劣化RF性能。
因此，希望提供具有高崩潰電壓和低導通電阻的LDMOS裝置。 額外地，希望將這種裝置與具有較低崩潰電壓的LDMOS裝置整合至積體電路裝置中。並且，希望提供製造具有高崩潰電壓的LDMOS裝置的方法、以及製造具有具有高崩潰電壓的LDMOS裝置和具有較低崩潰電壓的LDMOS裝置的積體電路的方法。再者，其它希望特徵和特性從接下來的實施方式和附加的申請專利範圍、並連同伴隨的圖式和先前的技術領域和背景，將變得明顯。
提供橫向擴散金屬氧化物半導體(LDMOS)裝置、包括LDMOS裝置的積體電路、以及製造該積體電路的方法。範例LDMOS裝置包括具有表面的基底、覆於該表面和在閘極結構下方的該基底中的通道區域上的該閘極結構、以及在該基底中的汲極區域。該LDMOS裝置復包括設置在該基底的該表面處的 該閘極結構與該汲極區域之間的表面絕緣體區域、以及不同於該表面絕緣體區域並且位在該表面絕緣體區域上方的介電阻擋件。並且，該LDMOS裝置包括場效結構。該場效結構包括設置在該基底的該表面上方並且遠離該基底的該表面的場板。該場效結構也包括耦接至該場板並且從該場板朝向該介電阻擋件延伸的導電結構。
在另一個實施例中，積體電路裝置包括具有表面的基底、第一LDMOS裝置、第二LDMOS裝置、以及組構成增加該第二LDMOS裝置的崩潰電壓的場效結構。該第一LDMOS裝置包括在該基底中的第一源極區域和第一汲極區域、在該第一源極區域與該第一汲極區域之間的該基底上方的第一閘極結構、以及設置在該第一閘極結構與該第一汲極區域之間的該基底的該表面處的第一表面絕緣體區域。該第一表面絕緣體具有第一厚度和第一寬度。該第二LDMOS裝置包括在該基底中的第二源極區域和第二汲極區域、在該第二源極區域與該第二汲極區域之間的該基底上方的第二閘極結構、設置在該第二閘極結構與該第二汲極區域之間的該基底的該表面處的第二表面絕緣體區域、以及在該第二表面絕緣體區域上方的介電阻擋件。該第二表面絕緣體具有等於該第一厚度的第二厚度和大於該第一寬度的第二寬度。該場效結構包括設置在該第二LDMOS裝置上方並且遠離該基底的該表面的場板。該場效結構復包括耦接至該場板並且從該場板朝向該介電阻擋件延伸的導電結構。
依據另一個實施例，提供製造積體電路裝置的方法。該方法包括形成隔離區域在具有表面的基底中，以定義第一裝置區域和第二裝置區域。該方法復包括氧化該第一裝置區域，以形成第一表面絕緣體區域在該第一裝置區域中和第二隔離區域在該第二裝置區域中。該方法包括沉積閘極材料在該基底上 方並且圖案化該閘極材料，以形成第一閘極結構在該第一裝置區域中和第二閘極結構在該第二裝置區域中。並且，該方法包括形成介電阻擋件在該第二表面絕緣體區域上方。此外，該方法包括形成場效結構在該第二LDMOS裝置上方，其中，該場效結構包括設置在該介電阻擋件上的導電結構。
提供此發明內容，以引進簡化形式的概念的選擇，這些概念在下方詳細描述中進一步描述。此發明內容不意圖識別所請求的發明標的的關鍵特徵或主要特徵，也不意圖用來幫助決定所請求的發明標的的範疇。
10:積體電路裝置
12:基底
14:上表面、表面
16:隔離區域
20:裝置區域
21:第一裝置區域、裝置區域
22:第二裝置區域、裝置區域
32:阱區域
34:漂移區域
36:阱區域
40、41、42:表面絕緣體區域
44:厚度、高度
48:水平介面
51、52:寬度
60:閘極結構
61:閘極介電質
62:源極區域
63:閘極電極
64:汲極區域
65、95:上表面
66:阱接觸區域
70:間隔件
80:LDMOS裝置、LDMOS電晶體、LDMOS電晶體裝置
90:介電阻擋件
92:邊緣
99:層間介電質
100:場效結構
110:場板、導電場板
111、112:端點
114:下表面
120、130:導電柱、導電結構
122:遠端
131、132:虛線
LDMOS裝置、包括LDMOS裝置的積體電路、以及製造這種積體電路的方法的實施例將在下文中連同接下來的圖式加以描述，其中，相同的編號是指相同元件，並且其中： 第1至4圖以剖面方式例示依據本文中的各種實施例的積體電路的一部分以及製造該積體電路的方法；以及 第5和6圖以剖面方式例示第4圖的該LDMOS裝置和場效結構的不同實施例。
接下來的實施方式在本質上只是例示，而不意圖限制如本文中所請求的包括LDMOS裝置的積體電路和製造方法。再者，沒有意圖由先前的技術領域、背景或發明內容中、或接下來的實施方式中所出現的任何明示或暗示的理論所限制。
依據本文中的各種實施例，提供包括LDMOS裝置的積體電路及製造LDMOS裝置的方法。大致上，接下來的實施例是關於形成設有場效結構的至少一個LDMOS裝置，以增加該LDMOS裝置的崩潰電壓。此外，相較於傳統設計，該LDMOS裝置可設有較薄的表面絕緣體區域，但展現較高的崩潰電壓。 此可藉由設置介電阻擋件在該表面絕緣體區域上方加以達成。在相同製造程序期間形成的其它LDMOS裝置可形成沒有該介電阻擋件，並且保留較低的崩潰電壓和對應的較低汲極電阻。這種處理是希望的，因為這種LDMOS裝置是形成具有較薄的表面絕緣體區域，其可用在較小間距處。
第1至4圖循序地例示依據本文中的各種實施例的製造具有LDMOS裝置的積體電路的方法。積體電路的設計和組成中的各種步驟是已知的，並且因此為了簡潔起見，許多傳統步驟在本文中只簡短提到、或整個省略，而沒有提供已知的程序細節。此外，注意到積體電路包括不同數目的組件而在例示中所顯示的單一組件可代表該積體電路中的多個組件。
圖式是部分圖解的、而非按比例的，並且特別是一些尺寸為了清楚呈現而在圖式中誇張地顯示。類似地，雖然圖式中的視圖為了容易描述起見大致上顯示類似轉向，但圖式中的此繪示是任意的。大致上，積體電路可運作在任何轉向中。如本文中所使用的，將了解到，當元件或層是指在另一個元件或層「上方」或「下方」時，它是直接地在該其它元件或層上、或者可出現中介元件或層。 當元件或層是指在另一個元件或層「上」時，它是直接地在該其它元件或層上或與該其它元件或層接觸。此外，空間相對用語，例如，「上」(upper)、「上方」、「下」(lower)、「下方」及類似者在本文中可用於容易描述，以描述一個元件或特徵與另外元件或特徵的關係，如圖式中所例示的。將了解到，除了圖式中所繪 示的轉向，空間相對用語是意圖涵蓋該裝置在使用和運作的不同轉向。舉例來說，如果圖式中的裝置倒過來，則描述成在其它元件或特徵「下方」的元件將之後轉向成在其它元件或特徵「上方」。因此，範例用語「下方」可涵蓋上方或下方的轉向。裝置不然可轉向(轉動90度或在其它轉向)，並且本文中所使用的空間相對描述可同樣地相應被解讀。
雖然「MOS」起初大致上是指金屬氧化物半導體電晶體並且特定地是指金屬氧化物矽電晶體，如本文中所使用的，但LDMOS電晶體指定所有類型的絕緣閘極場效電晶體，不論這種電晶體是否包含金屬閘極，因為術語「MOS」是共同地應用在產業中。舉例來說，「MOS」電晶體包括利用矽閘極科技的那些電晶體，該矽閘極科技使用摻雜多晶矽閘極和矽化的閘極。在特定實施例中，「導體」或「導體區域」是指具有大於1.0×105S/cm的電導性的材料。在特定實施例中，「絕緣體」、「絕緣體區域」、「介電質」或「介電材料」是指具有小於1.0×10-6S/cm的電導性的材料。所有用於電導性的測量均是在標準條件下作成。
現在轉至第1圖，例示範例積體電路裝置10和製造電路裝置10的程序。該範例積體電路裝置10包括具有上表面14的基底12。範例基底12是矽、或其它適合的半導體材料。如本文中所使用的，術語「半導體基底」可包括典型地使用在電性裝置的形成中的任何半導體材料。半導體材料包括單晶矽材料(例如，典型地使用在半導體工業的相當純或輕度摻雜雜質的單晶矽材料)以及多晶矽材料，以及與其它元素(例如，鍺、碳、及類似者)摻合的矽。額外地，「半導體材料」涵蓋其它材料，例如，相對純和摻雜雜質的鍺、鎵鉮化物、鋅氧化物、及類似者。在範例實施例中，該基底12以第二導電類型(例如，p-類型)的元素摻雜。
在第1圖中，隔離區域16(例如，淺溝槽隔離區域)依據傳統處理技術形成在該基底12中。舉例來說，可蝕刻該基底12以形成空洞，該空洞可以熱矽氧化物襯裡和矽氧化物填充物加以填充，並且過剩的隔離材料可藉由化學機械平坦化(CMP)加以移除。隔離區域16可隔離不同的裝置區域20。也就是所選擇的裝置將要形成的區域。舉例來說，第一裝置區域21和第二裝置區域22可由隔離區域16定義。雖然顯示為彼此鄰接，但應注意到第一裝置區域21和第二裝置區域22不須在該基底12上彼此鄰接。
在第1圖中，可實施實作程序以形成阱區域32和漂移區域34在各個裝置區域20中。在特定實施例中，該阱區域32和漂移區域34以相對的摻質類型摻雜。舉例來說，該阱區域32可以第二導電類型(例如，p-類型)的元素摻雜，而該漂移區域34可以第一導電類型(例如，n-類型)的元素摻雜。該阱區域32和漂移區域34可依據傳統處理形成。舉例來說，可在該基底12上方循序地形成並且圖案化，並且實施希望的布植。
如第1圖中所進一步顯示的，形成表面絕緣體區域40。具體而言，表面絕緣體區域41是形成在裝置區域21中，而表面絕緣體區域42是形成在裝置區域22中。表面絕緣體區域40可形成如場氧化物、淺溝槽隔離、或其它適合的絕緣材料。在範例實施例中，該表面絕緣體區域40是藉由熱生長程序形成。 舉例來說，可實施矽局部氧化(LOCOS)程序，其中，氧化物穿透該基底12的表面14，以形成矽氧化物表面絕緣體區域40，使得各個表面絕緣體區域40與該基底12之間的水平介面48是位在低於該基底12的該表面14的平面處。在傳統程序期間，矽氮化物可被沉積、遮蔽、和蝕刻，以選擇性使矽氮化物位在非希望區域 上方，之後，實施LOCOS氧化程序，以在剩餘的矽氮化物被移除前形成該表面絕緣體區域40。
由於相同表面絕緣體區域形成程序而同時形成該表面絕緣體區域41和42，因此，表面絕緣體區域41和表面絕緣體區域42是形成具有相同最大厚度或高度44。舉例來說，該厚度44可從大約500至大約3000埃(A)，例如，大約1500A。然而，藉由在微影處理期間變化尺寸，例如，在圖案化遮罩期間，該表面絕緣體區域41和42可形成具有不同寬度，也就是，表面絕緣體區域41是形成具有寬度51，而該表面絕緣體區域42是形成具有寬度52。在範例實施例中，寬度52大於寬度51。舉例來說，寬度51可從大約0.5至大約1微米(um)，例如，大約0.8um，而寬度52可從大約1至大約5um，例如，大約3um。
在第2圖中，該方法可繼續形成閘極結構60在每個這種裝置區域20中。舉例來說，閘極介電層和閘極材料層可依據傳統處理而沉積在該基底12上方並予以圖案化，以形成閘極結構60，其中，各個閘極結構60均包括閘極介電質61和閘極電極63。在範例實施例中，該閘極介電質61可為矽氧化物，而該閘極電極63可為多晶矽。該閘極結構60可依據傳統閘極形成處理而予以圖案化。
之後可實施進一步的佈植程序。舉例來說，輕度摻雜的汲極區域(未顯示)可形成在各個漂移區域34中。在範例實施例中，該輕度摻雜的汲極區域是以第一導電類型(例如，n-類型)摻雜。用來佈植該汲極區域的程序可利用該閘極結構60作為遮罩。之後，依據傳統處理，形成間隔件70圍繞各個閘極結構60。之後，實施摻雜程序，以形成源極區域62在該阱區域32中和汲極區域64在該漂移區域34中。在範例實施例中，該源極區域62和汲極區域64是以第一 導電類型(例如，n-類型)重度摻雜，也就是，該源極區域62和汲極區域64是n+摻雜的。並且，阱接觸區域66可形成在該阱區域32中。在範例實施例中，該阱接觸區域66是以第二導電類型(例如，p-類型)重度摻雜，也就是，該阱接觸區域66是p+摻雜的。由於所描述的該處理，因此LDMOS裝置80是形成在各個裝置區域20中。
在第3圖中，該方法繼續形成介電阻擋件90在裝置區域22中的該LDMOS裝置80的該表面絕緣體區域40上方。如所顯示的，該介電阻擋件90可與該閘極結構60上的該間隔件70直接接觸。在範例實施例中，該介電阻擋件90沒有接觸該基底12的該表面14，也就是，沒有接觸該汲極區域64。反而是，範例介電阻擋件90是只在該表面絕緣體區域40的中央部分上方直接地形成，而沒有延伸超過該表面絕緣體區域40的邊緣。換言之，該介電阻擋件90的邊緣92接觸該表面絕緣體區域40。此外，在特定實施例中，範例介電阻擋件90是比該閘極結構60在表面絕緣體區域40上方的部分短。在這種實施例中，該閘極結構60在上表面65處具有最大高度並且終止在該上表面65處，而該介電阻擋件90在上表面95處具有最大高度並且終止在該上表面95處。因此，在這種實施例中，介電阻擋件90的上表面95是低於閘極結構60的上表面65或是比閘極結構60的上表面65較接近基底12的表面14。
介電阻擋件90可形成如矽化金屬(自對準矽化物)阻擋件，也就是，用來阻擋下覆表面的矽化的材料。具體而言，在傳統處理以形成裝置在該基底12上期間，實施矽化程序，並且包括矽化金屬阻擋件的形成。如此一來，形成介電阻擋件90在裝置區域22中不會添加任何額外處理至該積體電路製作程序。在範例實施例中，沉積並圖案化一層介電材料，以形成該介電阻擋件90。範例介電阻 擋件90可形成為一層或數層二氧化矽(SiO2)、四乙氧基矽烷(TEOS)、矽氮化物、或其它適合的非導電性或絕緣體材料。在範例實施例中，該介電阻擋件90是形成具有從大約1000至大約4000A(例如，大約2000A)的厚度或高度。
在第4圖中，該方法形成一層或數層介電材料，以形成層間介電質99在基底12上方。此外，如所顯示的，場效結構100是形成在裝置區域22中的該LDMOS裝置80上方。如所顯示的，該場效結構100包括導電場板110和耦接至導電場板110的導電結構120和130(例如，柱)。範例場板110和導電柱120和130是導電材料，例如，銅(例如，金屬1層(metal 1 layer))。眾所周知，該場板110和導電柱120和130可分別形成，或可在溝槽已經形成在層間介電質99中後於單一沉積或填充程序期間形成。
如所顯示的，該場板110是設置在該基底12的該表面14上方並且遠離該基底12的該表面14，並且更具體而言，是直接地設置在裝置區域22中的該閘極結構60上方。範例場板110具有平面的、水平的下表面114，其實質地平行於基底12的該表面14。範例場板110延伸超過該閘極結構60，並且直接橫臥在該閘極結構60與該汲極區域64之間的區域上方，或者甚至直接在該汲極區域64上方，以幫助裝置區域22中的該裝置80的該漂移區域34中的電場成形。
如所顯示的，該導電柱120和130直接地接觸並且電性耦接至該場板110的下表面114。單一導電柱或多個導電柱120從該場板110朝向該介電阻擋件90向下延伸。在範例實施例中，該導電柱120終止在遠端122，該遠端122座落在介電阻擋件90的上表面95上，也就是，與介電阻擋件90的上表面95直接接觸。在第4圖中，導電柱130從該場板110朝向該基底12向下延伸， 並且直接地接觸該阱接觸區域66。或者，該導電柱130可如虛線131所指示的設置並且直接地接觸該閘極結構60的閘極電極，或者如虛線132所指示的設置並且直接地接觸源極區域62。在各個案例中，該導電柱130是電性耦接至阱接觸區域66、閘極結構60或源極區域62。
因此，該場效結構100是電性連接至該閘極結構60、源極區域62或阱接觸區域66，以最大化該場效結構100、以及特別是該導電柱120的該遠端122與該裝置80的該汲極區域64之間的電位差異(potential difference)，而最大化場效結構100於電壓施加至該汲極和閘極時，使該源極區域62與該汲極區域64之間所產生的電場成形的能力。
第5圖例示第4圖的該LDMOS裝置80和場效結構100的不同實施例。在第5圖中注意到，該阱區域32如傳統上在特定應用中在漂移區域34下方並且繞著漂移區域34延伸。舉例來說，阱區域32可為高電壓阱區域，而漂移區域34可為高電壓漂移區域。並且，額外高電壓阱區域36可設置得較深且繞著阱區域32。典型地，阱區域36可以第一導電類型(例如，n-類型)摻雜，相對於阱區域32的導電類型。
如第5圖中所顯示的，該場板110從直接地在閘極結構60上方的端點111延伸至直接地在介電阻擋件90上方的端點112。導電柱130接觸與端點111等高的該場板110的下表面114，並且實質地直立地向下延伸以與該閘極結構60接觸。單一導電柱120接觸與端點112等高的該場板110的下表面114，並且實質地直立地向下延伸以與該介電阻擋件90接觸。
第6圖例示第5圖的該LDMOS裝置80和場效結構100的不同實施例。在第6圖中，場板110比第5圖的實施例長。如所顯示的，該場效板延 伸至端點112，該端點112可直接地設在表面絕緣體區域40上方，並且沒有直接地在介電阻擋件90上方。單一導電柱120在與端點112隔開的位置處接觸該場板110的下表面114，使得下表面114的一部分是位在該導電柱120與該端點112之間。如所顯示的，該導電柱120實質地直立地向下延伸以與該介電阻擋件90接觸。
第4至6圖的實施例例示可提供不同的配置，以從場效結構100獲得在漂移區域34中的電場的希望效應。特定其它實施例可結合來自各個實施例的特徵或各種特徵。
在傳統的LDMOS裝置中，崩潰熱點通常發生在靠近閘極結構的汲極側邊緣，在那位置處，電場是高的。如本文中所描述的，可利用導電場效結構100以定位較靠近LDMOS裝置80的汲極區域64的較低電位。具體而言，在該LDMOS電晶體裝置80的運作期間，該場效結構100是經受來自導電柱130與該LDMOS電晶體80之間的接觸的電位。藉由使場效結構100經受特別的電位，可調變形成在閘極結構60與汲極區域64之間的電場。此調變可運作以增加該閘極結構60與汲極區域64之間的崩潰電壓。舉例來說，該場效結構100可有效地迫使通常出現在靠近該閘極結構60的該汲極側邊的高電場更遠離該閘極結構60並且朝向該汲極區域64。以此方式，可增加該LDMOS裝置80的崩潰電壓。
雖然至少一個範例實施例已經出現在先前的實施方式中，但應體會到存在大量的變體。應體會到該範例實施例或本文中所描述的實施例不意圖以任何方式限制該請求的發明標的的範疇、應用或組構。反而是，先前的實施方式將提供本領域的熟習技術者方便的藍圖，以實作該描述的一個或多個實施例。 應了解到，可對元件的功能和配置作出各種改變，而不致於偏離由該申請專利範圍所定義的範疇，其包括已知均等物和此專利申請案提出時的可預見的均等物。
10:積體電路裝置
12:基底
14:上表面、表面
22:第二裝置區域
34:漂移區域
60:閘極結構
62:源極區域
64:汲極區域
66:阱接觸區域
80:LDMOS裝置、LDMOS電晶體、LDMOS電晶體裝置
90:介電阻擋件
95:上表面
99:層間介電質
100:場效結構
110:場板、導電場板
114:下表面
120、130:導電柱、導電結構
122:遠端
131、132:虛線

Claims (20)

  1. 一種橫向擴散金屬氧化物半導體(LDMOS)裝置，包含：基底，具有表面；閘極結構，上覆於該基底的該表面並且包括閘極介電質及位於該閘極介電質上的閘極電極；通道區域，在該基底中在該閘極結構下面；汲極區域，在該基底中；表面絕緣體區域，設置在該基底的該表面處的該閘極結構與該汲極區域之間；介電阻擋件，不同於該表面絕緣體區域並且僅位在該表面絕緣體區域的一部分上方；以及場效結構，包括場板和導電結構，其中，該場板設置在該基底的該表面上方並且遠離該基底的該表面，並且其中，該導電結構耦接至該場板及從該場板朝向該介電阻擋件延伸，其中，該閘極介電質的一部分位於該表面絕緣體區域上，使得該表面絕緣體區域位於該閘極介電質的該部分與該基底的該表面之間。
  2. 如申請專利範圍第1項所述之LDMOS裝置，其中，該導電結構是直接地位在該介電阻擋件上方。
  3. 如申請專利範圍第1項所述之LDMOS裝置，其中，該導電結構實體地接觸該介電阻擋件。
  4. 如申請專利範圍第1項所述之LDMOS裝置，進一步包含：源極區域，在該基底中；以及 漂移區域，在該基底中，其中，該汲極區域是位在該漂移區域中。
  5. 如申請專利範圍第1項所述之LDMOS裝置，進一步包含：源極區域，在該基底中；以及漂移區域，在該基底中，其中，該汲極區域是位在該漂移區域中，並且其中，該導電結構是位在該閘極結構與該汲極區域之間。
  6. 如申請專利範圍第1項所述之LDMOS裝置，進一步包含在該基底中的源極區域，其中，該場板是電性耦接至該源極區域。
  7. 如申請專利範圍第1項所述之LDMOS裝置，進一步包含在該基底中的本體區域，其中，該場板是電性耦接至該本體區域。
  8. 如申請專利範圍第1項所述之LDMOS裝置，其中，該場板是電性耦接至該閘極結構。
  9. 如申請專利範圍第1項所述之LDMOS裝置，其中，該場板從直接地設置在該閘極結構上方的中央部分延伸至直接地在該介電阻擋件上方的邊緣。
  10. 如申請專利範圍第1項所述之LDMOS裝置，其中，該場板從直接地設置在該閘極結構上方的中央部分延伸至直接地在該表面絕緣體區域上方的邊緣，並且其中，該導電結構是耦接至該場板的該邊緣。
  11. 如申請專利範圍第1項所述之LDMOS裝置，其中，該場板從直接地設置在該閘極結構上方的中央部分延伸至直接地在該表面絕緣體區域上方的邊緣，並且其中，該導電結構是在該中央部分與該邊緣之間處耦接至該場板。
  12. 一種積體電路裝置，包含：基底，具有表面； 第一橫向擴散金屬氧化物半導體(LDMOS)裝置，其中，該第一LDMOS裝置包含：第一源極區域和第一汲極區域，在該基底中；第一閘極結構，在該基底上方並且在該第一源極區域與該第一汲極區域之間；以及第一表面絕緣體區域，設置在該第一閘極結構與該第一汲極區域之間的該基底的該表面處，其中，該第一表面絕緣體區域具有第一厚度和第一寬度；第二LDMOS裝置，其中，該第二LDMOS裝置包含：第二源極區域和第二汲極區域，在該基底中；第二閘極結構，在該基底上方並且在該第二源極區域與該第二汲極區域之間；第二表面絕緣體區域，設置在該第二閘極結構與該第二汲極區域之間的該基底的該表面處，其中，該第二表面絕緣體具有等於該第一厚度的第二厚度及大於該第一寬度的第二寬度；以及介電阻擋件，在該第二表面絕緣體區域上方；以及場效結構，組構成增加該第二LDMOS裝置的崩潰電壓，其中，該場效結構包含：場板，設置在該第二LDMOS裝置上方並且遠離該基底的該表面；以及導電結構，耦接至該場板並且從該場板朝向該介電阻擋件延伸。
  13. 如申請專利範圍第12項所述之積體電路裝置，其中，該場效結構的該導電結構實體地接觸該介電阻擋件。
  14. 如申請專利範圍第12項所述之積體電路裝置，其中，該導電結構是位在該第二閘極結構與該第二汲極區域之間。
  15. 如申請專利範圍第12項所述之積體電路裝置，其中，該場板是電性耦接至該第二源極區域。
  16. 如申請專利範圍第12項所述之積體電路裝置，進一步包含在該基底中的本體區域，其中，該場板是電性耦接至該本體區域。
  17. 如申請專利範圍第12項所述之積體電路裝置，其中，該場板是電性耦接至該第二閘極結構。
  18. 一種製造積體電路裝置的方法，該方法包含：形成隔離區域在具有表面的基底中，以定義第一裝置區域和第二裝置區域；實施氧化程序，以形成第一表面絕緣體區域在該第一裝置區域中和第二隔離區域在該第二裝置區域中；沉積閘極材料在該基底上方；圖案化該閘極材料，以形成第一閘極結構在該第一裝置區域中和第二閘極結構在該第二裝置區域中；形成介電阻擋件在第二表面絕緣體區域上方；形成場效結構在第二LDMOS裝置上方，其中，該場效結構包括在該介電阻擋件上的導電結構。
  19. 如申請專利範圍第18項所述之方法，其中，第一表面絕緣體區域具有第一厚度，而該第二表面絕緣體區域具有等於該第一厚度的第二厚度。
  20. 如申請專利範圍第18項所述之方法，其中，第一表面絕緣體區域具有第一厚度和第一寬度，而該第二表面絕緣體區域具有等於該第一厚度的第二厚度和大於該第一寬度的第二寬度。
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