TW201503366A - 溝渠式功率半導體元件及其製作方法 - Google Patents
溝渠式功率半導體元件及其製作方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 32
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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Abstract
一種溝渠式功率電晶體元件,包含有一半導體基底;一磊晶層,設於該半導體基底上;至少一閘極溝槽,設於該磊晶層中;一閘極氧化層,位於該閘極溝槽內;一閘極,位於該閘極溝槽中,該閘極突出於該磊晶層,且該閘極上具有一凹陷結構;一間隙壁,位於該閘極的一側壁上;一金屬頂部結構,位於該凹陷結構內;一接觸插塞,位於該間隙壁的一側,延伸進入到該磊晶層中,其中該間隙壁隔離該金屬頂部結構與該接觸插塞;以及一源極摻雜區,於該磊晶層中,介於該接觸插塞與該閘極溝槽之間。
Description
本發明係有關於半導體元件技術領域,特別是有關於一種溝渠式功率半導體元件的製作方法。
在傳統功率電晶體中,平面型功率元件(DMOS)因來自於通道區域(channel region)、聚集層(accumulation layer)以及接面場效電晶體(JFET)的貢獻,而使得導通電阻(on-resistance)上升。
為了降低上述區域之電阻,溝渠式功率電晶體元件(UMOS)於是被提出來,更因為UMOS結構不存在JFET區域,因此可以縮小UMOS元件尺寸(cell size)以提高通道密度(channel density),可以進一步降低導通電阻。
但隨著縮小元件的尺寸,閘極與源極接觸窗(contact)之間隔也隨之縮小,導致製程上對準(overlay)的問題。
本發明之目的,即在於提供一種功率半導體元件之製作方法,利用間隙壁來形成自我對準之接觸窗,使得能夠在縮小元件尺寸時,同時能避免閘極溝槽(gate trench)與接觸窗(contact)對準的問題。
根據本發明一實施例,本發明提供一種溝渠式功率電晶體元件,包含有一半導體基底,具有一第一導電型;一磊晶層,設於該半導體基底上;至少一閘極溝槽,設於該磊晶層中;一閘極氧化層,位於該閘極溝槽內;一閘極,位於該閘極溝槽中,該閘極突出於該磊晶層,且該閘極上具有一凹陷結構;一間隙壁,位於該閘極的一側壁上;一金屬頂部結構,位於該凹陷結
構內;一接觸插塞,位於該間隙壁的一側,延伸進入到該磊晶層中,其中該間隙壁隔離該金屬頂部結構與該接觸插塞;以及一源極摻雜區,於該磊晶層中,介於該接觸插塞與該閘極溝槽之間,該源極摻雜區具有該第一導電型。
根據本發明另一實施例,本發明提供一種溝渠式功率電晶體元件的製作方法,包含有:提供一第一導電型之半導體基底;於該半導體基底上形成一磊晶層;於該磊晶層中形成至少一閘極溝槽;於該閘極溝槽內形成一閘極氧化層;於該閘極溝槽中形成一閘極,該閘極突出於該磊晶層的上表面;進行一離子佈植製程,於該磊晶層中形成一源極摻雜區;於該閘極的側壁形成一間隙壁;以該間隙壁作為蝕刻遮罩,自我對準蝕刻該源極摻雜區,俾形成一接觸洞;以及於該接觸洞內形成一接觸插塞,並於該閘極上形成一金屬頂部結構,其中該接觸插塞與該金屬頂部結構被該間隙壁分離。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。
10‧‧‧半導體基底
11‧‧‧磊晶層
12‧‧‧硬遮罩層
18‧‧‧閘極氧化層
19‧‧‧氧化層
20a‧‧‧溝渠閘極
20b‧‧‧凹陷結構
22‧‧‧源極摻雜區
24‧‧‧間隙壁
24a‧‧‧開口
24b‧‧‧突出結構
32‧‧‧阻障層
34‧‧‧金屬層
112‧‧‧開口
122‧‧‧閘極溝槽
122a‧‧‧閘極溝槽
123‧‧‧凹陷區域
134‧‧‧金屬頂部結構
140‧‧‧介電層
210‧‧‧離子井
230‧‧‧接觸洞
234‧‧‧接觸插塞
250‧‧‧接觸摻雜區
342‧‧‧凹陷結構
380‧‧‧側壁摻雜區
432‧‧‧阻障層
434‧‧‧金屬層
第1圖至第13圖為依據本發明一實施例所繪示的溝渠式功率電晶體元件之製造方法示意圖。
第14圖至第17圖繪示本發明另一實施例。
第18圖至第20圖例示不同的接觸洞與溝渠閘極的佈局。
請參閱第1圖至第13圖,其為依據本發明一實施例所繪示的溝渠式功率電晶體元件之製造方法示意圖。首先,如第1圖所示,提供一半導體基底10,例如N型重摻雜之矽基底,其可作為電晶體元件的汲極(drain)。接著,利用一磊晶製程於半導體基底10上形成一磊晶層11,例如N型磊晶矽層。接著,可以在磊晶層11表面形成一硬遮罩層12,例如,氧化矽或者氮
化矽。
然後,如第2圖所示,利用光阻以及微影、蝕刻等製程,於硬遮罩層12中形成開口112。接著將光阻去除,然後,利用乾蝕刻製程,經由硬遮罩層12中的開口112,蝕刻磊晶層11至一預定深度,如此形成閘極溝槽122。根據本發明實施例,閘極溝槽122的寬度小於0.3微米,而閘極溝槽122之間的間隔小於0.5微米。
如第3圖所示,繼續進行一氧化製程,於閘極溝槽122表面形成一犧牲氧化層(圖未示),再以蝕刻將犧牲氧化層及部分的硬遮罩層12去除,留下閘極溝槽122a。
如第4圖所示,接著進行一熱氧化製程,於閘極溝槽122a的表面形成一閘極氧化層18,接下來,進行一化學氣相沈積製程,全面沈積一多晶矽層(圖未示),填滿閘極溝槽122,再進行一蝕刻或研磨製程,將部分厚度的多晶矽層蝕除,而剩下的多晶矽層則構成溝渠閘極20a。
如第5圖所示,接著將硬遮罩層12完全去除,顯露出部分的溝渠閘極20a的側壁。然後,進行一氧化製程,在顯露出的溝渠閘極20a的側壁上及上表面,形成一氧化層19。
如第6圖所示,進行一離子佈植製程,於磊晶層11的溝渠閘極20a之間形成至少一摻雜區,再進行熱驅入製程,例如900至1200℃,針對摻雜區310進行摻質的驅入及擴散,俾形成離子井210。
如第7圖所示,接著再進行一離子佈植製程,於磊晶層11中形成緊鄰閘極溝槽122a的源極摻雜區22,例如,N+源極摻雜區。然後可以進行熱驅入製程,進行摻質的驅入及擴散。上述離子佈植製程可以配合微影製程進行,先以光阻圖案定義出待佈植的源極區域,再進行離子佈植製程。
如第8圖所示,接著全面沈積一間隙壁材料層(圖未示),例如,氮化矽,其厚度小於0.2微米。然後進行乾蝕刻製程,於溝渠閘極20a的側壁上形成間隙壁24。相鄰的間隙壁24,於溝渠閘極20a之間的源極摻雜區22
上構成一開口24a,顯露出部分的源極摻雜區22。開口24a的大小可以藉由間隙壁24的橫向厚度來決定。
如第9圖所示,進行一乾蝕刻製程,經由間隙壁24之間的開口24a蝕刻磊晶層11,自我對準形成一接觸洞230。由於是自我對準產生接觸洞,因此可以避免黃光製程的對準誤差。其中,接觸洞230的深度可以大於或等於源極摻雜區22的接面深度。此外,在蝕刻接觸洞230的同時,同時也會蝕刻溝渠閘極20a,故最後會在溝渠閘極20a上形成一凹陷結構20b。
接觸洞230與溝渠閘極20a的佈局,如第18圖所示,可以是彼此平行的線條圖案,或者如第19圖所示,可以是溝渠閘極20a環繞接觸洞230的圖案,或者是如第20圖所示,接觸洞230成格柵圖案,區隔溝渠閘極20a。當然,上述佈局僅為例示,本發明不限於此。
如第10圖所示,隨後進行一斜角度離子佈植,將P型摻質植入在靠近閘極溝槽122a的磊晶層11中,形成側壁摻雜區380。然後,進行接觸洞離子佈植製程,於接觸洞230底部形成接觸摻雜區250。隨後可以再進行快速熱退火處理。
如第11圖所示,然後沈積阻障層32及金屬層34,並使金屬層34填滿接觸洞230。阻障層32可以包含鈦或氮化鈦。金屬層34可以包含鎢。接著,進行研磨或蝕刻製程,去除部分厚度的阻障層32及金屬層34,如此在凹陷結構20b形成一金屬頂部結構134,包含阻障層32及金屬層34,其與位於間隙壁24另一惻的接觸插塞234彼此分離。從第11圖中可看出間隙壁24的頂端突出於金屬層34的上表面,構成一突出結構24b。金屬頂部結構134可以幫助降低閘極的電阻值。
如第12圖所示,接著進行化學氣相沈積製程,全面沈積一介電層140,使介電層140覆蓋金屬層34以及突出結構24b,然後進行微影製程,先於介電層140上形成一光阻圖案(圖未示),定義出接觸洞的位置,再利用光阻圖案為蝕刻遮罩,蝕刻介電層140至一預定深度,直到顯露出部分的接觸
插塞234,形成介層洞240。然後去除光阻圖案。
如第13圖所示,最後全面沈積一阻障層432及金屬層434,並使金屬層434填滿介層洞240,形成內連結。
第14圖至第17圖繪示本發明另一實施例,其中第14圖接續第10圖的步驟,故前面的步驟相同,不再贅述。如第14圖所示,沈積阻障層32及金屬層34,並使金屬層34填滿接觸洞230以及溝渠閘極20a上的凹陷結構20b。
如第15圖,接著進行微影及蝕刻製程,將溝渠閘極20a上的部分阻障層32及金屬層34蝕除,並蝕刻掉部分的間隙壁24,如此分離出金屬頂部結構134以及接觸插塞234。此時,在溝渠閘極20a上的金屬層34中形成一凹陷結構342。
如第16圖所示,再沈積一介電層140,使介電層140覆蓋金屬層34,並填滿凹陷結構342。然後進行一研磨製程,例如,化學機械研磨,去除掉金屬層34上的介電層140,僅留下位於凹陷結構342的介電層140,構成一全面平坦的表面。
最後,如第17圖所示,全面沈積一阻障層432及金屬層434,與接觸插塞234形成內連結。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10‧‧‧半導體基底
11‧‧‧磊晶層
18‧‧‧閘極氧化層
19‧‧‧氧化層
20a‧‧‧溝渠閘極
22‧‧‧源極摻雜區
24‧‧‧間隙壁
24b‧‧‧突出結構
32‧‧‧阻障層
34‧‧‧金屬層
122a‧‧‧閘極溝槽
134‧‧‧金屬頂部結構
140‧‧‧介電層
210‧‧‧離子井
230‧‧‧接觸洞
234‧‧‧接觸插塞
250‧‧‧接觸摻雜區
380‧‧‧側壁摻雜區
432‧‧‧阻障層
434‧‧‧金屬層
Claims (11)
- 一種溝渠式功率電晶體元件,包含有:一半導體基底,具有一第一導電型;一磊晶層,設於該半導體基底上;至少一閘極溝槽,設於該磊晶層中;一閘極氧化層,位於該閘極溝槽內;一閘極,位於該閘極溝槽中,該閘極突出於該磊晶層,且該閘極上具有一凹陷結構;一間隙壁,位於該閘極的一側壁上;一金屬頂部結構,位於該凹陷結構內;一接觸插塞,位於該間隙壁的一側,延伸進入到該磊晶層中,其中該間隙壁隔離該金屬頂部結構與該接觸插塞;以及一源極摻雜區,於該磊晶層中,介於該接觸插塞與該閘極溝槽之間,該源極摻雜區具有該第一導電型。
- 如申請專利範圍第1項所述之溝渠式功率電晶體元件,其中該半導體基底係作為該溝渠式功率電晶體元件的一汲極。
- 如申請專利範圍第1項所述之溝渠式功率電晶體元件,其中該接觸插塞與該閘極溝槽之間另包含有一離子井,具有一第二導電型。
- 如申請專利範圍第3項所述之溝渠式功率電晶體元件,其中該第一導電型為N型,該第二導電型為P型。
- 如申請專利範圍第1項所述之溝渠式功率電晶體元件,其中該出間隙壁的頂端突出於該金屬頂部結構的上表面,構成一突出結構。
- 如申請專利範圍第1項所述之溝渠式功率電晶體元件,其中另包含:一介電層,覆蓋該金屬頂部結構的上表面以及該間隙壁;以及至少一金屬層,覆蓋在該介電層上,並電連結該接觸插塞。
- 一種溝渠式功率電晶體元件的製作方法,包含有:提供一第一導電型之半導體基底;於該半導體基底上形成一磊晶層;於該磊晶層中形成複數個閘極溝槽;於各該閘極溝槽內形成一閘極氧化層;於各該閘極溝槽中形成一閘極,該閘極突出於該磊晶層的上表面;於該磊晶層中形成一源極摻雜區,具有該第一導電型;於該閘極的側壁形成一間隙壁;以該間隙壁作為蝕刻遮罩,自我對準蝕刻該源極摻雜區,俾形成一接觸洞;以及於該接觸洞內形成一接觸插塞,並於該閘極上形成一金屬頂部結構,其中該接觸插塞與該金屬頂部結構被該間隙壁分離。
- 如申請專利範圍第7項所述之溝渠式功率電晶體元件的製作方法,其中形成該接觸插塞之後,另包含:全面沈積一介電層,覆蓋該接觸插塞與該金屬頂部結構;蝕刻該介電層,俾形成一介層洞,顯露出部分的該接觸插塞;以及全面沈積一金屬層,經由該介層洞與該接觸插塞電連結。
- 如申請專利範圍第7項所述之溝渠式功率電晶體元件的製作方法,其中於該磊晶層中形成該源極摻雜區之前,另包含: 於該閘極溝槽之間的該磊晶層中形成一離子井,其具有一第二導電型。
- 如申請專利範圍第9項所述之溝渠式功率電晶體元件的製作方法,其中該第一導電型為N型,該第二導電型為P型。
- 如申請專利範圍第7項所述之溝渠式功率電晶體元件,其中該半導體基底係作為該溝渠式功率電晶體元件的一汲極。
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TWI836689B (zh) * | 2022-11-01 | 2024-03-21 | 世界先進積體電路股份有限公司 | 半導體裝置及其形成方法 |
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TWI836689B (zh) * | 2022-11-01 | 2024-03-21 | 世界先進積體電路股份有限公司 | 半導體裝置及其形成方法 |
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