TW201943081A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201943081A
TW201943081A TW108107520A TW108107520A TW201943081A TW 201943081 A TW201943081 A TW 201943081A TW 108107520 A TW108107520 A TW 108107520A TW 108107520 A TW108107520 A TW 108107520A TW 201943081 A TW201943081 A TW 201943081A
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Taiwan
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trench
substrate
source region
conductivity type
electrode
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TW108107520A
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English (en)
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大須賀祐喜
原田博文
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日商艾普凌科有限公司
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Publication of TW201943081A publication Critical patent/TW201943081A/zh

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Abstract

構成源極區域19的濃度比第一源極區域部16低的第二源極區域部14包含第一部分141與第二部分142來構成，所述第一部分141具有自第一源極區域部16的底面至比作為閘電極的上表面的第一高度H1高的第二高度H2為止的深度，所述第二部分142的上表面接觸第一部分141的底面的一部分，與作為溝槽20的延伸方向的第一方向垂直的第二方向上的一側的側面接觸溝槽20的外側面，第二方向上的另一側的側面、第一方向上的兩側面、及底面接觸基極層13，且具有自第一部分141的底面至少至第一高度H1為止的深度。

Description

半導體裝置及其製造方法
本發明是有關於一種半導體裝置及其製造方法，且特別是有關於一種具有縱型金屬氧化物半導體場效應電晶體（Metal Oxide Semiconductor Field Effect Transistor，MOSFET）的半導體裝置及其製造方法。
使用圖18（a）及圖18（b）對先前的具有縱型MOSFET的半導體裝置進行說明（例如，參照專利文獻1）。
圖18（a）是先前的半導體裝置900的平面圖，圖18（b）是沿著圖18（a）的a-a'線的剖面圖。
如圖18（a）及圖18（b）所示，具有縱型MOSFET的半導體裝置900包括：包含N型高濃度半導體基板911與N型半導體層912的汲極區域918、P型通道層（亦稱為基極層）913、包含高濃度的N型源極區域916與以包圍其的方式設置的低濃度的N型源極區域914的源極區域919、P型後閘極區域（亦稱為基極接觸區域）917、溝槽920、閘極絕緣膜921、及閘電極922。
閘電極922自溝槽920中突出，由層間絕緣膜923覆蓋，源電極931經由開在層間絕緣膜923上的接觸孔而與高濃度源極區域916電性連接。
如圖18（a）所示，溝槽920於一方向上延伸，呈條紋狀地設置有多個，於鄰接的溝槽920之間，包含高濃度的N型源極區域916與包圍其的低濃度的N型源極區域914的源極區域919以規定的間隔配置於溝槽920的延伸方向上，於鄰接的源極區域919之間，經由基極層913而配置有基極接觸區域917。
再者，雖然未圖示，但經由與開在層間絕緣膜923上的所述接觸孔不同的接觸孔，將與基極接觸區域917電性連接的基電極與源電極931平行地設置於同一層上。
如此，將源電極931與基電極分開設置，藉此基極層913可取得與源電極931不同的電位。即，藉由對將基電極與源電極931設為同電位（接地）的情況與將基電極與汲電極933設為同電位（接地）的情況進行切換，可將一個縱型MOSFET用作雙向開關元件。此時，藉由低濃度源極區域914來包圍高濃度源極區域916，另外，使源極區域919與基極接觸區域917分離，藉此可去除高濃度的PN接合面，因此即便於對源電極931施加了高電壓的情況（將基電極與汲電極933設為接地的情況）下，亦可充分地確保源極區域919-基極層913間的耐壓。
[現有技術文獻]
[專利文獻]
[專利文獻1]日本專利特開2009-170532號公報
[發明所欲解決之課題]
但是，於所述先前的具有縱型MOSFET的半導體裝置900中，當在源極區域919-基極層913間需要更高的耐壓時，為了藉由低濃度的源極區域914來確保所述耐壓，必須使低濃度的源極區域914的深度變得更深。於此情況下，低濃度的源極區域914不僅於深度方向上擴大，亦於與基板平行的方向，即溝槽920延伸的方向上擴大。因此，為了不接觸鄰接的基極接觸區域917，必須將源極區域919與基極接觸區域917的間隔保持得大，因此必須使晶片面積變大，而難以微細化。
因此，本發明的目的在於提供一種可不使晶片面積變大，而提昇縱型MOSFET的源極區域-基極層間的耐壓的半導體裝置及其製造方法。
[解決課題之手段]
本發明的半導體裝置包括：基板；第一導電型的汲極區域，具有規定的厚度，設置於所述基板的背面側；溝槽，以自所述基板的表面到達所述汲極區域的上表面，並於第一方向上延伸的方式設置；第二導電型的基極層，鄰接於所述溝槽，並設置於所述汲極區域上；閘極絕緣膜，覆蓋所述溝槽的內側的底面及側面；閘電極，於所述溝槽內經由所述閘極絕緣膜而自所述溝槽的底面埋入至第一高度為止；層間絕緣膜，於所述溝槽內自所述第一高度埋入至所述基板的表面為止；以及源極區域，設置於所述基板的表面上，包含與所述第一方向垂直的第二方向上的側面接觸所述溝槽的外側面，於所述第一方向上具有第一長度來設置的第一導電型的第一源極區域部，及濃度比所述第一源極區域部低的第一導電型的第二源極區域部。所述第二源極區域部包含：第一部分，上表面接觸所述第一源極區域部的底面，所述第二方向上的側面接觸所述溝槽的外側面，於所述第一方向上具有比所述第一長度長的第二長度，且具有自所述第一源極區域部的底面至比所述第一高度高的第二高度為止的深度；第二部分，上表面接觸所述第一部分的底面的一部分，所述第二方向上的一側的側面接觸所述溝槽的外側面，所述第二方向上的另一側的側面、所述第一方向上的兩側面、及底面接觸所述基極層，於所述第一方向上具有所述第二長度，且具有至少至所述第一高度為止的深度；以及第三部分，設置於所述基板的表面上，所述第一方向上的一側的側面接觸所述第一源極區域部，所述第一方向上的另一側的側面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，底面接觸所述第一部分的上表面的一部分。進而，本發明的半導體裝置的特徵在於包括：第二導電型的基極接觸區域，設置於所述基板的表面上，所述第一方向上的兩側面及底面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，濃度比於所述第一方向上與所述源極區域並列設置的所述基極層高；源電極，於所述基板上，以與所述源極區域電性連接，並於所述第二方向上延伸的方式設置；基電極，於所述基板上，以與所述基極接觸區域電性連接，與所述源電極電性絕緣，並於所述第二方向上延伸的方式設置；以及汲電極，設置於所述基板的背面上，並與所述汲極區域電性連接。
另外，本發明的半導體裝置的製造方法包括：自第一導電型的基板的表面至規定的深度形成具有規定的厚度的第二導電型的基極層，並使所述基板的比所述基極層更深的剩餘的區域作為第一導電型的汲極區域而殘存的步驟；形成以自所述基板的表面到達所述汲極區域的方式於第一方向上延伸的溝槽的步驟；於所述溝槽的內側的底面及側面上形成閘極絕緣膜的步驟；將閘電極材料經由所述閘極絕緣膜而埋入所述溝槽內的步驟；對所述閘電極材料的上部進行蝕刻，藉此形成自所述溝槽的底面埋入至第一高度為止的閘電極的步驟；自所述基板的表面及比所述溝槽的所述第一高度更上方的內側面朝規定的區域中選擇性地注入第一導電型的雜質，藉此形成第一導電型的雜質區域的步驟；於所述溝槽內自所述第一高度至所述基板的表面為止埋入層間絕緣膜的步驟；於所述基板的表面上形成第一導電型的第一源極區域部、及濃度比所述第一源極區域部低的第一導電型的第二源極區域部的步驟。所述第一源極區域部藉由自所述基板的表面朝所述第一導電型的雜質區域內選擇性地注入第一導電型的雜質而形成，與所述第一方向垂直的第二方向上的側面接觸所述溝槽的外側面，並於所述第一方向上具有第一長度，並且所述第二源極區域部包含：第一部分，上表面接觸所述第一源極區域部的底面，所述第二方向上的側面接觸所述溝槽的外側面，於所述第一方向上具有比所述第一長度長的第二長度，且具有自所述第一源極區域部的底面至比所述第一高度高的第二高度為止的深度；第二部分，上表面接觸所述第一部分的底面的一部分，所述第二方向上的一側的側面接觸所述溝槽的外側面，所述第二方向上的另一側的側面、所述第一方向上的兩側面、及底面接觸所述基極層，於所述第一方向上具有所述第二長度，且具有至少至所述第一高度為止的深度；以及第三部分，設置於所述基板的表面上，所述第一方向上的一側的側面接觸所述第一源極區域部，所述第一方向上的另一側的側面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，底面接觸所述第一部分的上表面的一部分。進而，本發明的半導體裝置的製造方法的特徵在於包括：自所述基板的表面朝於所述第一方向上與所述源極區域鄰接的區域中選擇性地注入第二導電型的雜質，藉此於所述基板的表面上形成所述第一方向上的兩側面及底面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，且濃度比所述基極層高的第二導電型的基極接觸區域的步驟；於所述基板上形成電極膜，並對該電極膜進行圖案化，藉此形成與所述源極區域電性連接，並於所述第二方向上延伸的源電極，及與所述基極接觸區域電性連接，並於所述第二方向上延伸的基電極的步驟；以及於所述基板的背面上形成與所述汲極區域電性連接的汲電極的步驟。
[發明的效果]
根據本發明，如上所述，構成源極區域的第一源極區域部及第二源極區域部之中，濃度比第一源極區域部低的第二源極區域部包含第一部分第二部分來構成，所述第一部分具有自第一源極區域部的底面至比作為閘電極的上表面的第一高度高的第二高度為止的深度，所述第二部分的上表面接觸第一部分的底面的一部分，與作為溝槽的延伸方向的第一方向垂直的第二方向上的一側的側面接觸溝槽的外側面，第二方向上的另一側的側面、第一方向上的兩側面、及底面接觸基極層，且具有自第一部分的底面至少至作為閘電極的上表面的第一高度為止的深度。藉此，於第二源極區域部的第二部分中，空乏層不僅自其底面與基極層的PN接合部擴大，空乏層亦自其側面與基極層的PN接合部擴大，因此可藉由所謂的降低表面電場（REduced SURface Field，RESURF）效應，使該第二部分完全地空乏化。因此，可不使晶片面積變大，而提昇縱型MOSFET的源極區域與基極層之間的耐壓。
以下，一面參照圖式一面對本發明的實施方式進行詳細說明。
圖1是用於說明本發明的第一實施方式的具有縱型MOSFET的半導體裝置100的平面圖，圖2是沿著圖1的a-a'線的剖面圖，圖3是沿著圖1的b-b'線的剖面圖，圖4是沿著圖1的c-c'線的剖面圖，圖5是沿著圖1的d-d'線的剖面圖。再者，圖1中所示的平面圖於後述的第二實施方式的半導體裝置200中亦通用。
如圖2及圖3所示，半導體裝置100包括N型（第一導電型）的半導體基板10、及設置於半導體基板10上的磊晶層11。再者，以下亦將半導體基板10與磊晶層11合稱為基板1。
於基板1內設置有包含半導體基板10與設置於其上的N型的半導體層12的汲極區域18、設置於汲極區域18上的P型（第二導電型）的基極層13、及自基板1（磊晶層11）的表面貫穿基極層13而到達汲極區域18的上表面的溝槽20。於圖2及圖3中，將溝槽20在相對於紙面垂直的方向上設置成條紋狀（參照圖1）。
於溝槽20的內部，以覆蓋溝槽20的底面及側面的方式形成閘極絕緣膜21，經由閘極絕緣膜21而自溝槽20的底面至高度H1為止埋入閘電極22，於閘電極22上的溝槽20的剩餘的部分中埋入層間絕緣膜23直至基板1的表面為止。
於基板1的表面的鄰接於溝槽20的區域中，如圖1、圖4、及圖5所示，設置有在溝槽20的延伸方向（Y方向）上具有長度L1的N型的源極區域部16。另外，以覆蓋Y方向上的源極區域部16的兩側面、及底面的方式，設置有濃度比源極區域部16低的N型的源極區域部14。藉由該些源極區域部16及源極區域部14來構成源極區域19。
如圖1、圖2、圖4、及圖5所示，源極區域部14具有第一部分141 、第二部分142 、及第三部分143 來構成。詳細而言，第一部分141 的上表面接觸源極區域部16的底面，與溝槽20的延伸方向垂直的方向（X方向）上的側面接觸溝槽20的外側面，於Y方向上具有比長度L1長的長度L2，且具有自源極區域部16的底面至比高度H1高的高度H2為止的深度。第二部分142 的上表面接觸第一部分141 的底面的一部分，X方向上的一側的側面接觸溝槽20的外側面，X方向上的另一側的側面、Y方向上的兩側面、及底面接觸基極層13，於Y方向上具有與第一部分141 的相同的長度L2，且具有至少至高度H1為止的深度。第三部分143 設置於基板1的表面上，Y方向上的一側的側面接觸源極區域部16，Y方向上的另一側的側面接觸基極層13，X方向上的兩側面接觸溝槽20的外側面，底面接觸第一部分141 的上表面的一部分。
於基板1的表面上，進而如圖1、圖3、圖4、及圖5所示，以與源極區域19分離的方式設置有P型的基極接觸區域17，所述P型的基極接觸區域17的Y方向上的兩側面及底面接觸基極層13，X方向上的側面接觸溝槽20的外側面，濃度比於Y方向上與源極區域19並列設置的基極層13高。
如圖2、圖4、及圖5所示，於基板1上，以與源極區域19電性連接，並於X方向上延伸的方式設置源電極31。另外，如圖3、圖4、及圖5所示，於基板1上，以與基極接觸區域17電性連接，並於X方向上延伸的方式，即與源電極31平行地設置有基電極32。再者，源電極31與基電極32藉由絕緣膜（未圖示）而電性絕緣。
另外，如圖2～圖5所示，於基板1的背面上設置有與汲極區域18電性連接的汲電極33。
如上所述，於本實施方式中，變成如下的結構（RESURF結構）：源極區域19包括源極區域部16與濃度比其低的源極區域部14，該低濃度的源極區域部14包含第一部分141 與第二部分142 ，所述第一部分141 具有自源極區域部16的底面至比作為閘電極22的上表面的高度的高度H1高的高度H2為止的深度，所述第二部分142 的上表面接觸第一部分141 的底面的一部分，與溝槽20的延伸方向（Y方向）垂直的X方向上的一側的側面接觸溝槽20的外側面，X方向上的另一側的側面、Y方向上的兩側面、及底面接觸基極層13，具有自第一部分141 的底面至少至高度H1為止的深度。藉由所述結構，於源極區域部14的第二部分142 中，空乏層不僅自其底面與基極層13的PN接合部擴大，空乏層亦自其側面與基極層13的PN接合部擴大，藉由RESURF效應，該第二部分142 完全地空乏化，因此源極區域19-基極層13間的電場得到緩和。因此，可不使晶片面積變大，而提昇縱型MOSFET的源極區域19-基極層13間耐壓，可將該縱型MOSFET用作高耐壓的雙向開關元件。
繼而，使用圖1及圖6對本發明的第二實施方式的具有縱型MOSFET的半導體裝置200進行說明。圖6是沿著圖1的a-a'線的剖面圖。
第二實施方式的半導體裝置200的汲極區域18的結構與第一實施方式的半導體裝置100不同。其他方面與半導體裝置100相同，因此對相同的構成元件標註相同的符號，並適宜省略重覆的說明。
第二實施方式的半導體裝置200中的汲極區域18除半導體基板10及半導體層12以外，進而具有汲極區域部15來構成，所述汲極區域部15是於溝槽20的底部的外側面，以橫跨半導體層12與基極層13的方式設置，且為N型，即側面接觸溝槽20的外側面，上側的面接觸基極層13，下側的面與半導體層12連接，濃度比半導體層12高，且濃度與源極區域部14相等。再者，此處，為了防止耐壓的下降，較佳為溝槽20的底面接觸半導體層12。
如此，根據本實施方式，於自源電極31到達汲電極33的電流路徑中設置濃度比半導體層12高的汲極區域部15，藉此與第一實施方式的半導體裝置100中的縱型MOSFET相比，可減少縱型MOSFET的導通電阻。
此處，假設於將濃度比半導體層12高的N型的層而非汲極區域部15作為汲極區域18的一部分，設置於半導體層12的上層的情況下，雖然導通電阻減少，但汲極區域18-基極層13間的耐壓下降。相對於此，於本實施方式中，將濃度比半導體層12高的汲極區域部15設為如所述般的結構，藉此於汲極區域18中，汲極區域部15與源極區域19中的源極區域部14的第二部分142 同等地發揮功能。即，藉由RESURF效應，汲極區域18-基極層13間的電場得到緩和。因此，根據本實施方式，可不使汲極區域18-基極層13間耐壓下降，而減少導通電阻。
繼而，使用圖7～圖17中所示的步驟剖面圖對本實施方式的半導體裝置200的製造方法的一例進行說明。
如圖7所示，於高濃度地摻雜有N型的雜質的半導體基板10上，藉由磊晶成長來形成摻雜有N型的雜質的磊晶層11。藉此，形成包含高濃度半導體基板10與磊晶層11的基板1。
其後，以高能量自磊晶層11（基板1）的表面摻雜P型的雜質，藉此如圖8所示，於磊晶層11的深的位置上形成P型雜質區域130 。
繼而，藉由化學氣相沈積（Chemical Vapor Deposition，CVD）法等而於基板1表面上形成絕緣膜24後，藉由光微影而於形成有溝槽20的區域上形成具有開口的光阻劑圖案（未圖示），將該光阻劑圖案作為遮罩對絕緣膜24進行圖案化，如圖9所示，於絕緣膜24的形成溝槽20的區域上形成開口。其後，將絕緣膜24作為遮罩對磊晶層11進行蝕刻，藉此如圖10所示，形成貫穿P型雜質區域130 的溝槽20。
繼而，如圖11所示，將絕緣膜24作為遮罩，於溝槽20的底部摻雜N型的雜質，藉此形成N型雜質區域150 。
其後，進行熱處理，藉此如圖12所示，使雜質區域130 的P型雜質擴散至基板1的表面為止，並且使雜質區域150 的N型雜質以覆蓋溝槽的底部側面的方式擴散，而形成自基板1的表面起覆蓋N型雜質區域150 的上側的至少一部分的深度的基極層13。藉此，於磊晶層11的底部殘存N型的半導體層12。
繼而，如圖13所示，將絕緣膜24作為遮罩，將溝槽20的底面進一步向下挖，而將殘存於溝槽20的底面下的N型雜質區域150 蝕刻去除。藉此，形成接觸溝槽20的外側面，上側的面接觸基極層13，下側的面與半導體層12連接且濃度比半導體層12高的N型的汲極區域部15。
繼而，將絕緣膜24去除後，例如藉由熱氧化而於溝槽20的包含底面及側面的整個面上形成閘極絕緣膜21。此時，於基板1的上表面上，與閘極絕緣膜21同時形成絕緣膜25。
繼而，將閘電極材料埋入溝槽20內後，如圖14所示，回蝕至高度H1為止，而形成閘電極22。
繼而，如圖15所示，於形成覆蓋除形成源極區域部14的區域以外的區域的光阻劑圖案（未圖示）的狀態下，經由閘極絕緣膜21及絕緣膜25，朝溝槽20的包含內側面的整個面上傾斜離子注入N型的雜質。藉此，沿著基板1的表面及溝槽20的側面選擇性地形成N型雜質區域140 。此時，N型雜質區域140 的下端形成得與作為閘電極22的上表面的高度H1相等或比高度H1略深。即，N型雜質區域140 相對於閘電極自我對準地形成。
繼而，如圖16所示，將絕緣膜埋入溝槽20內的閘電極22上的剩餘的部分中，並進行回蝕，藉此形成層間絕緣膜23。
其後，如圖17所示，於形成覆蓋除形成源極區域部16的區域以外的區域的光阻劑圖案（未圖示）的狀態下，自基板1的表面經由絕緣膜25而朝N型雜質區域140 內離子注入N型的雜質。藉此，選擇性地形成源極區域部16，並且N型雜質區域140 的剩餘的部分變成源極區域部14。如此，形成包含源極區域部14及源極區域部16的源極區域19。
繼而，於形成覆蓋除形成有基極接觸區域17的區域以外的區域的光阻劑圖案（未圖示）的狀態下，自基板1的表面經由絕緣膜25而摻雜P型的雜質，藉此如圖1所示，於基板1的表面上形成基極接觸區域17。
其後，將殘存於基板1上的絕緣膜25及層間絕緣膜23的上部去除後，於基板1的表面整個面上形成金屬層，藉由光微影，以具有在與源極區域部16取得接觸的區域上、及與基極接觸區域17取得接觸的區域上露出的開口的方式對光阻劑（未圖示）進行圖案化，並將該光阻劑作為遮罩來對金屬層進行蝕刻，藉此形成與源極區域19電性連接的源電極31、及與基極接觸區域17電性連接的基電極32（參照圖4及圖5）。
進而，於基板1的背面整個面上形成與汲極區域18電性連接的汲電極33。藉由以上方式，可獲得圖6中所示的第二實施方式的半導體裝置200。
再者，第一實施方式的半導體裝置100除汲極區域部15的結構以外，與第二實施方式的半導體裝置200大致相同，因此省略第一實施方式的半導體裝置100的製造方法的說明，但藉由去除第二實施方式的半導體裝置200的製造方法之中，圖11～圖13中所示的形成汲極區域部15的步驟，可獲得第一實施方式的半導體裝置100。
以上，對本發明的實施方式進行了說明，但本發明並不限定於所述實施方式，當然可於不脫離本發明的主旨的範圍內進行各種變更。
於所述實施方式中，將第一導電型設為N型，將第二導電型設為P型進行了說明，但亦可將導電型調換，將第一導電型設為P型，將第二導電型設為N型。
1‧‧‧基板
10、911‧‧‧半導體基板
11‧‧‧磊晶層
12、912‧‧‧半導體層
13、913‧‧‧基極層
130‧‧‧P型雜質區域
140、150‧‧‧N型雜質區域
14‧‧‧源極區域部
141‧‧‧第一部分
142‧‧‧第二部分
143‧‧‧第三部分
15‧‧‧汲極區域部
16‧‧‧源極區域部/第一源極區域部
17、917‧‧‧基極接觸區域
18、918‧‧‧汲極區域
19、919‧‧‧源極區域
20、920‧‧‧溝槽
21、921‧‧‧閘極絕緣膜
22、922‧‧‧閘電極
23、923‧‧‧層間絕緣膜
24、25‧‧‧絕緣膜
31、931‧‧‧源電極
32‧‧‧基電極
33、933‧‧‧汲電極
100、200、900‧‧‧半導體裝置
914‧‧‧源極區域
916‧‧‧源極區域
H1、H2‧‧‧高度
L1、L2‧‧‧長度
X、Y‧‧‧方向
圖1是用於說明本發明的根據第一實施方式的半導體裝置的結構的平面圖。
圖2是沿著圖1的a-a'線的剖面圖。
圖3是沿著圖1的b-b'線的剖面圖。
圖4是沿著圖1的c-c'線的剖面圖。
圖5是沿著圖1的d-d'線的剖面圖。
圖6是用於說明本發明的根據第二實施方式的半導體裝置的結構的剖面圖，且為沿著圖1的a-a'線的剖面圖。
圖7是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖8是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖9是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖10是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖11是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖12是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖13是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖14是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖15是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖16是表示本發明的根據第二實施方式的半導體裝置的製造方法的剖面圖。
圖17是表示本發明的第二實施方式的半導體裝置的製造方法的剖面圖。
圖18（a）及圖18（b）是用於說明先前的半導體裝置的結構的圖，圖18（a）為平面圖，圖18（b）為沿著圖18（a）的a-a'線的剖面圖。

Claims (4)

  1. 一種半導體裝置，其特徵在於，包括： 基板； 第一導電型的汲極區域，具有規定的厚度，設置於所述基板的背面側； 溝槽，以自所述基板的表面到達所述汲極區域的上表面，並於第一方向上延伸的方式設置； 第二導電型的基極層，鄰接於所述溝槽，並設置於所述汲極區域上； 閘極絕緣膜，覆蓋所述溝槽的內側的底面及側面； 閘電極，於所述溝槽內經由所述閘極絕緣膜而自所述溝槽的底面埋入至第一高度為止； 層間絕緣膜，於所述溝槽內自所述第一高度埋入至所述基板的表面為止； 源極區域，設置於所述基板的表面上，包含與所述第一方向垂直的第二方向上的側面接觸所述溝槽的外側面，於所述第一方向上具有第一長度來設置的第一導電型的第一源極區域部，及濃度比所述第一源極區域部低的第一導電型的第二源極區域部； 第二導電型的基極接觸區域，設置於所述基板的表面上，所述第一方向上的兩側面及底面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，濃度比於所述第一方向上與所述源極區域並列設置的所述基極層高； 源電極，於所述基板上，以與所述源極區域電性連接，並於所述第二方向上延伸的方式設置； 基電極，於所述基板上，以與所述基極接觸區域電性連接，並於所述第二方向上延伸的方式設置；以及 汲電極，設置於所述基板的背面上，並與所述汲極區域電性連接； 所述第二源極區域部包含： 第一部分，上表面接觸所述第一源極區域部的底面，所述第二方向上的側面接觸所述溝槽的外側面，於所述第一方向上具有比所述第一長度長的第二長度，且具有自所述第一源極區域部的底面至比所述第一高度高的第二高度為止的深度； 第二部分，上表面接觸所述第一部分的底面的一部分，所述第二方向上的一側的側面接觸所述溝槽的外側面，所述第二方向上的另一側的側面、所述第一方向上的兩側面、及底面接觸所述基極層，於所述第一方向上具有所述第二長度，且具有至少至所述第一高度為止的深度；以及 第三部分，設置於所述基板的表面上，所述第一方向上的一側的側面接觸所述第一源極區域部，所述第一方向上的另一側的側面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，底面接觸所述第一部分的上表面的一部分。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述汲極區域包括：第一導電型的第一汲極區域部，與所述汲電極接觸；第一導電型的第二汲極區域部，設置於所述第一汲極區域部的與所述汲電極相反側的表面上，濃度比所述第二源極區域部低；以及第一導電型的第三汲極區域部，側面接觸所述溝槽的外側面，上側的面接觸所述基極層，下側的面與所述第二汲極區域部連接，且具有與所述第二源極區域部相等的濃度。
  3. 一種半導體裝置的製造方法，其特徵在於，包括： 自第一導電型的基板的表面至規定的深度形成具有規定的厚度的第二導電型的基極層，並使所述基板的比所述基極層更深的剩餘的區域作為第一導電型的汲極區域而殘存的步驟； 形成以自所述基板的表面到達所述汲極區域的方式於第一方向上延伸的溝槽的步驟； 於所述溝槽的內側的底面及側面上形成閘極絕緣膜的步驟； 將閘電極材料經由所述閘極絕緣膜而埋入所述溝槽內的步驟； 對所述閘電極材料的上部進行蝕刻，藉此形成自所述溝槽的底面埋入至第一高度為止的閘電極的步驟； 自所述基板的表面及比所述溝槽的所述第一高度更上方的內側面朝規定的區域中選擇性地注入第一導電型的雜質，藉此形成第一導電型的雜質區域的步驟； 於所述溝槽內自所述第一高度至所述基板的表面為止埋入層間絕緣膜的步驟； 於所述基板的表面上形成第一導電型的第一源極區域部、及濃度比所述第一源極區域部低的第一導電型的第二源極區域部的步驟； 自所述基板的表面朝於所述第一方向上與所述源極區域鄰接的區域中選擇性地注入第二導電型的雜質，藉此於所述基板的表面上形成所述第一方向上的兩側面及底面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，且濃度比所述基極層高的第二導電型的基極接觸區域的步驟； 於所述基板上形成電極膜，並對所述電極膜進行圖案化，藉此形成與所述源極區域電性連接，並於所述第二方向上延伸的源電極，及與所述基極接觸區域電性連接，並於所述第二方向上延伸的基電極的步驟；以及 於所述基板的背面上形成與所述汲極區域電性連接的汲電極的步驟； 所述第一源極區域部藉由自所述基板的表面朝所述第一導電型的雜質區域內選擇性地注入第一導電型的雜質而形成，與所述第一方向垂直的第二方向上的側面接觸所述溝槽的外側面，並於所述第一方向上具有第一長度，並且 所述第二源極區域部包含： 第一部分，上表面接觸所述第一源極區域部的底面，所述第二方向上的側面接觸所述溝槽的外側面，於所述第一方向上具有比所述第一長度長的第二長度，且具有自所述第一源極區域部的底面至比所述第一高度高的第二高度為止的深度； 第二部分，上表面接觸所述第一部分的底面的一部分，所述第二方向上的一側的側面接觸所述溝槽的外側面，所述第二方向上的另一側的側面、所述第一方向上的兩側面、及底面接觸所述基極層，於所述第一方向上具有所述第二長度，且具有至少至所述第一高度為止的深度；以及 第三部分，設置於所述基板的表面上，所述第一方向上的一側的側面接觸所述第一源極區域部，所述第一方向上的另一側的側面接觸所述基極層，所述第二方向上的側面接觸所述溝槽的外側面，底面接觸所述第一部分的上表面的一部分。
  4. 如申請專利範圍第3項所述的半導體裝置的製造方法，其中所述汲極區域具有與所述汲電極接觸的第一導電型的第一汲極區域部，及設置於所述第一汲極區域部的與所述汲電極相反側的表面上、且濃度比所述第二源極區域部低的第一導電型的第二汲極區域部，所述半導體裝置的製造方法更包括： 於形成所述閘電極步驟之前，自所述溝槽的底面朝所述第二汲極區域部中注入第一導電型的雜質，並使所述第一導電型的雜質進行熱擴散的步驟；以及 將所述溝槽向下挖直至所述溝槽的底面到達所述第二汲極區域部為止，藉此形成側面接觸所述溝槽的外側面，上側的面接觸所述基極層，下側的面與所述第二汲極區域部連接，且濃度與所述第二源極區域部相等的第一導電型的第三汲極區域部作為所述汲極區域的一部分的步驟。
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