TW201409578A - 具有低米勒電容之半導體元件的製作方法 - Google Patents

具有低米勒電容之半導體元件的製作方法 Download PDF

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TW201409578A
TW201409578A TW101129913A TW101129913A TW201409578A TW 201409578 A TW201409578 A TW 201409578A TW 101129913 A TW101129913 A TW 101129913A TW 101129913 A TW101129913 A TW 101129913A TW 201409578 A TW201409578 A TW 201409578A
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forming
semiconductor device
trench
gate
fabricating
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Yung-Fa Lin
Chia-Hao Chang
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Anpec Electronics Corp
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Priority to TW101129913A priority Critical patent/TW201409578A/zh
Priority to CN201210350105.0A priority patent/CN103594348A/zh
Priority to US13/628,055 priority patent/US8828822B2/en
Publication of TW201409578A publication Critical patent/TW201409578A/zh

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Abstract

具有低米勒電容之半導體元件的製作方法，包含有：提供一第一導電型之半導體基底；於該半導體基底上形成一磊晶層；於該磊晶層中形成至少一閘極溝槽；於該閘極溝槽的側壁形成一側壁子；蝕刻該閘極溝槽的底部，形成一凹陷溝槽；進行一熱氧化製程，經由該凹陷溝槽氧化該磊晶層，如此形成一氧化層，填滿該凹陷溝槽；去除該側壁子；於該閘極溝槽的側壁形成一閘極氧化層；以及於該閘極溝槽中形成一閘極。

Description

具有低米勒電容之半導體元件的製作方法
本發明係有關於半導體元件技術領域，特別是有關於一種具有低米勒電容之金氧半場效電晶體(MOSFET)元件的製作方法。
在傳統功率電晶體中，平面型功率元件(DMOS)因來自於通道區域(channel region)、聚集層(accumulation layer)以及接面場效電晶體(JFET)的貢獻，而使得導通電阻(on-resistance)上升。為了降低上述區域之電阻，溝渠型功率元件(UMOS)於是被提出來，更因為UMOS結構不存在之JFET區域，因此可以縮小UMOS元件尺寸(cell size)以提高通道密度(channel density)，可以進一步降低導通電阻，但另一方面，UMOS元件也因其結構的關係導致閘汲間電容(米勒電容)上升而使得開關速度變慢。
因此，本發明之目的，即在傳統UMOS下方再置入一溝渠結構，並利用氧化製程(oxidation)填入此溝渠，以降低米勒電容。在小線寬(small pitch)的結構下，氧化製程比傳統沉積製程更容易進行，因此，本發明亦可應用於具有超級接面之溝渠結構電晶體之深溝渠填入製程，藉以克服高深寬比(high aspect ratio)填入之問題。
根據本發明之較佳實施例，本發明提供一種具有低米勒電容之半 導體元件的製作方法，包含有：提供一第一導電型之半導體基底；於該半導體基底上形成一磊晶層；於該磊晶層中形成至少一閘極溝槽；於該閘極溝槽的側壁形成一側壁子；蝕刻該閘極溝槽的底部，形成一凹陷溝槽；進行一熱氧化製程，經由該凹陷溝槽氧化該磊晶層，如此形成一氧化層，填滿該凹陷溝槽；去除該側壁子；於該閘極溝槽的側壁形成一閘極氧化層；以及於該閘極溝槽中形成一閘極。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
請參閱第1圖至第11圖，其為依據本發明一實施例所繪示的電晶體元件之製造方法示意圖。首先，如第1圖所示，提供一半導體基底10，例如N型重摻雜之矽基底，可作為電晶體元件的汲極(drain)。接著，利用一磊晶製程於半導體基底10上形成一磊晶層11，例如N型磊晶矽層。
如第2圖所示，接著於磊晶層11上沈積一硬遮罩層12，例如矽氧層，然後，利用光阻層13以及微影、蝕刻等製程，於硬遮罩層12中形成開口112。
如第3圖所示，接著將光阻層13去除，然後，利用乾蝕刻製程，經由硬遮罩層12中的開口112，蝕刻磊晶層11至一第一預定深度，如此形成閘極溝槽122。
如第4圖所示，接下來於閘極溝槽122的側壁上形成側壁子14， 例如，氮化矽側壁子。形成側壁子14方法，例如，先沈積一氮化矽層，然後以非等向性蝕刻製程回蝕刻該氮化矽層。
如第5圖所示，接著進行另一乾蝕刻製程，利用側壁子14作為蝕刻遮罩，繼續經由閘極溝槽122蝕刻磊晶層11至一第二預定深度，如此在閘極溝槽122下方形成一凹陷溝槽123。凹陷溝槽123的開口寬度大小，可以藉由側壁子14的厚度來控制。
如第6圖所示，接著進行一熱氧化製程，例如，在溫度介於800-1200℃，以水蒸汽、氧氣，或內含少量氯化氫或氮氣的水蒸汽或氧氣，製程壓力介於600-760托耳(torr))的條件下，利用側壁子14作為保護層，氧化凹陷溝槽123內未被側壁子14遮蓋住的部分，使得凹陷溝槽123最後被氧化層16填滿，而在氧化層16表面上留下楔形凹陷結構16a。
如第7圖所示，在形成氧化層16後，接著去除側壁子14，顯露出閘極溝槽122的側壁，再去除硬遮罩層12，顯露出磊晶層11的表面。去除硬遮罩層12的方法可以先以光阻塗佈在磊晶層11的表面並填入閘極溝槽122，再回蝕刻光阻，顯露出硬遮罩層12，蝕刻掉硬遮罩層12之後，再去除光阻。
如第8圖所示，接著進行一熱氧化製程，於顯露出來的磊晶層11的表面以及閘極溝槽122的側壁形成一閘極氧化層18，接下來，進行一化學氣相沈積製程，全面沈積一多晶矽層20，並使多晶矽層20填滿閘極溝槽122。
如第9圖所示，接著進行一蝕刻製程，將部分厚度的多晶矽層20蝕除，顯露出閘極氧化層18，而剩下的多晶矽層20則構成溝渠 閘極20a。接著，進行一離子佈植製程，於磊晶層11中形成一離子井210，例如P型井。
如第10圖所示，接著利用微影製程於磊晶層11上形成一圖案化光阻層(圖未示)，定義出源極區域，再以離子佈植製程將摻質，例如N型摻質，植入上述源極區域，構成源極摻雜區22。之後，再將光阻層去除，並以施以熱驅入製程，活化這些被植入的摻質。
最後，如第11圖所示，形成接觸洞，並進行金屬化製程，包括形成層間介電層30，於層間介電層30中形成接觸洞230，於接觸洞230底部以離子佈植製程形成接觸摻雜區250，沈積阻障層32及金屬層34，並使金屬層34填滿接觸洞230，構成接觸件34a。
請參閱第12圖至第19圖，其為依據本發明另一實施例所繪示的含有超級接面的電晶體元件之製造方法示意圖，其中，仍沿用相同的符號來表示相同的區域或元件。如第12圖所示，首先提供一半導體基底10，例如N型矽基底，可作為電晶體元件的汲極。接著，利用一磊晶製程於半導體基底10上形成一磊晶層11，例如P型磊晶矽層。接著，在磊晶層11中形成一離子井210，例如，P型井。然後，在磊晶層11上形成一硬遮罩層12，其具有複數個開口112，顯露出部分的磊晶層11的表面。
如第13圖所示，接著進行一乾蝕刻製程，經由開口112蝕刻磊晶層11至一第一預定深度，如此形成閘極溝槽122。
如第14圖所示，接下來於閘極溝槽122的側壁上形成側壁子14，例如，氮化矽側壁子。形成側壁子14方法，例如，先沈積一氮化矽層，然後以非等向性蝕刻製程回蝕刻該氮化矽層。
如第15圖所示，接著進行另一乾蝕刻製程，利用側壁子14作為蝕刻遮罩，繼續經由閘極溝槽122蝕刻磊晶層11至一第二預定深度，如此在閘極溝槽122下方形成一凹陷溝槽123。凹陷溝槽123的開口寬度大小，可以藉由側壁子14的厚度來控制。再以擴散等方式，於凹陷溝槽123內的磊晶層11中形成基體摻雜區310，例如，N型基體摻雜區。當然，基體摻雜區310亦可以在形成側壁子14之前，利用不同能量的離子佈植製程經由閘極溝槽122的底部植入磊晶層11。
如第16圖所示，接著進行一熱氧化製程，利用側壁子14作為保護層，氧化凹陷溝槽123內未被側壁子14遮蓋住的部分，使得凹陷溝槽123最後被氧化層16填滿，而在氧化層16表面上留下楔形凹陷結構16a。
如第17圖所示，在形成氧化層16後，接著去除側壁子14，顯露出閘極溝槽122的側壁，再去除硬遮罩層12，顯露出磊晶層11的表面。接著進行一熱氧化製程，於顯露出來的磊晶層11的表面以及閘極溝槽122的側壁形成一閘極氧化層18，接下來，進行一化學氣相沈積製程，全面沈積一多晶矽層20，並使多晶矽層20填滿閘極溝槽122。
如第18圖所示，接著進行一蝕刻製程或一研磨製程，將部分厚度的多晶矽層20蝕除或磨平，顯露出磊晶層11，而剩下的多晶矽層20則構成溝渠閘極20a，其具有一楔形底部。接著以離子佈植製程將摻質，例如N型摻質，植入源極區域，構成源極摻雜區22。
如第19圖所示，形成接觸洞，並進行金屬化製程，包括形成層 間介電層30，於層間介電層30中形成接觸洞230，於接觸洞230底部以離子佈植製程形成接觸摻雜區250，沈積阻障層32及金屬層34，並使金屬層34填滿接觸洞230，構成接觸件34a。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體基底
11‧‧‧磊晶層
12‧‧‧硬遮罩層
13‧‧‧光阻層
14‧‧‧側壁子
16‧‧‧氧化層
16a‧‧‧楔形凹陷結構
18‧‧‧閘極氧化層
20‧‧‧多晶矽層
20a‧‧‧閘極
22‧‧‧源極摻雜區
30‧‧‧層間介電層
32‧‧‧阻障層
34‧‧‧金屬層
34a‧‧‧接觸件
112‧‧‧開口
122‧‧‧閘極溝槽
123‧‧‧凹陷溝槽
210‧‧‧離子井
230‧‧‧接觸洞
250‧‧‧接觸摻雜區
310‧‧‧基體摻雜區
第1圖至第11圖為依據本發明一實施例所繪示的電晶體元件之製造方法示意圖。
第12圖至第19圖為依據本發明另一實施例所繪示的含有超級接面的電晶體元件之製造方法示意圖。
10‧‧‧半導體基底
11‧‧‧磊晶層
12‧‧‧硬遮罩層
14‧‧‧側壁子
16‧‧‧氧化層
16a‧‧‧楔形凹陷結構
122‧‧‧閘極溝槽
123‧‧‧凹陷溝槽

Claims (9)

  1. 一種具有低米勒電容之半導體元件的製作方法，包含有：提供一第一導電型之半導體基底；於該半導體基底上形成一磊晶層；於該磊晶層中形成至少一閘極溝槽；於該閘極溝槽的側壁形成一側壁子；經由該閘極溝槽的底部蝕刻該磊晶層，形成一凹陷溝槽；進行一熱氧化製程，經由該凹陷溝槽氧化該磊晶層，如此形成一氧化層，填滿該凹陷溝槽；去除該側壁子；於該閘極溝槽的側壁形成一閘極氧化層；以及於該閘極溝槽中形成一閘極。
  2. 如申請專利範圍第1項所述之具有低米勒電容之半導體元件的製作方法，其中該熱氧化製程係在溫度介於800-1200℃，以水蒸汽、氧氣，或內含少量氯化氫或氮氣的水蒸汽或氧氣，製程壓力介於600-760托耳的條件下進行。
  3. 如申請專利範圍第1項所述之具有低米勒電容之半導體元件的製作方法，其中該磊晶層具有該第一導電型。
  4. 如申請專利範圍第1項所述之具有低米勒電容之半導體元件的製作方法，其中於該閘極溝槽中形成該閘極之後，另包含有以下步 驟：於該磊晶層中形成一離子井，具有一第二導電型；以及於該離子井中形成至少一源極摻雜區，該源極摻雜區具有該第一導電型。
  5. 如申請專利範圍第4項所述之具有低米勒電容之半導體元件的製作方法，其中該第一導電型為N型，該第二導電型為P型。
  6. 如申請專利範圍第1項所述之具有低米勒電容之半導體元件的製作方法，其中該氧化層填滿該凹陷溝槽後，其表面上形成一楔形凹陷結構。
  7. 如申請專利範圍第1項所述之具有低米勒電容之半導體元件的製作方法，其中該半導體基底係作為該半導體元件的汲極。
  8. 如申請專利範圍第1項所述之具有低米勒電容之半導體元件的製作方法，其中在形成該凹陷溝槽之後，另包含有以下步驟：於該磊晶層中形成一基體摻雜區。
  9. 如申請專利範圍第8項所述之具有低米勒電容之半導體元件的製作方法，其中該基體摻雜區具有該第一導電型。
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