CN103594348A - 具有低密勒电容的半导体元件的制作方法 - Google Patents

具有低密勒电容的半导体元件的制作方法 Download PDF

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CN103594348A
CN103594348A CN201210350105.0A CN201210350105A CN103594348A CN 103594348 A CN103594348 A CN 103594348A CN 201210350105 A CN201210350105 A CN 201210350105A CN 103594348 A CN103594348 A CN 103594348A
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semiconductor element
manufacture method
miller capacitance
epitaxial loayer
sidewall
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林永发
张家豪
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Anpec Electronics Corp
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Abstract

本发明公开了一种具有低密勒电容的半导体元件的制作方法，其步骤包含提供一第一导电型的半导体基底、于所述半导体基底上形成一外延层、于所述外延层中形成至少一栅极沟槽、于所述栅极沟槽的侧壁形成一侧壁子、刻蚀所述栅极沟槽的底部以形成一凹陷沟槽、进行一热氧化工艺经由所述凹陷沟槽氧化所述外延层，如此以形成一氧化层填满凹陷沟槽、去除所述侧壁子、于栅极沟槽的侧壁形成一栅极氧化层、以及于所述栅极沟槽中形成一栅极。

Description

具有低密勒电容的半导体元件的制作方法
技术领域
本发明大体上关于半导体元件的技术领域，特别是有关于一种具有低密勒电容的金氧半场效应晶体管(MOSFET)元件的制作方法。
背景技术
在传统的功率晶体管中，平面型的功率元件(DMOS)会因为沟道区域(channel region)、积累层(accumulation layer)以及结型场效晶体管(JFET)的缘故而使得其导通电阻上升。为了降低上述区域的电阻，沟渠型功率元件(UMOS)于是被提出来，更因为UMOS结构中不存在有JFET区域，因此可以缩小UMOS元件的单元尺寸以提高沟道密度，并进一步降低其导通电阻。但另一方面，UMOS元件也因其结构的关系导致栅极间电容(密勒电容)上升而使得开关速度变慢。
因此，本发明的目的即在传统UMOS下方再置入一沟渠结构，并利用氧化工艺填入此沟渠以降低密勒电容。在小节距的结构设计中，氧化工艺会比传统的沉积工艺更容易进行，因此，本发明也可应用于具有超结的沟渠结构晶体管的深沟渠填入工艺，借以克服高深宽比的填充问题。
发明内容
根据本发明的优选实施例，本发明提供一种具有低密勒电容的半导体元件的制作方法，其步骤包含：提供一第一导电型的半导体基底、于所述半导体基底上形成一外延层、于所述外延层中形成至少一栅极沟槽、于所述栅极沟槽的侧壁形成一侧壁子、刻蚀所述栅极沟槽的底部以形成一凹陷沟槽、进行一热氧化工艺以经由所述凹陷沟槽氧化所述外延层，如此形成一氧化层填满所述凹陷沟槽、去除所述侧壁子、于所述栅极沟槽的侧壁形成一栅极氧化层、以及于所述栅极沟槽中形成一栅极。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图11为依据本发明一实施例所绘示的晶体管元件的制造方法示意图。
图12至图19为依据本发明另一实施例所绘示的含有超结的晶体管元件的制造方法示意图。
其中，附图标记说明如下：
10半导体基底               30层间介电层
11外延层                   32阻障层
12硬掩膜层                 34金属层
13光刻胶层                 34a接触件
14侧壁子                   112开口
16氧化层                   122栅极沟槽
16a楔形凹陷结构            123凹陷沟槽
18栅极氧化层               210离子井
20多晶硅层                 230接触洞
20a栅极                    250接触掺杂区
22源极掺杂区               310基体掺杂区
具体实施方式
请参阅图1至图11，其为依据本发明一实施例所绘示的晶体管元件的制造方法示意图。首先，如图1所示，提供一半导体基底10，例如N型重掺杂的硅基底，其可作为晶体管元件的漏极。接着，利用一外延工艺于半导体基底10上形成一外延层11，例如N型外延硅层。
如图2所示，接着于外延层11上沉积一硬掩膜层12，例如硅氧层，然后利用光刻胶层13以及光刻等工艺于硬掩膜层12中形成开口112。
如图3所示，接着将光刻胶层13去除，然后，利用干刻蚀工艺经由硬掩膜层12中的开口112刻蚀外延层11至一第一预定深度，如此形成栅极沟槽122。
如图4所示，接下来于栅极沟槽122的侧壁上形成侧壁子14，例如氮化硅侧壁子。形成侧壁子14方法可为先沉积一氮化硅层，然后以各向异性刻蚀工艺回刻蚀所述氮化硅层。
如图5所示，接着进行另一干刻蚀工艺，利用侧壁子14作为刻蚀掩膜继续经由栅极沟槽122刻蚀外延层11至一第二预定深度，如此在栅极沟槽122下方形成一凹陷沟槽123。凹陷沟槽123的开口宽度大小可以借由侧壁子14的厚度来控制。
如图6所示，接着进行一热氧化工艺，如在温度介于800-1200℃，以水蒸气、氧气，或内含少量氯化氢或氮气的水蒸气或氧气，在工艺压力介于600-760托(torr)的条件下，利用侧壁子14作为保护层来氧化凹陷沟槽123内未被侧壁子14遮盖住的部分，使得凹陷沟槽123最后被氧化层16填满，而在氧化层16表面上留下楔形凹陷结构16a。
如图7所示，在形成氧化层16后，接着去除侧壁子14以裸露出栅极沟槽122的侧壁，再去除硬掩膜层12以裸露出外延层11的表面。去除硬掩膜层12的方法可为先以光刻胶涂布在外延层11的表面并填入栅极沟槽122，再回刻蚀光刻胶以裸露出硬掩膜层12。待刻蚀硬掩膜层12之后，再去除光刻胶。
如图8所示，接着进行一热氧化工艺于裸露出来的外延层11表面以及栅极沟槽122侧壁形成一栅极氧化层18，接下来，进行一化学气相沉积工艺全面性地沉积一多晶硅层20，并使多晶硅层20填满栅极沟槽122。
如图9所示，接着进行一刻蚀工艺将部分厚度的多晶硅层20蚀除，以裸露出栅极氧化层18，而剩下的多晶硅层20则构成沟渠栅极20a。接着，进行一离子注入工艺以于外延层11中形成一离子井210，例如P型井。
如图10所示，接着利用光刻工艺于外延层11上形成一图案化光刻胶层(图未示)，定义出源极区域，再以离子注入工艺将掺质(如N型掺质)注入上述源极区域，构成源极掺杂区22。之后，再将光刻胶层去除，并施以热驱入工艺活化这些被植入的掺质。
最后，如图11所示，形成接触洞，并进行金属化工艺，包括形成层间介电层30、于层间介电层30中形成接触洞230、于接触洞230底部以离子注入工艺形成接触掺杂区250、沉积阻障层32及金属层34、以及使金属层34填满接触洞230以构成接触件34a。
请参阅图12至19图，其为依据本发明另一实施例所绘示的含有超结的晶体管元件的制造方法示意图，图中仍沿用相同的符号来表示相同的区域或组件。如图12所示，首先提供一半导体基底10，例如N型硅基底，其可作为晶体管元件的漏极。接着，利用一外延工艺于半导体基底10上形成一外延层11，例如P型外延硅层。接着，在外延层11中形成一离子井210，例如P型井。然后，在外延层11上形成一硬掩膜层12，其具有多个开口112以裸露出部分的外延层11的表面。
如图13所示，接着进行一干刻蚀工艺、经由开口112刻蚀外延层11至一第一预定深度，如此形成栅极沟槽122。
如图14所示，接下来于栅极沟槽122的侧壁上形成侧壁子14，例如氮化硅侧壁子。形成侧壁子14方法，如先沉积一氮化硅层，然后以各向异性刻蚀工艺回刻蚀所述氮化硅层。
如图15所示，接着进行另一干刻蚀工艺，利用侧壁子14作为刻蚀掩膜继续经由栅极沟槽122刻蚀外延层11至一第二预定深度，如此在栅极沟槽122下方形成一凹陷沟槽123。凹陷沟槽123的开口宽度大小可以借由侧壁子14的厚度来控制。再以扩散等方式于凹陷沟槽123内的外延层11中形成基体掺杂区310，例如N型基体掺杂区。当然，基体掺杂区310也可以在形成侧壁子14之前利用不同能量的离子注入工艺经由栅极沟槽122底部注入外延层11。
如图16所示，接着进行一热氧化工艺，利用侧壁子14作为保护层氧化凹陷沟槽123内未被侧壁子14遮盖住的部分，使得凹陷沟槽123最后被氧化层16填满，而在氧化层16表面上留下楔形凹陷结构16a。
如图17所示，在形成氧化层16后，接着去除侧壁子14以裸露出栅极沟槽122的侧壁，再去除硬掩膜层12以裸露出外延层11的表面。接着进行一热氧化工艺于裸露出的外延层11表面以及栅极沟槽122的侧壁形成一栅极氧化层18，接下来，进行一化学气相沉积工艺全面性地沉积一多晶硅层20，并使多晶硅层20填满栅极沟槽122。
如图18所示，接着进行一刻蚀工艺或一抛光工艺将部分厚度的多晶硅层20蚀除或磨平，以裸露出外延层11，而剩下的多晶硅层20则构成沟渠栅极20a，其具有一楔形底部。接着以离子注入工艺将掺质(如N型掺质)注入源极区域，构成源极掺杂区22。
如图19所示，形成接触洞，并进行金属化工艺，包括形成层间介电层30、于层间介电层30中形成接触洞230、于接触洞230底部以离子注入工艺形成接触掺杂区250、沉积阻障层32及金属层34、以及使金属层34填满接触洞230，构成接触件34a。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种具有低密勒电容的半导体元件的制作方法，其特征在于，包含：
提供一第一导电型的半导体基底；
于所述半导体基底上形成一外延层；
于所述外延层中形成至少一栅极沟槽；
于所述栅极沟槽的侧壁形成一侧壁子；
经由所述栅极沟槽的底部刻蚀所述外延层以形成一凹陷沟槽；
进行一热氧化工艺以经由所述凹陷沟槽氧化所述外延层，如此形成一氧化层填满所述凹陷沟槽；
去除所述侧壁子；
于所述栅极沟槽的侧壁形成一栅极氧化层；以及
于所述栅极沟槽中形成一栅极。
2.根据权利要求1所述的具有低密勒电容的半导体元件的制作方法，其特征在于，所述热氧化工艺是在温度介于800-1200℃，以水蒸气、氧气，或内含氯化氢或氮气的水蒸气或氧气，在工艺压力介于600-760托的条件下进行。
3.根据权利要求1所述的具有低密勒电容的半导体元件的制作方法，其特征在于，所述外延层具有所述第一导电型。
4.根据权利要求1所述的具有低密勒电容的半导体元件的制作方法，其特征在于，于所述栅极沟槽中形成所述栅极之后，另包含有以下步骤：
于所述外延层中形成一具有一第二导电型的离子井；以及
于所述离子井中形成至少一具有所述第一导电型的源极掺杂区。
5.根据权利要求4所述的具有低密勒电容的半导体元件的制作方法，其特征在于，所述第一导电型为N型，所述第二导电型为P型。
6.根据权利要求1所述的具有低密勒电容的半导体元件的制作方法，其特征在于，所述氧化层填满所述凹陷沟槽后，在所述氧化层表面上形成一楔形凹陷结构。
7.根据权利要求1所述的具有低密勒电容的半导体元件的制作方法，其特征在于，所述半导体基底是作为所述半导体元件的漏极。
8.根据权利要求1所述的具有低密勒电容的半导体元件的制作方法，其特征在于，在形成所述凹陷沟槽之后，另包含有以下步骤：
于所述外延层中形成一基体掺杂区。
9.根据权利要求8所述的具有低密勒电容的半导体元件的制作方法，其特征在于，所述基体掺杂区具有所述第一导电型。
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