CN104103519A - 半导体功率器件的制作方法 - Google Patents

半导体功率器件的制作方法 Download PDF

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CN104103519A
CN104103519A CN201310182816.6A CN201310182816A CN104103519A CN 104103519 A CN104103519 A CN 104103519A CN 201310182816 A CN201310182816 A CN 201310182816A CN 104103519 A CN104103519 A CN 104103519A
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epitaxial loayer
hard mask
layer
manufacture method
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CN104103519B (zh
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林永发
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Anpec Electronics Corp
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Abstract

本发明公开了一种半导体功率器件的制作方法，首先提供一半导体基底，其上形成有外延层；于外延层表面形成硬掩膜层，其具有第一开口；再经由第一开口刻蚀外延层，形成第一沟槽；修整硬掩膜层，将第一开口增宽为第二开口，并显露出第一沟槽上缘的转角部位；接着于第一沟槽中填满一掺杂层；再将掺杂层的掺杂物驱入到外延层中，以于第一沟槽内形成掺杂区，包括接近第一沟槽表面的第一区域及较深入外延层的第二区域，再以经过修整后的硬掩膜层作为刻蚀硬掩膜，刻蚀去除全部的掺杂层及至少第一区域内的外延层，形成第二沟槽。

Description

半导体功率器件的制作方法
技术领域
本发明涉及一种半导体功率器件的制作方法，尤其涉及一种具有超结(super junction)结构的半导体功率器件(例如功率晶体管)的制作方法。
背景技术
已知，在功率器件中，其基底的设计通常为P型与N型半导体交替设置，因此在基底中会存在有多个垂直于基底表面的PN结，且该些PN结是互相平行的，又称为超结结构，此种结构具有耐压低阻抗的优点。
其中一种超结结构是利用刻蚀出深沟渠，填入与基底导电性相反的外延掺杂层，再利用后续高温扩散将掺杂层的掺杂物驱入，以形成PN交替的超结，其具有工艺上简化以及低成本的优点。然而这种技术仍有技术问题需要克服，例如，掺杂物驱入后的表面浓度过高，导致载子浓度分布不均匀的问题。
发明内容
因此本发明的目的即在于提供一种改良的半导体功率器件的制作方法，利用二次沟渠刻蚀去除高浓度的沟渠侧壁，以提升超结功率器件的电性及良率。
为达上述目的，本发明提出一种半导体功率器件的制作方法，首先提供一半导体基底；于所述半导体基底上形成一外延层；于所述外延层表面形成一硬掩膜层；于所述硬掩膜层中形成至少一第一开口；经由所述第一开口刻蚀所述外延层，形成至少一第一沟槽；修整所述硬掩膜层，将所述第一开口增宽为一第二开口，并显露出所述第一沟槽上缘的转角部位；于所述第一沟槽中填满一掺杂层；进行一高温扩散工艺，将所述掺杂层的掺杂物驱入到所述外延层中，如此于所述第一沟槽内形成一掺杂区，包括接近所述第一沟槽表面的一第一区域以及较深入所述外延层的一第二区域；以及进行一干刻蚀工艺，以经过修整后的所述硬掩膜层作为刻蚀硬掩膜，刻蚀去除全部的所述掺杂层以及至少刻蚀去除所述第一区域内的所述外延层，以形成一第二沟槽。
根据本发明另一实施例，其提出了一种半导体功率器件的制作方法，首先提供一半导体基底；于所述半导体基底上形成一外延层；于所述外延层表面形成一硬掩膜层；于所述硬掩膜层中形成至少一第一开口；于所述第一开口的侧壁上形成一侧壁子；经由所述第一开口刻蚀所述外延层，形成至少一第一沟槽；去除所述侧壁子，显露出所述第一沟槽上缘的转角部位；于所述第一沟槽中填满一掺杂层；进行一高温扩散工艺，将所述掺杂层的掺杂物驱入到所述外延层中，如此于所述第一沟槽内形成一掺杂区，包括接近所述第一沟槽表面的一第一区域以及较深入所述外延层的一第二区域；以及进行一干刻蚀工艺，以经过修整后的所述硬掩膜层作为刻蚀硬掩膜，刻蚀去除全部的所述掺杂层以及至少刻蚀去除所述第一区域内的所述外延层，以形成一第二沟槽。
根据本发明又另一实施例，其提出了一种半导体功率器件的制作方法，首先提供一半导体基底；于所述半导体基底上形成一外延层；于所述外延层表面形成一硬掩膜层；于所述硬掩膜层上形成一光刻胶图案，所述光刻胶图案包含有至少一第一开口；经由所述第一开口刻蚀所述硬掩膜层，形成至少一第二开口；修整所述硬掩膜层，将所述第二开口增宽为一第三开口；经由所述第一开口，刻蚀所述外延层，形成至少一第一沟槽；去除所述光刻胶图案；于所述第三开口及所述第一沟槽中填满一掺杂层；进行一高温扩散工艺，将所述掺杂层的掺杂物驱入到所述外延层中，如此于所述第一沟槽内形成一掺杂区，包括接近所述第一沟槽表面的一第一区域以及较深入所述外延层的一第二区域；以及进行一干刻蚀工艺，以经过修整后的所述硬掩膜层作为刻蚀硬掩膜，刻蚀去除全部的所述掺杂层以及至少刻蚀去除所述第一区域内的所述外延层，以形成一第二沟槽。
为让本发明的上述目的、特征及优点能更为明显易懂，下文中特举出优选实施方式并配合附图作详细说明如下。然而如下的优选实施方式与图式仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图10为依据本发明实施例1所绘示的沟渠式功率晶体管器件的制造方法示意图。
图11至图16为依据本发明实施例2所绘示的沟渠式功率晶体管器件的制造方法示意图。
图17至图22为依据本发明实施例3所绘示的沟渠式功率晶体管器件的制造方法示意图。
其中，附图标记说明如下：
10    半导体基底           122a 转角部位
11    外延层               130  离子井
12    硬掩膜层             132  源极掺杂区
13    掺杂多晶硅层         210  掺杂区
22    栅极氧化层           211  第一区域
24    栅极                 212  第二区域
30    层间介电层           222  沟槽
32    阻障层               226  硅氧层
34    金属层               230  接触洞
34a   接触件               310  光刻胶图案
112   开口                 310a 开口
112a  开口                 420  侧壁子
122   沟槽
具体实施方式
实施例1
请参阅图1至图10，其为依据本实施例所绘示的沟渠式功率晶体管器件的制造方法示意图。首先，如图1所示，提供一半导体基底10，其具有第一电性，例如N型重掺杂的硅晶圆，其可作为晶体管器件的漏极(drain)。再利用一外延工艺于半导体基底10上形成一外延层11，例如N型外延硅层或P型外延硅层。
如图2所示，接着，在外延层11表面形成一硬掩膜层12，如氧化硅或氮化硅。然后，利用光刻、刻蚀等工艺，于硬掩膜层12中形成开口112，如直线形的开口，其具有宽度W1。然后，如图3所示，利用干刻蚀工艺，经由硬掩膜层12中的开口112，干刻蚀外延层11至一深度H1，形成沟槽122，其中，沟槽122的宽度约略等于开口112的宽度W1，而深度H1小于外延层11的厚度。
如图4所示，进行一硬掩膜修整步骤，利用如湿刻蚀等方式去除宽度d的硬掩膜层12，如此将原本开口宽度为W1的开口112增宽为宽度为W2的开口112a，并显露出部分的沟槽122上缘的转角部位122a。根据本发明实施例，宽度d可以是约为0.5微米，但不限于此。
如图5所示，接着于沟槽122中填满掺杂多晶硅层13。根据本发明实施例，掺杂多晶硅层13的电性与外延层11的电性相反，例如，若外延层11为N型，掺杂多晶硅层13则为P型掺杂，若外延层11为P型，掺杂多晶硅层13则为N型掺杂。根据本发明实施例，外延层11为N型。根据本发明实施例，掺杂多晶硅层13可以覆盖硬掩膜层12。随后，进行一高温扩散工艺，将掺杂多晶硅层13的掺杂物驱入到外延层11中，形成PN交替的超结。
此时，扩散进入到外延层11的掺杂区210包括接近沟槽122表面的第一区域211以及较深入外延层11的第二区域212，其中，第一区域211的掺杂浓度高于第二区域212的掺杂浓度。例如，第一区域211的掺杂浓度可约介于1×1017atoms/cm3至1×1019atoms/cm3之间，而第二区域212的掺杂浓度约为1×1016atoms/cm3，但不限于上述浓度范围。根据本发明实施例，第一区域211的宽度约略等于上述硬掩膜修整步骤时所去除掉的硬掩膜层12的宽度d。
如图6所示，接着进行干刻蚀工艺，以经过修整后的硬掩膜层12作为刻蚀硬掩膜，刻蚀去除全部的掺杂多晶硅层13以及至少刻蚀去除在第一区域211内的外延层11，形成沟槽222，其中，沟槽222的宽度约略等于开口112a的宽度W2，而沟槽222的深度H2大于沟槽122的深度H1，且可以大于或约略等于外延层11的厚度。需注意，若外延层11为N型，则上述沟槽222刻蚀的深度可以选择性地贯穿或不贯穿外延层11，若外延层11为P型的话，则沟槽222刻蚀的深度必须贯穿外延层11。
如图7所示，沉积一硅氧层226，使硅氧层226填满沟槽222。在沉积硅氧层226之前，还可以先进行氧化工艺，在沟槽222表面形成一牺牲氧化层(未示于图中)，再以刻蚀方式去除掉所述牺牲氧化层。接着，可以利用化学机械抛光(CMP)工艺，将硬掩膜层12表面上的硅氧层226抛光去除，再回刻蚀沟槽222内部分厚度的硅氧层226，使硅氧层226的上表面低于硬掩膜层12表面。
如图8所示，去除硬掩膜层12，显露出外延层11的上表面。接着，于外延层的上表面形成栅极氧化层22以及栅极24。根据本发明实施例，栅极24可以是多晶硅栅极。再进行一离子注入工艺，于两栅极24之间的外延层11中注入具有第二电性(例如P型)的掺质，形成离子井130。后续可再进行热驱入(thermal drive-in)工艺。
如图9所示，利用光刻胶及光刻工艺，界定出源极掺杂区域，然后，施以离子注入，将第一电性(例如N型)的掺质注入离子井130，形成源极掺杂区132。后续可以进行热驱入工艺。
最后，如图10所示，进行接触洞及金属化工艺，包括形成层间介电层30，于层间介电层30中刻蚀出接触洞230，接触洞230显露出部分的离子井130、源极掺杂区132，以及硅氧层226。沉积阻障层32及金属层34，并使金属层34填满接触洞230，构成接触件34a，接触离子井130及源极掺杂区132。
实施例2
图11至图16为依据本实施例所绘示的沟渠式功率晶体管器件的制造方法示意图。如图11所示，同样提供一半导体基底10，其具有第一电性，例如N型重掺杂的硅晶圆，其可作为晶体管器件的漏极。再利用一外延工艺于半导体基底10上形成一外延层11，如N型外延硅层或P型外延层。接着，在外延层11表面形成一硬掩膜层12，如氧化硅或氮化硅。然后，利用光刻工艺先在硬掩膜层12上形成一光刻胶图案310，其具有开口310a，开口310a具有宽度W1，再以刻蚀工艺于硬掩膜层12中形成开口112，例如直线形的开口，同样具有宽度W1。
如图12所示，接着针对硬掩膜层12进行一硬掩膜修整步骤，利用如湿刻蚀等方式去除宽度d的硬掩膜层12，如此将原本开口宽度为W1的开口112增宽为宽度为W2的开口112a。根据本发明实施例，宽度d可以是约为0.5微米，但不限于此。
如图13所示，利用各向异性的干刻蚀工艺，经由光刻胶图案310的开口310a干刻蚀外延层11至一深度H1，形成沟槽122，其中，沟槽122的宽度约略等于开口310a的宽度W1，而深度H1小于外延层11的厚度。
如图14所示，在形成沟槽122之后，接着去除光刻胶图案310，显露出经过修整后的硬掩膜层12。
然后，如图15所示，于沟槽122中填满掺杂多晶硅层13。根据本发明实施例，掺杂多晶硅层13的电性与外延层11的电性相反，例如，若外延层11为N型，掺杂多晶硅层13则为P型掺杂，若外延层11为P型，掺杂多晶硅层13则为N型掺杂。根据本发明实施例，掺杂多晶硅层13可以覆盖硬掩膜层12。随后，进行一高温扩散工艺，将掺杂多晶硅层13的掺杂物驱入到外延层11中，形成PN交替的超结结构。
此时，扩散进入到外延层11的掺杂区210包括接近沟槽122表面的第一区域211以及较深入外延层11的第二区域212，其中，第一区域211的掺杂浓度高于第二区域212的掺杂浓度。例如，第一区域211的掺杂浓度约介于1×1017atoms/cm3至1×1019atoms/cm3之间，而第二区域212的掺杂浓度约为1×1016atoms/cm3，但不限于上述浓度范围。根据本发明实施例，第一区域211的宽度约略等于上述硬掩膜修整步骤时所去除掉的硬掩膜层12的宽度d。
如图16所示，接着进行干刻蚀工艺，以经过修整后的硬掩膜层12作为刻蚀硬掩膜，刻蚀去除全部的掺杂多晶硅层13以及至少刻蚀去除在第一区域211内的外延层11，形成沟槽222，其中，沟槽222的宽度约略等于开口112a的宽度W2，而沟槽222的深度H2大于沟槽122的深度H1，且深度H2可以大于或约略等于外延层11的厚度。需注意，若外延层11为N型，则上述沟槽222刻蚀的深度可以选择性地贯穿或不贯穿外延层11，若外延层11为P型的话，则沟槽222刻蚀的深度必须贯穿外延层11。后续的工艺步骤如同图7至图10所描述，文中故不再复述。
实施例3
图17至图22为依据本实施例所绘示的沟渠式功率晶体管器件的制造方法示意图。如图17所示，同样提供一半导体基底10，其具有第一电性，例如N型重掺杂的硅晶圆，其可作为晶体管器件的漏极。再利用一外延工艺于半导体基底10上形成一外延层11，例如N型外延硅层或P型外延层。
如图18所示，在外延层11表面形成一硬掩膜层12，如氧化硅或氮化硅。然后，利用光刻及刻蚀工艺，于硬掩膜层12中形成开口112a，例如直线形的开口，同样具有宽度W2。接着于开口112a的侧壁上形成侧壁子420，如氧化硅或氮化硅侧壁子，其具有一宽度d(指底部宽度)，且材质与硬掩膜层不同。根据本发明实施例，宽度d可约为0.5微米，但不限于此。
如图19所示，利用干刻蚀工艺，以硬掩膜层12及侧壁子420共同作为刻蚀硬掩膜，经由硬掩膜层12中的开口112a干刻蚀外延层11至一深度H1，形成沟槽122，其中，沟槽122具有宽度W1，而深度H1小于外延层11的厚度。
如图20所示，随后将侧壁子420剥除，显露出部分沟槽122上缘的转角部位122a。根据本发明实施例，宽度d可约为0.5微米，但不限于此。
如图21所示，接着同样于沟槽122中填满掺杂多晶硅层13。根据本发明实施例，掺杂多晶硅层13的电性与外延层11的电性相反，例如，若外延层11为N型，则掺杂多晶硅层13为P型掺杂，若外延层11为P型，则掺杂多晶硅层13为N型掺杂。根据本发明实施例，掺杂多晶硅层13可以覆盖硬掩膜层12。随后，进行一高温扩散工艺，将掺杂多晶硅层13的掺杂物驱入到外延层11中，形成PN交替的超结结构。
此时，扩散进入到外延层11的掺杂区210会包括接近沟槽122表面的第一区域211以及较深入外延层11的第二区域212，其中，第一区域211的掺杂浓度高于第二区域212的掺杂浓度。例如，第一区域211的掺杂浓度约介于1×1017atoms/cm3至1×1019atoms/cm3之间，而第二区域212的掺杂浓度约为1×1016atoms/cm3，但不限于上述浓度范围。根据本发明实施例，第一区域211的宽度约略等于侧壁子420的宽度d。
如图22所示，接着进行干刻蚀工艺，以硬掩膜层12作为刻蚀硬掩膜，去除全部的掺杂多晶硅层13以及至少刻蚀去除在第一区域211内的外延层11，形成沟槽222，其中，沟槽222的宽度约略等于开口112a的宽度W2，而沟槽222的深度H2大于沟槽122的深度H1，且深度H2可以大于或约略等于外延层11的厚度。需注意，若外延层11为N型，则上述沟槽222刻蚀的深度可以选择性地贯穿或不贯穿外延层11，若外延层11为P型的话，则沟槽222刻蚀的深度必须贯穿外延层11。
本发明主要是利用第二次沟渠刻蚀，在刻蚀去除掺杂多晶硅层13的同时去除高浓度的沟渠侧壁，也就是掺杂区210的第一区域211，以提升超结功率器件的电性及良率。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (21)

1.一种半导体功率器件的制作方法，其特征在于，包含：
提供一半导体基底；
于所述半导体基底上形成一外延层；
于所述外延层表面形成一硬掩膜层；
于所述硬掩膜层中形成至少一第一开口；
经由所述第一开口刻蚀所述外延层，形成至少一第一沟槽；
修整所述硬掩膜层，将所述第一开口增宽为一第二开口，并显露出所述第一沟槽上缘的转角部位；
于所述第一沟槽中填满一掺杂层；
进行一高温扩散工艺，将所述掺杂层的掺杂物驱入到所述外延层中，如此于所述第一沟槽内形成一掺杂区，所述掺杂区包括接近所述第一沟槽表面的一第一区域以及较深入所述外延层的一第二区域；以及
进行一干刻蚀工艺，以经过修整后的所述硬掩膜层作为刻蚀硬掩膜，刻蚀去除全部的所述掺杂层以及至少刻蚀去除所述第一区域内的所述外延层，形成一第二沟槽。
2.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，在形成所述第二沟槽后，另包含有：
于所述第二沟槽中填入一硅氧层；
去除所述硬掩膜层；以及
于所述外延层的上表面形成一栅极氧化层以及一栅极。
3.根据权利要求2所述的半导体功率器件的制作方法，其特征在于，在形成所述栅极后，另包含有：
进行一离子注入工艺，于所述外延层中形成一离子井；以及
于所述离子井中形成一源极掺杂区。
4.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述掺杂层为掺杂多晶硅层。
5.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述第一区域的掺杂浓度高于所述第二区域的掺杂浓度。
6.根据权利要求5所述的半导体功率器件的制作方法，其特征在于，所述第一区域的掺杂浓度介于1×1017atoms/cm3至1×1019atoms/cm3之间，而所述第二区域的掺杂浓度为1×1016atoms/cm3。
7.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述第一沟槽的宽度等于所述第一开口的宽度，而所述第一沟槽的深度小于所述外延层的厚度。
8.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述第二沟槽的宽度等于所述第二开口的宽度。
9.根据权利要求8所述的半导体功率器件的制作方法，其特征在于，所述第二沟槽的深度大于所述外延层的厚度。
10.根据权利要求8所述的半导体功率器件的制作方法，其特征在于，所述第二沟槽的深度小于所述外延层的厚度。
11.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述半导体基底为N型重掺杂半导体基底，作为所述半导体功率器件的漏极。
12.根据权利要求11所述的半导体功率器件的制作方法，其特征在于，所述外延层为N型外延硅层，所述掺杂层及所述掺杂区为P型。
13.根据权利要求11所述的半导体功率器件的制作方法，其特征在于，所述外延层为P型外延硅层，所述掺杂层及所述掺杂区为N型。
14.一种半导体功率器件的制作方法，其特征在于，包含有：
提供一半导体基底；
于所述半导体基底上形成一外延层；
于所述外延层表面形成一硬掩膜层；
于所述硬掩膜层中形成至少一第一开口；
于所述第一开口的侧壁上形成一侧壁子；
经由所述第一开口刻蚀所述外延层，形成至少一第一沟槽；
去除所述侧壁子，显露出所述第一沟槽上缘的转角部位；
于所述第一沟槽中填满一掺杂层；
进行一高温扩散工艺，将所述掺杂层的掺杂物驱入到所述外延层中，如此于所述第一沟槽内形成一掺杂区，包括接近所述第一沟槽表面的一第一区域以及较深入所述外延层的一第二区域；以及
进行一干刻蚀工艺，以经过修整后的所述硬掩膜层作为刻蚀硬掩膜，刻蚀去除全部的所述掺杂层以及至少刻蚀去除所述第一区域内的所述外延层，形成一第二沟槽。
15.根据权利要求14所述的半导体功率器件的制作方法，其特征在于，所述掺杂层覆盖在所述硬掩膜层上。
16.根据权利要求14所述的半导体功率器件的制作方法，其特征在于，所述掺杂层为掺杂多晶硅层。
17.根据权利要求14所述的半导体功率器件的制作方法，其特征在于，所述第一区域的掺杂浓度高于所述第二区域的掺杂浓度。
18.根据权利要求17所述的半导体功率器件的制作方法，其特征在于，所述第一区域的掺杂浓度介于1×1017atoms/cm3至1×1019atoms/cm3之间，而所述第二区域的掺杂浓度为1×1016atoms/cm3。
19.根据权利要求14所述的半导体功率器件的制作方法，其特征在于，在形成所述第二沟槽后，另包含有：
于所述第二沟槽中填入一硅氧层；
去除所述硬掩膜层；以及
于所述外延层的上表面形成一栅极氧化层以及一栅极。
20.根据权利要求19所述的半导体功率器件的制作方法，其特征在于，在形成所述栅极后，另包含有：
进行一离子注入工艺，于所述外延层中形成一离子井；以及
于所述离子井中形成一源极掺杂区。
21.一种半导体功率器件的制作方法，其特征在于，包含有：
提供一半导体基底；
于所述半导体基底上形成一外延层；
于所述外延层表面形成一硬掩膜层；
于所述硬掩膜层上形成一光刻胶图案，所述光刻胶图案包含有至少一第一开口；
经由所述第一开口刻蚀所述硬掩膜层，形成至少一第二开口；
修整所述硬掩膜层，将所述第二开口增宽为一第三开口；
经由所述第一开口刻蚀所述外延层，形成至少一第一沟槽；
去除所述光刻胶图案；
于所述第三开口及所述第一沟槽中填满一掺杂层；
进行一高温扩散工艺，将所述掺杂层的掺杂物驱入到所述外延层中，如此于所述第一沟槽内形成一掺杂区，所述掺杂区包括接近所述第一沟槽表面的一第一区域以及较深入所述外延层的一第二区域；以及
进行一干刻蚀工艺，以经过修整后的所述硬掩膜层作为刻蚀硬掩膜，刻蚀去除全部的所述掺杂层以及至少刻蚀去除所述第一区域内的所述外延层，形成一第二沟槽。
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