CN103972096A - 半导体功率器件的制作方法 - Google Patents

半导体功率器件的制作方法 Download PDF

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CN103972096A
CN103972096A CN201310128850.5A CN201310128850A CN103972096A CN 103972096 A CN103972096 A CN 103972096A CN 201310128850 A CN201310128850 A CN 201310128850A CN 103972096 A CN103972096 A CN 103972096A
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林永发
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Anpec Electronics Corp
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Abstract

本发明公开了一种半导体功率器件的制作方法。先提供一半导体基底，其具有多个芯片区域以及芯片区域间的划线区域。再于半导体基底上形成第一外延层。再于第一外延层表面形成硬掩膜层，于硬掩膜层中形成至少一开口，经由开口刻蚀第一外延层，形成至少一沟槽，其中开口及沟槽横跨多个芯片区域及划线区域，使得沟槽的两端都不落在芯片区域内。接着去除硬掩膜层，再于沟槽中填满一第二外延层，并使第二外延层覆盖第一外延层。再将覆盖在第一外延层上的第二外延层抛光去掉，显露出第一外延层。于第一及第二外延层上形成第三外延层。

Description

半导体功率器件的制作方法
技术领域
本发明涉及一种半导体功率器件的制作方法，尤其涉及一种具有超结(super junction)结构的半导体功率器件的制作方法。
背景技术
已知，在功率器件中，其基底的设计通常为P型与N型半导体交替设置，因此在基底中会存在有多个垂直于基底表面的PN结，且这些PN结互相平行，又称为超结结构，这种结构具有耐压低阻抗的优点。
其中的一种超结结构是利用刻蚀出深沟渠，再填入外延层的方式来制作，其具有工艺上简化以及低成本的优点，然而这种技术仍有一些技术问题需要克服，例如，深沟槽内的刻蚀能力以及后续外延工艺所产生的缺陷。
发明内容
本发明的目的，即为提供一种改良的半导体功率器件的制作方法，利用跨芯片区域的沟槽外延工艺，降低一般外延工艺所产生的缺陷，并且可以形成功率器件所使用具有超结结构的基材。
为达上述目的，本发明提出一种半导体功率器件的制作方法，包含有：提供一半导体基底，具有第一电性，其上有多个芯片区域以及介于所述芯片区域之间的划线区域；于所述半导体基底上形成一第一外延层，具有所述第一电性；于所述第一外延层表面形成一硬掩膜层；于所述硬掩膜层中形成至少一开口；经由所述开口刻蚀所述第一外延层，形成至少一沟槽，其中所述开口及所述沟槽横跨所述多个芯片区域以及所述划线区域，使得所述沟槽的两端都不落在所述芯片区域内；去除所述硬掩膜层；于所述沟槽中填满一第二外延层，其具有第二电性，并使第二外延层覆盖所述第一外延层；进行一化学机械抛光工艺，将覆盖在所述第一外延层上的所述第二外延层抛光去除，显露出所述第一外延层；以及于所述第一及第二外延层上形成一第三外延层，其具有所述第一电性。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图8为依据本发明一实施例所绘示的沟渠式功率晶体管器件的制造方法示意图。
图9为依据本发明一实施例所绘示的沟渠式功率晶体管器件的平面示意图。
其中，附图标记说明如下：
10 半导体基底 34a 接触件
11 外延层 100 芯片区域
11a 外延层 110 划线区域
12 硬掩膜层 112 开口
13 外延层 122 沟槽
22 栅极氧化层 122a 沟槽两端
24 栅极 130 离子井
30 层间介电层 132 源极掺杂区
32 阻障层 230 接触孔
34 金属层
具体实施方式
请参阅图1至图8，其为依据本发明一实施例所绘示的沟渠式功率晶体管器件的制造方法示意图。图1可以为图2中沿着切线I-I’所作的横断面。首先，如图1及图2所示，提供一半导体基底10，其具有第一电性，例如N型重掺杂的硅晶圆，其可作为晶体管器件的漏极(drain)。在半导体基底10有多个芯片区域100以及介于芯片区域100之间的划线(scribe lane)区域110(见图2)，上述沟渠式功率晶体管器件即形成在各个芯片区域100内。
首先，利用一外延工艺于半导体基底10上形成一外延层11，例如N型外延硅层。接着，可以在外延层11表面形成一硬掩膜层12，例如，氧化硅或者氮化硅。然后，利用光刻、刻蚀等工艺，于硬掩膜层12中形成开口112。接着将光刻胶去除，然后，利用干刻蚀工艺，经由硬掩膜层12中的开口112，刻蚀外延层11至一预定深度，如此形成沟槽122。
本发明的主要特征在于，如图2所示，上述形成的开口112及沟槽122横跨多个芯片区域100以及划线区域110，使得各个沟槽122的两端122a都不落在芯片区域100内，意即，各个沟槽122的两端122a与芯片区域100不重叠。根据本发明实施例，各个直线条状的沟槽122在一方向(例如参考坐标X轴)为连续的，且横跨数个在所述方向上的同列多个芯片区域100。另外，如图9所示，沟槽122也可以是呈现格栅状或交错的图案，使直线条状的沟槽122在不同的方向(例如参考坐标X轴及参考坐标Y轴)为连续的，且同样横跨数个在各方向上的多个芯片区域100。
由于外延缺陷经常发生在沟槽122的两端122a，这样的做法即可降低外延工艺过程中形成在芯片区域100的介面缺陷。需注意的是，图2中的芯片区域100大小、数量以及沟槽122的数量、形状仅为例示，本发明并非以此为限。此外，除了上述如图1至图4中的作法之外，也可以在N型基底10上先形成第一(P型)外延层11，刻蚀出沟槽122之后，填入第二(N型)外延层13，之后，可以保留高于第一(P型)外延层11上的N型区域(类似11a)，或再抛光至第一(P型)外延层，再形成第三(N型)外延层11a。
需注意的是，若外延层11为N型，上述沟槽122刻蚀的深度可以选择贯穿或不贯穿外延层11，若外延层11为P型的话，则沟槽122刻蚀的深度必须贯穿外延层11。
如图3所示，接着去除硬掩膜层12，并进行外延工艺，于沟槽122中填满外延层13，其具有第二电性，例如P型外延硅层。根据本发明实施例，外延层11与外延层13具有相反的掺质电性。根据本发明实施例，外延层13可以覆盖外延层11。
如图4所示，接着进行化学机械抛光(CMP)工艺，将覆盖在外延层11上的外延层13抛光去除，显露出外延层11。随后，进行另一次的外延工艺，形成外延层11a，其具有上述第一电性，覆盖住外延层11及外延层13。外延层11a电性与外延层11相同，与外延层13相反。根据本发明实施例，外延层11a为N型外延硅层。此时，即完成可用于制作超结结构的半导体基材。
如图5所示，接着，于外延层11a表面形成栅极氧化层22以与栅极24。根据本发明实施例，栅极24可以是多晶硅栅极。根据本发明实施例，栅极24的图案可以是直线型，并以光刻工艺分别将各个芯片区域100内的栅极图案定义出来，加以刻蚀而成。
如图6所示，进行一离子注入工艺，在两栅极24之间的外延层11a中注入具有第二电性(例如P型)掺质，形成离子井130。后续可以进行热驱入(thermal drive-in)工艺。
如图7所示，利用光刻胶及光刻工艺，定义出源极掺杂区域，然后，施以离子注入，将第一电性(例如N型)掺质注入离子井130，形成源极掺杂区132。后续可以进行热驱入工艺。
最后，如图8所示，进行接触孔及金属化工艺，包括形成层间介电层30，于层间介电层30中刻蚀出接触孔230，沉积阻障层32及金属层34，并使金属层34填满接触孔230，构成接触件34a，接触离子井130及源极掺杂区132。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种半导体功率器件的制作方法，其特征在于，包含：
提供一具有第一电性的半导体基底，其上有多个芯片区域以及介于所述芯片区域之间的划线区域；
于所述半导体基底上形成一第一外延层，具有所述第一电性；
于所述第一外延层表面形成一硬掩膜层；
于所述硬掩膜层中形成至少一开口；
经由所述开口，刻蚀所述第一外延层，形成至少一沟槽，其中所述开口及所述沟槽横跨所述多个芯片区域以及所述划线区域，使得所述沟槽的两端都不落在所述芯片区域内；
去除所述硬掩膜层；
于所述沟槽中填满一具有第二电性的第二外延层，并使第二外延层覆盖所述第一外延层；
进行一化学机械抛光工艺，将覆盖在所述第一外延层上的所述第二外延层抛光去除，显露出所述第一外延层；以及
于所述第一及第二外延层上形成一具有所述第一电性的第三外延层。
2.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述第一电性为N型，所述第二电性为P型。
3.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述第一、第二及第三外延层都为外延硅层。
4.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，在形成所述第三外延层后，另包含有以下步骤：
于所述第三外延层上形成一栅极氧化层以及多个栅极；
进行一离子注入工艺，在所述多个栅极之间的所述第三外延层中注入具有所述第二电性的掺质，形成一离子井；以及
于所述离子井中形成一源极掺杂区。
5.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，在形成所述源极掺杂区后，另包含有以下步骤：
形成一层间介电层；
于所述层间介电层中刻蚀出至少一接触孔；以及
沉积一阻障层及一金属层，并使所述金属层填满所述接触孔，构成一接触件。
6.根据权利要求1所述的半导体功率器件的制作方法，其特征在于，所述半导体基底作为所述半导体功率器件的漏极。
7.一种半导体功率器件的制作方法，其特征在于，包含：
提供一半导体基底，具有第一电性，其上有多个芯片区域以及介于所述芯片区域之间的划线区域；
于所述半导体基底上形成一第一外延层，具有第二电性；
于所述第一外延层表面形成一硬掩膜层；
于所述硬掩膜层中形成至少一开口；
经由所述开口，刻蚀所述第一外延层，形成至少一沟槽，其中所述开口及所述沟槽横跨所述多个芯片区域以及所述划线区域，使得所述沟槽的两端都不落在所述芯片区域内；
去除所述硬掩膜层；以及
于所述沟槽中填满一第二外延层，具有所述第一电性，并使第二外延层覆盖所述第一外延层。
8.根据权利要求7所述的半导体功率器件的制作方法，其特征在于，于所述沟槽中填满所述第二外延层后，另包含有以下步骤：
进行一化学机械抛光工艺，将覆盖在所述第一外延层上的所述第二外延层抛光去除，显露出所述第一外延层；以及
于所述第一及第二外延层上形成一第三外延层，具有所述第一电性。
9.根据权利要求7所述的半导体功率器件的制作方法，其特征在于，所述第一电性为N型，所述第二电性为P型。
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