CN103545369B - 功率半导体器件及其制作方法 - Google Patents

功率半导体器件及其制作方法 Download PDF

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CN103545369B
CN103545369B CN201210352599.6A CN201210352599A CN103545369B CN 103545369 B CN103545369 B CN 103545369B CN 201210352599 A CN201210352599 A CN 201210352599A CN 103545369 B CN103545369 B CN 103545369B
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CN103545369A (zh
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林永发
张家豪
石逸群
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Anpec Electronics Corp
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Abstract

本发明公开了一种功率半导体器件，包含有一具有一第一导电型的基材；一半导体层，设在所述基材上，所述半导体层具有第一导电型；多个交替排列的第一导电型掺杂沟槽及第二导电型掺杂沟槽；一第一导电型扩散区，位于各所述第一导电型掺杂沟槽周围的所述半导体层中；以及一第二导电型扩散区，位于各所述第二导电型掺杂沟槽周围的所述半导体层中，其中所述第一导电型扩散区及所述第二导电型扩散区之间构成一PN结，且PN结与所述第一导电型掺杂沟槽的距离等于所述PN结与所述第二导电型掺杂沟槽的距离。

Description

功率半导体器件及其制作方法
技术领域
本发明涉及一种功率半导体器件，特别是一种超结(superjunction)功率半导体器件及其制作方法。
背景技术
功率半导体器件常应用于电源管理，例如，开关式电源供应器、计算机中心或周边电源管理IC、背光板电源供应器或马达控制等等用途，其种类包含有绝缘栅双极性晶体管(insulated-gatebipolartransistor,IGBT)、金属氧化物半导体场效应晶体管(metal-oxide-semiconductorfield-effecttransistor,MOSFET)与双极性结型晶体管(bipolarjunctiontransistor,BJT)等器件。其中，又以MOSFET较节省电能且可提供较快的器件开关速度。
在传统MOSFET功率器件中，为了高耐压因而增加漂移层(driftlayer)的厚度以及降低其掺杂浓度来提升功率器件的耐压能力，但漂移层同时也是晶体管导通时的电流路径，因此，降低漂移层的掺杂浓度以及增加厚度虽然可以提升器件耐压特性，也导致了导通电阻(Rds,on)上升。因此，发展出超结结构(superjunction)，即交互的N型与P型结构，作为功率器件的漂移层，以兼顾器件的耐压及导通电阻特性。
然而，习用的超结功率器件仍有许多缺点需要改进，例如，N型与P型的浓度分布不对称，导致电荷失衡问题。于是，所述技术领域仍需要一种改良的超结功率半导体器件，在不影响其耐压特性下，能形成对称的N型与P型的浓度梯度分布，以解决电荷失衡问题，并进一步降低导通电阻。
发明内容
本发明的主要目的在提供一种改良的超结功率半导体器件，以解决先有技术的不足与缺点。
根据本发明的实施例，本发明提供了一种功率半导体器件，包含有一具有一第一导电型的基材；一半导体层，设在所述基材上，所述半导体层具有第一导电型；多个交替排列的第一导电型掺杂沟槽及第二导电型掺杂沟槽；一第一导电型扩散区，位在各所述第一导电型掺杂沟槽周围的所述半导体层中；以及一第二导电型扩散区，位在各所述第二导电型掺杂沟槽周围的所述所述半导体层中，其中所述第一导电型扩散区及所述第二导电型扩散区之间构成一PN结，且所述PN结与所述第一导电型掺杂沟槽的距离等于所述PN结与所述第二导电型掺杂沟槽的距离。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附图式，作详细说明如下。然而下述的优选实施方式与图式仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图13为依据本发明一实施例所绘示的超结功率半导体器件的制作方法的示意图。
图14至图18为依据本发明另一实施例所绘示的超结功率半导体器件的制作方法的示意图。
其中，附图标记说明如下：
10半导体基材150侧护壁
10a主表面200PN结
11半导体层220P型扩散区
11a表面222N型扩散区
12硬掩膜层230中心线
14光刻胶层340栅极凹陷沟槽
16光刻胶层360栅极氧化层
18光刻胶层380多晶硅层
20P型掺杂区400沟渠栅极
22N型掺杂区420P型井
112开口500N+源极
114第一沟槽610介电层
114’第二沟槽610a接触开口
116开口616掺质
118开口620阻障层
120衬垫层630接触金属层
130沟渠填充介电层700功率器件单元
具体实施方式
在下文的细节描述中将参照附图来说明本发明的实施例，故该些附图中的内容也构成说明书细节描述的一部份，并且以可实行本发明实施例的特例描述方式来绘示。下文实施例已描述有足够的细节可使所属领域的一般技术人员得以具以实施。阅者须了解到本发明中亦可实行其它的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、步骤顺序上及电性上的改变。因此，下文中的细节描述将不被视为是一种限定，反之，其中所包含的实施例将由权利要求书来加以界定。
特定来说，本发明是关于一种双掺杂式沟渠型超结功率半导体器件及其制作方法，其中，制作方法部分是采分别实施N型、P型离子注入，再刻蚀形成柱状掺杂区为例说明。当然，本发明不限于此种实施方式，其它方法，诸如，斜角度离子注入法、反复垂直离子注入及刻蚀法或扩散掺杂法亦可以实施。以下，将借由图式说明本发明的一具体实施例，其中，图式中所绘示者主要是针对沟渠栅极式MOS结构例示说明，本领域的一般技术人员应能理解本发明也能应用在沟渠栅极式MOS结构以外种类的半导体功率器件的制作，例如，平面栅极式MOS结构。
请参阅图1至图14，其为依据本发明一实施例所绘示的超结功率半导体器件的制作方法的示意图。如图1所示，首先提供一具有一第一导电型的基材或半导体基材10，例如，N＋硅基材，再于半导体基材10的主表面10a上形成一半导体层11，例如，P型硅外延层或N型硅外延层。根据本发明实施例，半导体层11为一N型硅外延层11，其厚度t约为5微米(μm)至100微米之间，例如，45微米左右，但不限于此。根据本发明实施例，半导体层11较佳为轻掺杂外延层，其掺杂浓度小于1014原子/立方公分(atoms/cm3)。
如图2所示，随后，于半导体层11的表面上形成一硬掩膜图案12，包括开口112，显露出部分的半导体层11的表面11a，其中，开口112是用以定义出后续欲刻蚀至半导体层11的深沟渠的位置。根据本发明实施例，硬掩膜图案12可以是硅氧层、硅氮层等单一层或复合层结构，但不限于此。硬掩膜的图案化可以利用光刻胶层14，并利用光刻工艺形成，细节不另赘述。此时，在硬掩膜图案12中形成的开口112可再区分为多个第二导电型掺杂开口及第一导电型掺杂开口，例如P型掺杂开口及N型掺杂开口，彼此交替排列。
如图3所示，接着进行一各向异性干法刻蚀工艺，经由开口112刻蚀部分的半导体层11，形成多个第一沟槽114。同样的，第一沟槽114可区分为P型掺杂沟槽及N型掺杂沟槽，彼此交替排列。之后去除光刻胶层14。
如图4所示，接着，于半导体层11上全面性地形成一光刻胶层16，使其填入各个第一沟槽114，并且覆盖硬掩膜图案12，再以光刻工艺于光刻胶层16中形成开口116，使开口116仅显露出多个第一沟槽114中的P型掺杂沟槽。此时，图案化之后的光刻胶层16仍遮盖住多个第一沟槽114中的N型掺杂沟槽。接着，进行多次的离子注入工艺，例如，利用不同能量的离子注入，经由显露出来的多个第一沟槽114中的P型掺杂沟槽，于半导体层11中形成多个相对应的P型掺杂区20。随后，将光刻胶层16去除。
接着，如图5所示，于半导体层11上全面性地形成另一光刻胶层18，使其填入各个第一沟槽114，并且覆盖硬掩膜图案12，再以光刻工艺于光刻胶层18中形成开口118，使开口118仅显露出多个第一沟槽114中的N型掺杂沟槽。此时，图案化之后的光刻胶层18仍遮盖住多个第一沟槽114中的P型掺杂沟槽。接着，进行多次的离子注入工艺，例如，利用不同能量的离子注入，经由显露出来的多个第一沟槽114中的N型掺杂沟槽，于半导体层11中形成多个相对应的N型掺杂区22。随后，将光刻胶层18去除。当然，图4及图5中的步骤顺序可以互换，且P型掺杂区20及N型掺杂区22彼此交替排列。
如图6所示，在依序完成P型掺杂区20及N型掺杂区22之后，随即进行第二次的各向异性干法刻蚀工艺，例如以硬掩膜图案12作为刻蚀停止层，经由多个第一沟槽114继续刻蚀半导体层11，形成多个深度直达半导体基材10的第二沟槽114’。根据此实施例，各第二沟槽114’分别贯穿相对应的P型掺杂区20及相对应的N型掺杂区22。在其它实施例中，也可不贯穿P型掺杂区20及N型掺杂区22。
如图7所示，在完成第二沟槽114’的制作后，接着于各第二沟槽114’的底部以及垂直侧壁上分别形成一衬垫层120，例如，硅氧层。根据本发明的优选实施例，衬垫层120可以是介电层，并以热氧化方式形成者，但不限于此。接着，进行一化学气相沉积(chemicalvapordeposition,CVD)工艺，全面性地沉积一沟渠填充介电层130，例如，硅氧层，使其填满深沟渠114’，并均厚沉积在硬掩膜图案12上。接着进行一化学机械抛光工艺，先磨掉部分的沟渠填充介电层130，再去除硬掩膜图案12。
如图8所示，随后，继续进行一热驱入工艺，使各P型掺杂区20及各N型掺杂区22扩散，分别形成相对应的P型扩散区220及相对应的N型扩散区222，并且在相邻的P型扩散区220及N型扩散区222之间构成一PN结200。根据本发明实施例，PN结200距离相邻的第二沟槽114’的中心线230的距离分别为d1及d2，其中，d1约略等于d2，但也可不相等。其浓度分布为往PN结200处越低而约略呈现一对称的梯度分布。
如图9所示，利用一光刻胶层(图未示)覆盖住半导体层11，再以光刻工艺于光刻胶层中形成开口(图未示)，仅显露出多个第二沟槽114’中的N型掺杂沟槽，接着，进行一刻蚀工艺，例如湿法刻蚀工艺，去除部分显露出来的沟渠填充介电层130，形成多个栅极凹陷沟槽340，且于一垂直方向上，栅极凹陷沟槽340的底部约略切齐于N型扩散区222的顶部。随后，去除光刻胶层。
如图10所示，接着，进行一热氧化工艺，在显露出来的半导体层11的表面上，包括半导体层11的表面11a以及各栅极凹陷沟槽340表面，形成栅极氧化层360，然后，进行一化学气相沉积工艺，于半导体层11上全面性地沉积一导体层，例如一多晶硅层380，并使多晶硅层380填满各栅极凹陷沟槽340。
如图11所示，接下来，可以进行一抛光工艺或者刻蚀工艺，将多晶硅层380平坦化，并显露出半导体层11的表面11a上的各栅极氧化层360，如此便可使导体层于栅极凹陷沟槽340自动对准形成功率器件的沟渠栅极400。接着，进行P型井掺杂工艺，于半导体层11的表面11a形成P型井420。
如图12所示，完成P型井420掺杂后，接着再以一光刻胶层(图未示)定义出源极掺杂区域，并进行N+掺杂工艺，于沟渠栅极400两侧的P型井420中形成N+源极500。随后，去除光刻胶层，接着，可再进行一热驱入工艺，以活化掺质。
如图13所示，最后进行接触器件的作法。首先，全面沉积一介电层610，再以光刻工艺于介电层610中形成多个接触开口610a，显露出部分的P型井420以及部分的N+源极500。可另外进行一离子注入工艺，经由接触开口610a于P型井420中植入预定浓度的掺质616，以降低接触电阻。接着，全面沉积一阻障层620，例如，钛/氮化钛金属层，接着，沉积一接触金属层630，使其填满接触开口610a。在图13中，特别以虚线标示出功率器件单元700。
请参阅图14至图18，其为依据本发明另一实施例所绘示的超结功率半导体器件的制作方法的示意图，其中，图14接续图3的步骤。如图14所示，形成多个第一沟槽114之后，于各第一沟槽114的侧壁上分别形成一侧护壁150。根据本发明实施例，侧护壁150可以是由氮化硅或氧化硅所构成。
接着，如图15所示，步骤类似图4，于半导体层11上形成一光刻胶层16，使其填入多个第一沟槽114，并且覆盖硬掩膜图案12，再以光刻工艺于光刻胶层16中形成开口116，使开口116仅显露出多个第一沟槽114中的P型掺杂沟槽。此时，图案化之后的光刻胶层16仍遮盖住多个第一沟槽114中的N型掺杂沟槽。接着，进行多次的离子注入工艺，例如，利用不同能量的离子注入，经由显露出来的多个第一沟槽114中的P型掺杂沟槽，于半导体层11中形成多个相对应的P型掺杂区20。随后，将光刻胶层16去除。
如图16所示，步骤类似图5，于半导体层11上形成一光刻胶层18，使其填入多个第一沟槽114，并且覆盖硬掩膜图案12，再以光刻工艺于光刻胶层18中形成开口118，使开口118仅显露出多个第一沟槽114中的N型掺杂沟槽。此时，图案化之后的光刻胶层18仍遮盖住多个第一沟槽114中的P型掺杂沟槽。接着，进行多次的离子注入工艺，例如，利用不同能量的离子注入，经由显露出来的多个第一沟槽114中的N型掺杂沟槽，于半导体层11中形成多个相对应的N型掺杂区22。随后，将光刻胶层18去除。图15及图16中的步骤顺序可以互换，且P型掺杂区20及N型掺杂区22彼此交替排列。
如图17所示，在依序完成P型掺杂区20及N型掺杂区22之后，随即进行第二次的各向异性干法刻蚀工艺，例如以各硬掩膜图案12与各侧护壁150作为蚀刻停止层，经由多个第一沟槽114继续刻蚀半导体层11，形成多个深度直达半导体基材10的第二沟槽114’。
接着，如图18所示，在完成第二沟槽114’的制作后，接着去除各侧护壁150，再于各第二沟槽114’的底部以及垂直侧壁上分别形成一衬垫层120，例如，硅氧层。根据本发明的优选实施例，衬垫层120可以是介电层，并以热氧化方式形成者，但不限于此。接着，进行一化学气相沉积工艺，全面性地沉积一沟渠填充介电层130，例如，硅氧层，使其填满各深沟渠114’，并均厚沉积在硬掩膜图案12上。接着进行一化化学机械抛光工艺，先磨掉部分的沟渠填充介电层130，再去除硬掩膜图案12。后续步骤则类似图8至图13，不另赘述。
综上所述，本发明双掺杂式沟渠型超结功率半导体器件其特征在于利用形成在N型掺杂沟槽之间的P型掺杂沟槽，并经由N型掺杂沟槽及P型掺杂沟槽分别进行离子注入工艺，形成超结结构，其中，P型扩散区220及N型扩散区222的浓度分布呈现一对称的梯度分布。此外，结构上的特征包括：P型扩散区220及N型扩散区222之间构成一PN结200，PN结200距离相邻的第二沟槽114’的距离约略相等。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (8)

1.一种功率半导体器件，其特征在于，包含有：
一基材，具有一第一导电型；
一半导体层，设在所述基材上，所述半导体层具有所述第一导电型；
多个沟槽，位于所述半导体层中，其中周围的所述半导体层包含一第一导电型扩散区的沟槽为第一导电型掺杂沟槽，周围的所述半导体层包含一第二导电型扩散区的沟槽为第二导电型掺杂沟槽，其中所述第一导电型掺杂沟槽与所述第二导电型掺杂沟槽交替排列；
一PN结，位于所述第一导电型扩散区及所述第二导电型扩散区之间，且所述PN结与所述第一导电型掺杂沟槽的距离等于所述PN结与所述第二导电型掺杂沟槽的距离。
2.根据权利要求1所述的功率半导体器件，其特征在于，另包含一沟渠栅极，位于各个所述第一导电型掺杂沟槽内。
3.根据权利要求1所述的功率半导体器件，其特征在于，另包含一第一导电型源极，设在所述第一导电型掺杂沟槽周围的所述半导体层。
4.根据权利要求1所述的功率半导体器件，其特征在于，所述第一导电型为N型，所述第二导电型为P型。
5.根据权利要求1所述的功率半导体器件，其特征在于，所述基材为一N+硅基材。
6.根据权利要求1所述的功率半导体器件，其特征在于，所述半导体层为N型硅外延层。
7.根据权利要求1所述的功率半导体器件，其特征在于，所述半导体层为轻度掺杂外延层，其掺杂浓度小于1014atoms/cm3。
8.根据权利要求1所述的功率半导体器件，其特征在于，所述第一导电型扩散区及所述第二导电型扩散区呈现一对称的梯度分布。
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