CN103035668A - 横向堆叠超级接面功率半导体装置 - Google Patents
横向堆叠超级接面功率半导体装置 Download PDFInfo
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Abstract
本发明公开了一种横向堆叠超级接面功率半导体装置,包括一半导体基底;一外延堆叠结构,设于半导体基底上,外延堆叠结构包括至少一第一外延层,具有一第二导电型,及至少一第二外延层,具有第一导电型;一漏极结构,嵌入于外延堆叠结构中,且漏极结构沿着一第一方向延伸;多个栅极结构,嵌入外延堆叠结构中,并且断续的沿着第一方向延伸;一源极结构,设于多个栅极结构间;及一离子井,具有第一导电型,包围住源极结构。
Description
技术领域
本发明涉及一种半导体功率装置,特别是涉及一种横向堆叠超级接面(Super Junction)功率半导体装置。
背景技术
半导体功率装置常应用于电源管理的部分,例如切换式电源供应器、计算机中心或周边电源管理IC、背光板电源供应器或马达控制等等用途,其种类包含有绝缘栅双极型晶体管(insulated gate bipolar transistor,IGBT)、金氧半场效晶体(metal-oxide-semiconductor field-effect transistor,MOSFET)与双极型接面晶体管(bipolar junction transistor,BJT)等装置。其中,由于MOSFET可节省电能而且可以提供较快的装置切换速度,因此被广泛地应用各领域中。
在公知的功率装置中,基底的设计是P型外延层和N型外延层交替设置,因此在基底中会存在有多个垂直在基底表面的PN接面,而且这些PN接面互相平行,所以又被叫做超级接面结构。在现有制作超级接面结构的技术中,是先在一第一导电型基材(如:N型基材)上成长一第一导电型外延层(如:N型外延层),然后利用一第一掩模在第一导电型外延层上蚀刻出多个沟渠,接着在各沟渠内形成一第二导电型外延层(例如:P型外延层),并使第二导电型外延层的上表面和第一导电型外延层的上表面对齐,接着,进行一热驱入工艺,将第二导电型外延层的掺质扩散到各沟渠周围的N型基底中。这个时候,会形成环绕各沟渠的第二导电型基体掺杂区。而第二导电型外延层和第一导电型外延层的多个接触面即形成超级接面结构。
比较上述具有超级接面的功率装置和没有超级接面的功率装置,在相同耐压条件下,虽然具有较低的导通电阻,但是相对于高功率装置的绝缘栅极控制双极型晶体管(IGBT)来说,却是有较高的导通电阻。如果要达到与高功率装置的绝缘栅极控制双极型晶体管相同导通电阻,则需要制作出更高深宽比的超级接面,但是,以现有技术来说,高深宽比超级接面的工艺难度高,而且成本也较高。
发明内容
本发明的主要目的在提供一种横向堆叠超级接面功率半导体装置,可以解决先前技艺的不足与缺陷。
根据本发明的一优选实施例,提供一种横向堆叠超级接面功率半导体装置,包括一半导体基底;一外延堆叠结构,设于半导体基底上,外延堆叠结构包括至少一第一外延层,具有一第二导电型,及至少一第二外延层,具有第一导电型;一漏极结构,嵌入于外延堆叠结构中,且漏极结构沿着一第一方向延伸;多个栅极结构,嵌入外延堆叠结构中,并且断续的沿着第一方向延伸;一源极结构,设于多个栅极结构间;及一离子井,具有第一导电型,包围住源极结构。
根据本发明的另一优选实施例,提供一种横向堆叠超级接面功率半导体装置,包括一半导体基底,具有一第一导电型;一外延堆叠结构,设于半导体基底上,外延堆叠结构包括至少一第一外延层,具有一第二导电型,及至少一第二外延层,具有第一导电型;一漏极结构,嵌入于外延堆叠结构中,且漏极结构沿着一第一方向延伸;一栅极结构,嵌入于外延堆叠结构中,并且沿着第一方向延伸;一源极结构,设于栅极结构的一侧;及一离子井,具有第一导电型,包围住源极结构。
为让以上提到的目的、特征及优点能更容易被了解,下面特别写出优选实施方式,并配合附图,详细说明如下。然而下面的优选实施方式和附图仅供参考与说明,并非用来对本发明加以限制。
附图说明
图1A是本发明第一优选实施例的横向堆叠超级接面功率半导体装置的立体剖面侧视图。
图1B是第一优选实施例的横向堆叠超级接面功率半导体装置的上视示意图。
图2是第二优选实施例的横向堆叠超级接面功率半导体装置的上视示意图。
图3是第三优选实施例的横向堆叠超级接面功率半导体装置的上视示意图。
图4是第一优选实施例的横向堆叠超级接面功率半导体装置的部分布局示意图。
图5到图16是横向堆叠超级接面功率半导体装置的制作方法。
应注意的是,所有的附图皆是概略性的。为了方便和清晰,附图的相对尺寸和部分零件比例是以夸大或缩小规模呈现。相同的标记是用来在不同的实施例中指示相对应或类似的装置。
其中,附图标记说明如下:
1 横向堆叠超级接面功率半 10 半导体基底
导体装置
12 外延堆叠结构 14 栅极导电层
15 栅极介电层 16 漏极结构
18 源极结构 121 第二导电型外延层
122 第一导电型外层 140 栅极沟渠
140a 底部 140b 侧壁
160 漏极沟渠 161 重掺杂漏极扩散区
162 漏极接触层 180 源极沟渠
181 重掺杂源极扩散区 182 源极接触层
200 离子井沟渠 201 离子井
202 离子井接触层 210 栅极通道
300 电流路径 412 氧化衬垫层
414 氮化衬垫层 416 硬掩模层
512 氧化衬垫层 514 硅氧层
522 钛/氮化钛衬垫层 524 钨金属层
600 介电层 614 栅极接触洞
616 漏极接触洞 618 源极接触洞
620 离子井接触洞 622 钛/氮化钛衬垫层
624 金属层 700 介电层
714 栅极插塞介层洞 716 漏极插塞介层洞
722 钛/氮化钛衬垫层 724 金属层
C14 栅极接触插塞 C16 漏极接触插塞
C18 源极接触插塞
具体实施方式
虽然本发明以优选实施例揭露如下,然其并非用来限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围以权利要求书所界定的为标准,为了不使本发明的精神难懂,部分公知结构与工艺步骤的细节将不在此揭露。
同样地,图示所表示为优选实施例中的装置示意图,但并非用来限定装置的尺寸,特别是,为使本发明可更清晰地呈现,部分组件的尺寸可能放大呈现在图中。再者,多个优选实施例中所揭示相同的组件者,将标示相同或相似的符号以使说明更容易且清晰。
参考图1A及图1B,图1A是本发明第一优选实施例的横向堆叠超级接面功率半导体装置的立体剖面侧视图,图1B是一上视示意图。如图1A及第图1B,横向堆叠超级接面功率半导体装置1包括一第一导电型的半导体基底10,例如P型硅基底,在半导体基底10上设有一外延堆叠结构12,具有第二导电型,例如N型,的外延层121及一具有第一导电型的外延层122,使外延层121及外延层122沿着参考z轴向上重复交替堆叠的结构,且外延层121及外延层122构成多个横向PN超级接面,也就是说,横向PN超级接面平行半导体基底10的表面(或x-y平面)。上述外延层121及外延层122的厚度可以相同,也可以不相同。举例来说,与半导体基底10直接接触的外延层121可以比其它层的外延层121的厚度更厚,借此降低阻值。除此之外,上述外延层堆叠可先堆叠外延层121或先堆叠外延层122在半导体基底10上,将根据后续掺杂的浓度及厚度来调整。
在外延堆叠结构12中设有一沿着参考y轴延伸的漏极沟渠160,且在漏极沟渠160两侧壁各设有一第二导电型的重掺杂漏极扩散区161,在漏极沟渠160内则是填满漏极接触层162,例如金属。漏极沟渠160的底部向下深入到半导体基底10,且重掺杂漏极扩散区161与漏极接触层162构成一漏极结构16。根据本发明的另一优选实施例,漏极沟渠160的深度也可调整,使其不暴露出半导体基底10,而只暴露出与半导体基底10直接接触的外延层121。
在漏极结构16的相对侧,设有一沿着参考y轴延伸的栅极沟渠140,其具有底部140a及侧壁140b,其特征在于底部140a可以暴露出半导体基底10。同样的,根据本发明的另一优选实施例,栅极沟渠140的深度也可调整,使其不暴露出半导体基底10,而只暴露出与半导体基底10直接接触的外延层121。在栅极沟渠140的底部140a及侧壁140b上栅极沟渠140形成有一栅极介电层15,在栅极介电层15上则形成有一栅极导电层14。根据本发明的优选实施例,栅极沟渠140是沿着参考y轴断续的延伸,且在相邻的栅极沟渠140间,设有一源极沟渠180,其深度与漏极沟渠160大体相同,在源极沟渠180则形成有一第二导电型的重掺杂源极扩散区181。在源极沟渠180内则是填满源极接触层182,例如金属。
重掺杂源极扩散区181与源极接触层182构成一源极结构18。重掺杂源极扩散区181被一第一导电型的离子井201包围,在离子井201内设有一离子井沟渠200,其深度与漏极沟渠160或源极沟渠180大体相同,在离子井沟渠200内则是填满离子井接触层202,例如金属。离子井201与栅极导电层14重叠处,与重掺杂源极扩散区181间形成一栅极通道210,其定义一栅极长度,而各层的外延层121则定义出一栅极宽度。图1A中也画出导通时,电流从漏极结构16经由各层的外延层121再经由栅极通道210流向源极结构18的路径300。
图2是根据第二优选实施例的横向堆叠超级接面功率半导体装置的上视示意图,且相同的层、装置、区域仍沿用相同的标记表示。比较图1B,图2的源极沟渠180在参考x轴方向上较宽,使填入源极沟渠180内的源极接触层182,例如金属,可以直接接触到包围源极结构18的离子井201。第二导电型的重掺杂源极扩散区181则是成对形成在源极沟渠180的相对两侧壁上。离子井201内不需另外设置离子井沟渠。离子井201与栅极导电层14重叠处,与重掺杂源极扩散区181间形成一栅极通道210,其定义一栅极长度,而各层的外延层121则定义出一栅极宽度。
图3是本发明第三优选实施例的横向堆叠超级接面功率半导体装置的上视示意图,且相同的层、装置、区域仍沿用相同的标记表示。如图3,栅极沟渠140是是一连续的沟渠,且沿着参考y轴延伸。源极结构18是位在栅极沟渠140的一侧,其包括一对第二导电型的重掺杂源极扩散区181,并且其一紧邻栅极沟渠140的一侧。在第二导电型的重掺杂源极扩散区181间是一源极沟渠180,在源极沟渠180内则填满源极接触层182,例如金属。重掺杂源极扩散区181与源极接触层182构成源极结构18。同样的,重掺杂源极扩散区181被一第一导电型的离子井201包围住,在离子井201内不需设置离子井沟渠。源极接触层182与离子井201直接接触并电连接在一起。离子井201与栅极导电层14重叠处,与重掺杂源极扩散区181间形成一栅极通道210,其定义一栅极长度,而各层的外延层121则定义出一栅极宽度。
以下,将借由图4到图16详细说明本发明横向堆叠超级接面功率半导体装置的制作方法。图4是本发明第一优选实施例的横向堆叠超级接面功率半导体装置的部分布局示意图,图5到图16则是图4中沿着切线I-I’及II-II’的剖面示意图,且切线I-I’是沿着参考y轴横断栅极14及源极结构18,而切线II-II’是沿着参考x轴横断离子井201、源极结构18及漏极结构16。
如图5,首先提供一具有第一导电型的半导体基底10,例如,P型硅基底。接着,在半导体基底10上形成一外延堆叠结构12,其具有第二导电型,例如N型,的外延层121及一具有所述的第一导电型的外延层122,使外延层121及外延层122沿着参考z轴向上重复交替堆叠的结构,且所述的外延层121及外延层122构成多个横向PN超级接面。所述的横向PN超级接面平行半导体基底10的表面(或x-y平面)。上述外延层121及外延层122的厚度可以相同,也可以不相同。举例来说,与半导体基底10直接接触的外延层121的厚度d0可以较其它层的外延层121厚度d1更厚,借此降低阻值。除此之外,可以根据所要达到的导通电阻(RDS(ON)),调整外延堆叠结构12的整体厚度、外延层121或外延层122的层数等。
如图6,在外延堆叠结构12上依序形成一氧化衬垫层412、一氮化衬垫层414及一硬掩模层416。然后,利用光刻工艺和蚀刻工艺,在预定区域分别蚀刻出栅极沟渠140、源极沟渠180、漏极沟渠160及离子井沟渠200。如前所述,栅极沟渠140、源极沟渠180、漏极沟渠160及离子井沟渠200的深度可调整,使其暴露半导体基底10,或者不暴露出半导体基底10,而只暴露出与半导体基底10直接接触的外延层121。而漏极沟渠160至离子井沟渠200的距离将决定装置的耐压。
如图7,接下来,将硬掩模层416去除,留下氧化衬垫层412及氮化衬垫层414。然后,进行一氧化工艺,在栅极沟渠140、源极沟渠180、漏极沟渠160及离子井沟渠200的表面形成一牺牲氧化层(图未示),之后,将所述的牺牲氧化层去除。此步骤的目的在去除先前蚀刻步骤所产生的缺陷。
如图8,接着以光刻工艺在外延堆叠结构12上形成一光致抗蚀剂图案(图未示),所述的光致抗蚀剂图案暴露出形成离子井201的区域。接着,进行一斜角度离子注入工艺,将第一导电型掺质,例如P型掺质,植入外延堆叠结构12,俾形成第一导电型离子井201。然后,将光致抗蚀剂图案去除,然后进行第一导电型离子井201的热驱入工艺。当然,在其它优选实施例中,也可以利用扩散方式取代上述的离子注入工艺。
如图9,接着以光刻工艺在外延堆叠结构12上形成另一光致抗蚀剂图案(图未示),所述的光致抗蚀剂图案暴露出形成源极及漏极掺杂的区域。接着,进行一斜角度离子注入工艺,将第二导电型掺质,例如N型掺质,注入外延堆叠结构12,俾形成重掺杂漏极扩散区161及重掺杂源极扩散区181。然后,将光致抗蚀剂图案去除,然后进行热驱入工艺。当然,在其它实施例中,也可以利用扩散方式取代上述的离子注入工艺。除此之外,此例是同时形成源极及漏极掺杂区,也可以依不同的掺杂浓度需求,分开形成源极及漏极掺杂区。
如图10,进行一沟渠氧化工艺,在栅极沟渠140、源极沟渠180、漏极沟渠160及离子井沟渠200的表面形成一氧化衬垫层512,然后,进行一化学气相沉积工艺,在栅极沟渠140、源极沟渠180、漏极沟渠160及离子井沟渠200填入一硅氧层514,并进行平坦化。然后,在外延堆叠结构12上形成一光致抗蚀剂图案(图未示),其暴露出栅极沟渠140,但覆盖住源极沟渠180、漏极沟渠160及离子井沟渠200等栅极沟渠140以外的区域。然后,再将栅极沟渠140内的硅氧层514及氧化衬垫层512去除。接下来,去除光致抗蚀剂图案。
如图11,进行一氧化工艺,在栅极沟渠140内的表面上形成一栅极介电层15,例如二氧化硅。然后,进行一化学气相沉积工艺,在栅极沟渠140内填入一栅极导电层14,例如多晶硅层。接下来,进行一化学机械抛光工艺,将沉积在栅极沟渠140外的栅极导电层14去除并平坦化。
如图12,以光刻工艺在外延堆叠结构12上形成一光致抗蚀剂图案(图未示),所述的光致抗蚀剂图案只覆盖住栅极沟渠140及形成在栅极沟渠140内的栅极导电层14,暴露出源极沟渠180、漏极沟渠160及离子井沟渠200的硅氧层514,接着,去除源极沟渠180、漏极沟渠160及离子井沟渠200的硅氧层514及氧化衬垫层512。然后,去除光致抗蚀剂图案。然后,在外延堆叠结构12上全面沉积一钛/氮化钛衬垫层522,然后再在钛/氮化钛衬垫层522上沉积一钨金属层524。接着,进行一化学机械抛光工艺,将沉积在源极沟渠180、漏极沟渠160及离子井沟渠200外的金属层去除并平坦化。
如图13,接着,在外延堆叠结构12上沉积一介电层600,如硅氧层。然后,在介电层600上形成一光致抗蚀剂图案(图未示),所述的光致抗蚀剂图案暴露出欲形成接触洞的位置,所述的接触洞分别位在栅极沟渠140、源极沟渠180、漏极沟渠160及离子井沟渠200的正上方。接着,利用所述的光致抗蚀剂图案当作蚀刻掩模,进行一干蚀刻工艺,在介电层600形成栅极接触洞614、漏极接触洞616、源极接触洞618及离子井接触洞620,分别暴露出填入在栅极沟渠140的栅极导电层14、填入在源极沟渠180、漏极沟渠160及离子井沟渠200的钨金属层524。接下来,去除光致抗蚀剂图案。
如图14,在介电层600上沉积一钛/氮化钛衬垫层622,然后再在钛/氮化钛衬垫层622上沉积一金属层624,例如铝硅铜合金等。然后,进行一光刻及蚀刻工艺,将金属层624及钛/氮化钛衬垫层622图案化,分别形成栅极接触插塞C14、漏极接触插塞C16、源极接触插塞C18,其中,源极接触插塞C18同时电连接填入在源极沟渠180及离子井沟渠200的钨金属层524。
如图15,接着,在介电层600上沉积一介电层700,如硅氧层,使介电层700覆盖住栅极接触插塞C14、漏极接触插塞C16、源极接触插塞C18。然后,在介电层700上形成一光致抗蚀剂图案(图未示),所述的光致抗蚀剂图案暴露出欲形成介层洞的位置,所述的些介层洞分别位在栅极接触插塞C14以、漏极接触插塞C16及源极接触插塞C18(图未示)的正上方。接着,利用所述的光致抗蚀剂图案当作蚀刻掩模,进行一干蚀刻工艺,在介电层700形成栅极插塞介层洞714、漏极插塞介层洞716,分别暴露出栅极接触插塞C14及漏极接触插塞C16。接下来,去除光致抗蚀剂图案。
如图16,在介电层700上沉积一钛/氮化钛衬垫层722,然后在钛/氮化钛衬垫层722上沉积一金属层724,例如铝硅铜合金等。然后,进行一光刻工艺及蚀刻工艺,将金属层724及钛/氮化钛衬垫层722图案化,而形成导线图案。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (20)
1.一种横向堆叠超级接面功率半导体装置,其特征在于包括:
一半导体基底,具有一第一导电型;
一外延堆叠结构,设于所述半导体基底上,所述外延堆叠结构包括至少一第一外延层,具有一第二导电型,及至少一第二外延层,具有所述第一导电型;
一漏极结构,嵌入于所述外延堆叠结构中,且所述漏极结构沿着一第一方向延伸;
多个栅极结构,嵌入所述外延堆叠结构中,并且断续的沿着所述第一方向延伸;
一源极结构,设于所述多个栅极结构间;及
一离子井,具有所述第一导电型,包围住所述源极结构。
2.根据权利要求1所述横向堆叠超级接面功率半导体装置,其特征在于各所述栅极结构包括一栅极导电层,埋入于一栅极沟渠中,及一栅极介电层,包覆着所述栅极导电层。
3.根据权利要求2所述的横向堆叠超级接面功率半导体装置,其特征在于所述源极结构包括一源极扩散区、一源极沟渠,位于所述的源极扩散区内,及一源极接触层,填满所述源极沟渠。
4.根据权利要求3所述的横向堆叠超级接面功率半导体装置,其特征在于所述离子井与所述栅极导电层重叠处,与所述源极扩散区间形成一栅极通道。
5.根据权利要求4所述的横向堆叠超级接面功率半导体装置,其特征在于所述的栅极通道导通时,于所述第一外延层形成一第二方向的电流路径。
6.根据权利要求1所述的横向堆叠超级接面功率半导体装置,其特征在于所述第一外延层与所述第二外延层构成一平行于所述半导体基底表面的PN接面。
7.根据权利要求1所述的横向堆叠超级接面功率半导体装置,其特征在于所述第一外延层与所述半导体基底直接接触。
8.根据权利要求7所述的横向堆叠超级接面功率半导体装置,其特征在于所述第二外延层叠设于所述第一外延层上。
9.根据权利要求1所述的横向堆叠超级接面功率半导体装置,其特征在于所述第一外延层的厚度不等于所述第二外延层的厚度。
10.根据权利要求1所述的横向堆叠超级接面功率半导体装置,其特征在于所述第一外延层的厚度大于所述第二外延层的厚度。
11.根据权利要求3所述的横向堆叠超级接面功率半导体装置,其特征在于还包括一离子井沟渠,位于所述离子井中,及一离子井接触层,填满所述离子井沟渠。
12.根据权利要求11所述的横向堆叠超级接面功率半导体装置,其特征在于所述离子井接触层与所述源极接触层电连接在一起。
13.根据权利要求3所述的横向堆叠超级接面功率半导体装置,其特征在于所述源极扩散区是延伸所述外延堆叠结构的全部厚度。
14.根据权利要求1所述的横向堆叠超级接面功率半导体装置,其特征在于所述离子井是延伸所述外延堆叠结构的全部厚度。
15.一种横向堆叠超级接面功率半导体装置,其特征在于包括:
一半导体基底,具有一第一导电型;
一外延堆叠结构,设于所述半导体基底上,所述的外延堆叠结构包括至少一第一外延层,具有一第二导电型,及至少一第二外延层,具有所述第一导电型;
一漏极结构,嵌入于所述外延堆叠结构中,且所述漏极结构沿着一第一方向延伸;
一栅极结构,嵌入于所述外延堆叠结构中,并且沿着所述第一方向延伸;
一源极结构,设于所述栅极结构的一侧;及
一离子井,具有所述第一导电型,包围住所述源极结构。
16.根据权利要求15所述的横向堆叠超级接面功率半导体装置,其特征在于所述栅极结构包括一栅极导电层,埋入于一栅极沟渠中,及一栅极介电层包覆着所述栅极导电层。
17.根据权利要求16所述的横向堆叠超级接面功率半导体装置,其特征在于所述源极结构包括一源极沟渠,位于所述源极扩散区内、一源极扩散区,位于所述源极沟渠与所述的栅极沟渠间,及一源极接触层,填满所述源极沟渠。
18.根据权利要求17所述的横向堆叠超级接面功率半导体装置,其特征在于所述离子井与栅极导电层重叠处,与所述的源极扩散区间形成一栅极通道。
19.根据权利要求17所述的横向堆叠超级接面功率半导体装置,其特征在于所述源极扩散区是延伸所述的外延堆叠结构的全部厚度。
20.根据权利要求15所述的横向堆叠超级接面功率半导体装置,其特征在于所述离子井是延伸所述外延堆叠结构的全部厚度。
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US9059324B2 (en) * | 2013-06-30 | 2015-06-16 | Texas Instruments Incorporated | Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate |
US10014373B2 (en) | 2015-10-08 | 2018-07-03 | International Business Machines Corporation | Fabrication of semiconductor junctions |
RU2705761C1 (ru) * | 2016-08-10 | 2019-11-11 | Ниссан Мотор Ко., Лтд. | Полупроводниковое устройство |
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US20110127606A1 (en) * | 2009-11-30 | 2011-06-02 | Madhur Bobde | Lateral super junction device with high substrate-drain breakdwon and built-in avalanche clamp diode |
CN201975392U (zh) * | 2010-12-08 | 2011-09-14 | 马克斯半导体股份有限公司 | 内嵌沟渠式井区电场屏护功率金氧半场效晶体管结构 |
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US5674766A (en) * | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
JP4044721B2 (ja) * | 2000-08-15 | 2008-02-06 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
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US20110127606A1 (en) * | 2009-11-30 | 2011-06-02 | Madhur Bobde | Lateral super junction device with high substrate-drain breakdwon and built-in avalanche clamp diode |
CN201975392U (zh) * | 2010-12-08 | 2011-09-14 | 马克斯半导体股份有限公司 | 内嵌沟渠式井区电场屏护功率金氧半场效晶体管结构 |
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