CN104617133B - 沟槽型超级结器件的版图结构及其制造方法 - Google Patents

沟槽型超级结器件的版图结构及其制造方法 Download PDF

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CN104617133B
CN104617133B CN201510033925.0A CN201510033925A CN104617133B CN 104617133 B CN104617133 B CN 104617133B CN 201510033925 A CN201510033925 A CN 201510033925A CN 104617133 B CN104617133 B CN 104617133B
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李�昊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

本申请公开了一种沟槽型超级结器件的版图结构,是在每个晶粒中具有多个用于形成立柱的沟槽,相邻且平行的沟槽作为一个沟槽阵列,相邻的沟槽阵列的排列方向相互垂直。本申请还公开了一种沟槽型超级结器件的制造方法,已形成的超级结结构是在每个晶粒中具有两个以上的沟槽阵列,每个沟槽阵列由相邻且平行的沟槽所组成,相邻的沟槽阵列的排列方向相互垂直;所述方法包括以离子注入工艺形成覆盖所有沟槽阵列的离子注入区,所形成的离子注入区平行于至少一个沟槽阵列而垂直于至少另一个沟槽阵列;最终在所有沟槽阵列上均形成超级结器件。本申请通过相邻的晶粒或单元中的沟槽阵列的相互垂直的排列方向,来抵消深沟槽刻蚀后的应力,并克服了位错等缺陷。

Description

沟槽型超级结器件的版图结构及其制造方法
技术领域
本申请涉及一种沟槽型超级结器件的版图结构。
背景技术
申请公布号为CN103035677A、申请公布日为2013年4月10日的中国发明专利申请在其说明书的背景技术部分对于超级结MOSFET(金属-氧化物型场效应晶体管)进行了简要介绍。超级结器件除了包含超级结MOSFET外,还包含超级结JFET(结型场效应晶体管)、超级结肖特基二极管、超级结IGBT(绝缘栅双极晶体管)等,这些超级结器件的共同点是都具有超级结结构。
请参阅图1a,这是一种现有的超级结JFET的结构示意图,在n型外延层中具有交替排列的p型立柱(pillar,也称为纵向区)和n型立柱。这种在硅材料中所具有的交替排列的p型立柱和n型立柱就被称为超级结结构。
一种典型的超级结结构的制造工艺是在硅材料(例如n型外延层)刻蚀多个深沟槽(deep trench),然后以p型硅填充这些沟槽而形成p型立柱。相邻两个p型立柱之间的n型外延层就作为n型立柱,如图1b所示。采用这种制造工艺形成超级结结构的超级结器件被称为沟槽型超级结器件。
申请公布号为CA103824884A、申请公布日为2014年5月28日的中国发明专利申请进一步介绍了超级结MOSFET包括元胞区和终端区,所述终端区包括所述元胞区。上述用于形成立柱的沟槽阵列是在元胞区中。该份专利申请对于终端区中的沟槽排布进行了新设计,以提高耐压能力。
现有的沟槽型超级结器件中,用于形成立柱的沟槽阵列是由多道平行、等距、等长的沟槽形成的。请参阅图2a,一片晶圆(wafer)具有多个晶粒(die)。请参阅图2b,每个晶粒中用于制造沟槽型超级结器件的沟槽阵列均是同一方向排布。这种版图结构在沟槽间距(pitch)较大时没有问题。但是随着沟槽间距越来越小,这种设计会带来严重的晶圆翘曲(如图3所示),应力还会产生位错(dislocation)等硅缺陷。该缺陷主要发生在深沟槽刻蚀后及硅材料填充完成前,且晶圆在垂直于沟槽阵列的方向上弯曲最为严重,在平行于沟槽阵列的方向上弯曲较小。
发明内容
本申请所要解决的技术问题是解决带有深沟槽的晶圆在热工艺过程中的翘曲及应力所带来的位错乃至器件失效等缺陷,提高良品率。
为解决上述技术问题,本申请沟槽型超级结器件的版图结构是在每个晶粒中具有多个用于形成立柱的沟槽,相邻且平行的沟槽作为一个沟槽阵列,相邻的沟槽阵列的排列方向相互垂直。
本申请沟槽型超级结器件的制造方法是,已形成的超级结结构是在每个晶粒中具有两个以上的沟槽阵列,每个沟槽阵列由相邻且平行的沟槽所组成,相邻的沟槽阵列的排列方向相互垂直;所述方法包括以离子注入工艺形成覆盖所有沟槽阵列的离子注入区,所形成的离子注入区平行于至少一个沟槽阵列而垂直于至少另一个沟槽阵列;最终在所有沟槽阵列上均形成超级结器件。
本申请在晶粒中设计了相互垂直的多个沟槽阵列,来避免沟槽刻蚀后的晶圆翘曲现象,还抵消了沟槽刻蚀后的应力从而克服了位错等缺陷。本申请还为这种特殊版图结构提供了一种用于制造超级结器件的方法,可以对各个沟槽阵列不加区分地进行离子注入等工艺,从而与现有的制造工艺相比无需增加工艺步骤,最终则可在所有沟槽阵列上均形成超级结器件。
附图说明
图1a是一种现有的超级结JFET的结构示意图;
图1b是沟槽型超级结器件的超级结结构制造工艺示意图;
图2a是晶圆和晶粒的整体示意图;
图2b是现有的沟槽型超级结器件的版图结构示意图;
图3是现有的沟槽型超级结器件在沟槽刻蚀后导致晶圆翘曲的示意图;
图4a和图4b分别是本申请沟槽型超级结器件的版图结构的两个实施例的示意图;
图5a至图5d是本申请沟槽型超级结器件的版图结构的制造方法的示意图。
具体实施方式
请参阅图4a,这是本申请的实施例一。在每个晶粒中具有多个用于形成立柱的沟槽,均以黑色线条表示。相邻且平行的沟槽形成了多个正方形的沟槽阵列,这些沟槽阵列的大小大致相同。无论横向还是纵向,相邻两个沟槽阵列的排列方向相互垂直。
请参阅图4b,这是本申请的实施例二。其与实施例一的区别仅在于沟槽阵列的形状或者是正方形,或者是长方形,并且沟槽阵列的大小不同。
由于本申请在一个晶粒中具有相互垂直的沟槽阵列,这种特殊的沟槽型超级结器件的版图结构的制造工艺如图5a至图5c所示,以制造超级结MOSFET或超级结JFET为例。
请参阅图5a,这是已形成超级结结构的晶粒版图,准备用于制造超级结器件。在n型外延层中通过填充沟槽形成了p型立柱,相邻两个p型立柱之间的n型外延层作为n型立柱,p型立柱的宽度(即沟槽宽度)记为S,p型立柱的间距(即沟槽间距)记为L,位于左侧的横向沟槽阵列与位于右侧的纵向沟槽阵列的间距也为L。
请参阅图5b,采用淀积和光刻、刻蚀工艺形成覆盖所有沟槽阵列的栅极,至少在一个晶粒的范围内,也可在一片晶圆的范围内。虽然晶粒中具有相互垂直的多个沟槽阵列,这一步所形成的栅极只需要平行于其中一个沟槽阵列的排列方向即可。例如,图5b所示的栅极平行于位于左侧的横向沟槽阵列。此时在左侧的横向沟槽阵列中,栅极覆盖在与之平行的n型立柱之上。此时在右侧的纵向沟槽阵列中,栅极覆盖在与之垂直的p型立柱和n型立柱之上。
请参阅图5c,采用离子注入工艺形成覆盖所有沟槽阵列的p型体区(属于离子注入区的一种),至少在一个晶粒的范围内,也可在一片晶圆的范围内。虽然晶粒中具有相互垂直的多个沟槽阵列,这一步所形成的p型体区只需要平行于其中一个沟槽阵列的排列方向即可,并且要与上一步所形成的栅极平行。例如,图5c所示的p型体区平行于位于左侧的横向沟槽阵列。优选地,p型体区的宽度大于L。此时在左侧的横向沟槽阵列中,退火后扩散的p型体区不仅覆盖在p型立柱之上,还部分地挤占了n型立柱的上部,因而部分地位于栅极下方。p型立柱、n型立柱、栅极、p型体区的关系如图1a所示。此时在右侧的纵向沟槽阵列中,p型体区与p型立柱和n型立柱均相互垂直。
在图5c中,A-A向剖切线在左侧的横向沟槽阵列中且与其排列方向相垂直,B-B向剖切线在右侧的纵向沟槽阵列中且与其排列方向相平行。沿着A-A向剖切线,左侧的横向沟槽阵列的剖面结构类似于图1a所示,在n型外延层下方具有重掺杂的n型衬底作为超级结MOSFET或超级结JFET的漏极,还可根据超级结器件的不同类型选择性地增加栅氧化层、位于p型体区中的n型重掺杂区和p型重掺杂区等。沿着B-B向剖切线,右侧的纵向沟槽阵列的剖面结构如图5d所示,在n型外延层下方具有重掺杂的n型衬底作为超级结MOSFET或超级结JFET的漏极,还可根据超级结器件的不同类型选择性地增加栅氧化层、位于p型体区中的n型重掺杂区和p型重掺杂区等。综合图5c、图1a和图5d可以发现,左侧的横向沟槽阵列中所形成的超级结器件的栅极和体区均与沟槽阵列平行,右侧的纵向沟槽阵列中所形成的超级结器件的栅极和体区均与沟槽阵列垂直,然而两者都属于超级结器件。
在图5a至图5c给出的实施例中,本申请沟槽型超级结器件的版图结构是用于形成超级结MOSFET或超级结JFET。基于相同原理,本申请沟槽型超级结器件的版图结构还可用于形成其他超级结器件,例如超级结肖特基二极管、超级结IGBT等。
以上仅为本申请的优选实施例,并不用于限定本申请。对于本领域的技术人员来说,本申请可以有各种更改和变化。凡在本申请的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。

Claims (7)

1.一种沟槽型超级结器件的版图结构,是在每个晶粒中具有多个用于形成立柱的沟槽,其特征是,相邻且平行的沟槽作为一个沟槽阵列,相邻的沟槽阵列的排列方向相互垂直;
栅极覆盖所有沟槽阵列且所述栅极只平行于其中一个沟槽阵列的排列方向;
沟槽型超级结器件还包括覆盖所有沟槽阵列的离子注入区,所形成的离子注入区平行于至少一个沟槽阵列而垂直于至少另一个沟槽阵列。
2.根据权利要求1所述的沟槽型超级结器件的版图结构,其特征是,横向相邻的沟槽阵列的排列方向相互垂直,纵向相邻的沟槽阵列的排列方向也相互垂直。
3.根据权利要求1所述的沟槽型超级结器件的版图结构,其特征是,所述沟槽阵列为相同或不同大小的正方形或长方形。
4.根据权利要求1所述的沟槽型超级结器件的版图结构,其特征是,所述沟槽型超级结器件包括超级结MOSFET、超级结JFET、超级结肖特基二极管、超级结IGBT。
5.根据权利要求1所述的沟槽型超级结器件的版图结构,其特征是,所述沟槽阵列之间的间距等同于所述沟槽的间距。
6.一种沟槽型超级结器件的制造方法,其特征是,已形成的超级结结构是在每个晶粒中具有两个以上的沟槽阵列,每个沟槽阵列由相邻且平行的沟槽所组成,相邻的沟槽阵列的排列方向相互垂直;
所述方法包括以离子注入工艺形成覆盖所有沟槽阵列的离子注入区,所形成的离子注入区平行于至少一个沟槽阵列而垂直于至少另一个沟槽阵列;最终在所有沟槽阵列上均形成超级结器件,栅极只平行于其中一个沟槽阵列的排列方向。
7.根据权利要求6所述的沟槽型超级结器件的制造方法,其特征是,所述方法还包括以淀积和光刻、刻蚀工艺形成覆盖所有沟槽阵列的栅极,所形成的栅极平行于所述覆盖所有沟槽阵列的离子注入区的方向。
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