TW201430957A - 半導體功率元件的製作方法 - Google Patents

半導體功率元件的製作方法 Download PDF

Info

Publication number
TW201430957A
TW201430957A TW102102915A TW102102915A TW201430957A TW 201430957 A TW201430957 A TW 201430957A TW 102102915 A TW102102915 A TW 102102915A TW 102102915 A TW102102915 A TW 102102915A TW 201430957 A TW201430957 A TW 201430957A
Authority
TW
Taiwan
Prior art keywords
epitaxial layer
layer
trench
epitaxial
forming
Prior art date
Application number
TW102102915A
Other languages
English (en)
Inventor
Yung-Fa Lin
Original Assignee
Anpec Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anpec Electronics Corp filed Critical Anpec Electronics Corp
Priority to TW102102915A priority Critical patent/TW201430957A/zh
Priority to US13/783,399 priority patent/US20140213023A1/en
Priority to CN201310128850.5A priority patent/CN103972096A/zh
Publication of TW201430957A publication Critical patent/TW201430957A/zh
Priority to US14/523,938 priority patent/US20150054064A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一種半導體功率元件的製作方法。先提供一半導體基底，具有複數個晶片區域以及晶片區域間的切割道區域。再於半導體基底上形成第一磊晶層。再於第一磊晶層表面形成硬遮罩層，於硬遮罩層中形成至少一開口，經由開口，蝕刻第一磊晶層，形成至少一溝槽，其中開口及溝槽橫跨複數個晶片區域及切割道區域，使得溝槽的兩端均不落在晶片區域內。接著去除硬遮罩層，再於溝槽中填滿一第二磊晶層，並使第二磊晶層覆蓋第一磊晶層。再將覆蓋在第一磊晶層上的第二磊晶層研磨掉，顯露出第一磊晶層。於第一及第二磊晶層上形成第三磊晶層。

Description

半導體功率元件的製作方法
本發明係有關一種半導體功率元件的製作方法，特別是有關於一種具有超級接面結構的半導體功率元件的製作方法。
已知，在功率元件中，其基底的設計通常為P型與N型半導體交替設置，因此在基底中會存在有多個垂直於基底表面的PN接面，且該些PN接面互相平行，又稱為超級接面結構，此種結構具有耐壓低阻抗之優點。
其中一種超級接面結構係利用蝕刻出深溝渠，再填入磊晶層之方式來製作，其具有製程上之簡化以及低成本之優點，然而這種技術仍技術問題需要克服，例如，深溝槽內之蝕刻能力以及後續磊晶製程所產生的缺陷。
因此本發明之目的，即提供一種改良的半導體功率元件的製作方法，利用跨晶片區域的溝槽磊晶製程，降低磊晶製程所產生的缺陷，並且可以形成功率元件所使用具有超級介面的基材。
為達上述目的，本發明提出一種半導體功率元件的製作方法，包含有：提供一半導體基底，具有第一電性，其上有複數個晶片區域以及介於該晶片區域之間的切割道區域；於該半導體基底上形成一第一磊晶層，具有上述第一電性；於該第一磊晶層表面形成一硬遮罩層；於該硬遮罩層中形成至少一開口；經由該開口，蝕刻該第一磊晶層，形 成至少一溝槽，其中該開口及該溝槽係橫跨該複數個晶片區域以及該切割道區域，使得該溝槽的兩端均不落在該晶片區域內；去除該硬遮罩層；於該溝槽中填滿一第二磊晶層，具有第二電性，並使第二磊晶層覆蓋該第一磊晶層；進行一化學機械研磨製程，將覆蓋在該第一磊晶層上的該第二磊晶層研磨掉，顯露出該第一磊晶層；以及於該第一及第二磊晶層上形成一第三磊晶層，具有上述第一電性。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特 舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
10‧‧‧半導體基底
11‧‧‧磊晶層
11a‧‧‧磊晶層
12‧‧‧硬遮罩層
13‧‧‧磊晶層
22‧‧‧閘極氧化層
24‧‧‧閘極
30‧‧‧層間介電層
32‧‧‧阻障層
34‧‧‧金屬層
34a‧‧‧接觸件
100‧‧‧晶片區域
110‧‧‧切割道區域
112‧‧‧開口
122‧‧‧溝槽
122a‧‧‧溝槽兩端
130‧‧‧離子井
132‧‧‧源極摻雜區
230‧‧‧接觸洞
第1圖至第8圖為依據本發明一實施例所繪示的溝渠式功率電晶體元件之製造方法示意圖。
第9圖為依據本發明一實施例所繪示的溝渠式功率電晶體元件的平面示意圖。
請參閱第1圖至第8圖，其為依據本發明一實施例所繪示的溝渠式功率電晶體元件之製造方法示意圖。第1圖可以為第2圖中沿著切線I-I’所視剖面。首先，如第1圖及第2圖所示，提供一半導體基底10，其具有第一電性，例如N型重摻雜之矽晶圓，其可作為電晶體元件的汲極(drain)。在半導體基底10有複數個晶片區域100以及介於晶片區域100之間的切割道(scribe lane)區域110(見第2圖)，上述溝渠式功率電晶體元件即形成在各個晶片區域100內。
首先，利用一磊晶製程於半導體基底10上形成一磊晶層11， 例如N型磊晶矽層。接著，可以在磊晶層11表面形成一硬遮罩層12，例如，氧化矽或者氮化矽。然後，利用微影、蝕刻等製程，於硬遮罩層12 中形成開口112。接著將光阻去除，然後，利用乾蝕刻製程，經由硬遮罩層12中的開口112，蝕刻磊晶層11至一預定深度，如此形成溝槽122。
本發明的主要特徵在於，如第2圖所示，上述形成的開口112 及溝槽122係橫跨複數個晶片區域100以及切割道區域110，使得各個溝槽122的兩端122a均不落在晶片區域100內，意即，各個溝槽122的兩端122a與晶片區域100不重疊。根據本發明實施例，各個直線條狀的溝槽122係在一方向(例如參考座標X軸)為連續的，且橫跨數個在該方向上的同列複數個晶片區域100。另外，如第9圖所示，溝槽122亦可以是呈現格柵狀或交錯的圖案，使直線條狀的溝槽122在不同的方向(例如參考座標X軸及參考座標Y軸)為連續的，且同樣橫跨數個在各方向上的複數個晶片區域100。
由於磊晶缺陷經常發生在溝槽122的兩端122a，這樣的做法 即可降低磊晶製程過程中形成在晶片區域100的介面缺陷。需注意的是，第2圖中的晶片區域100大小、數量以及溝槽122的數量、形狀僅為例示，本發明並非以此為限。此外，除了上述如第1圖至第4圖中的作法之外，也可以在N型基底10上先形成第一(P型)磊晶層11，蝕刻出溝槽122之後，填入第二(N型)磊晶層13，之後，可以保留高於第一(P型)磊晶層11上的N型區域(類似11a)，或再研磨至第一(P型)磊晶層，再形成第三(N型)磊晶層11a。
需注意的是，若磊晶層11為N型，上述溝槽122蝕刻的深度 可以選擇貫穿或不貫穿磊晶層11，若磊晶層11為P型的話，則溝槽122蝕刻的深度必須貫穿磊晶層11。
如第3圖所示，接著去除硬遮罩層12，並進行磊晶製程，於 溝槽122中填滿磊晶層13，具有第二電性，例如P型磊晶矽層。根據本發明實施例，磊晶層11與磊晶層13具有相反的摻質電性。根據本發明實施例，磊晶層13可以覆蓋磊晶層11。
如第4圖所示，接著進行化學機械研磨(CMP)製程，將覆蓋在 磊晶層11上的磊晶層13研磨掉，顯露出磊晶層11。隨後，進行另一次的磊晶製程，形成磊晶層11a，具有上述第一電性，覆蓋住磊晶層11及磊晶層13。磊晶層11a電性與磊晶層11相同，與磊晶層13相反。根據本發明實施例，磊晶層11a為N型磊晶矽層。此時，即完成可用於製作超級接面結構的半導體基材。
如第5圖所示，接著，於磊晶層11a表面形成閘極氧化層22 以及閘極24。根據本發明實施例，閘極24可以是多晶矽閘極。根據本發明實施例，閘極24的圖案可以是直線型，並以微影製程分別將各個晶片區域100內的閘極圖案定義出來，加以蝕刻而成。
如第6圖所示，進行一離子佈植製程，在兩閘極24之間的磊 晶層11a中植入具有第二電性(例如P型)摻質，形成離子井130。後續可以進行熱驅入(thermal drive-in)製程。
如第7圖所示，利用光阻及微影製程，定義出源極摻雜區域， 然後，施以離子佈植，將第一電性(例如N型)摻質植入離子井130，形成源極摻雜區132。後續可以進行熱驅入製程。
最後，如第8圖所示，進行接觸洞及金屬化製程，包括形成 層間介電層30，於層間介電層30中蝕刻出接觸洞230，沈積阻障層32及金屬層34，並使金屬層34填滿接觸洞230，構成接觸件34a，接觸離子井130及源極摻雜區132。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體基底
12‧‧‧硬遮罩層
100‧‧‧晶片區域
110‧‧‧切割道區域
122‧‧‧溝槽
122a‧‧‧溝槽兩端

Claims (9)

  1. 一種半導體功率元件的製作方法，包含有：提供一半導體基底，具有第一電性，其上有複數個晶片區域以及介於該晶片區域之間的切割道區域；於該半導體基底上形成一第一磊晶層，具有上述第一電性；於該第一磊晶層表面形成一硬遮罩層；於該硬遮罩層中形成至少一開口；經由該開口，蝕刻該第一磊晶層，形成至少一溝槽，其中該開口及該溝槽係橫跨該複數個晶片區域以及該切割道區域，使得該溝槽的兩端均不落在該晶片區域內；去除該硬遮罩層；於該溝槽中填滿一第二磊晶層，具有第二電性，並使第二磊晶層覆蓋該第一磊晶層；進行一化學機械研磨製程，將覆蓋在該第一磊晶層上的該第二磊晶層研磨掉，顯露出該第一磊晶層；以及於該第一及第二磊晶層上形成一第三磊晶層，具有上述第一電性。
  2. 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該第一電性為N型，該第二電性為P型。
  3. 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該第一、第二及第三磊晶層均為磊晶矽層。
  4. 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中在形成該第三磊晶層後，另包含有以下步驟：於該第三磊晶層上形成一閘極氧化層以及複數閘極； 進行一離子佈植製程，在該複數閘極之間的該第三磊晶層中植入具有上述第二電性摻質，形成一離子井；以及於該離子井中形成一源極摻雜區。
  5. 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中在形成該源極摻雜區後，另包含有以下步驟：形成一層間介電層；於該層間介電層中蝕刻出至少一接觸洞；以及沈積一阻障層及一金屬層，並使該金屬層填滿該接觸洞，構成一接觸件。
  6. 如申請專利範圍第1項所述之半導體功率元件的製作方法，其中該半導體基底係作為該半導體功率元件的汲極。
  7. 一種半導體功率元件的製作方法，包含有：提供一半導體基底，具有第一電性，其上有複數個晶片區域以及介於該晶片區域之間的切割道區域；於該半導體基底上形成一第一磊晶層，第二電性；於該第一磊晶層表面形成一硬遮罩層；於該硬遮罩層中形成至少一開口；經由該開口，蝕刻該第一磊晶層，形成至少一溝槽，其中該開口及該溝槽係橫跨該複數個晶片區域以及該切割道區域，使得該溝槽的兩端均不落在該晶片區域內；去除該硬遮罩層；以及於該溝槽中填滿一第二磊晶層，具有上述第一電性，並使第二磊晶層覆蓋該第一磊晶層。
  8. 如申請專利範圍第7項所述之半導體功率元件的製作方法，其中於該溝槽中填滿該第二磊晶層後，另包含有以下步驟：進行一化學機械研磨製程，將覆蓋在該第一磊晶層上的該第二磊晶層研磨掉，顯露出該第一磊晶層；以及於該第一及第二磊晶層上形成一第三磊晶層，具有上述第一電性。
  9. 如申請專利範圍第7項所述之半導體功率元件的製作方法，其中該第一電性為N型，該第二電性為P型。
TW102102915A 2013-01-25 2013-01-25 半導體功率元件的製作方法 TW201430957A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW102102915A TW201430957A (zh) 2013-01-25 2013-01-25 半導體功率元件的製作方法
US13/783,399 US20140213023A1 (en) 2013-01-25 2013-03-04 Method for fabricating power semiconductor device
CN201310128850.5A CN103972096A (zh) 2013-01-25 2013-04-15 半导体功率器件的制作方法
US14/523,938 US20150054064A1 (en) 2013-01-25 2014-10-26 Power semiconductor device with super junction structure and interlaced, grid-type trench network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW102102915A TW201430957A (zh) 2013-01-25 2013-01-25 半導體功率元件的製作方法

Publications (1)

Publication Number Publication Date
TW201430957A true TW201430957A (zh) 2014-08-01

Family

ID=51223368

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102102915A TW201430957A (zh) 2013-01-25 2013-01-25 半導體功率元件的製作方法

Country Status (3)

Country Link
US (2) US20140213023A1 (zh)
CN (1) CN103972096A (zh)
TW (1) TW201430957A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9111992B2 (en) * 2011-09-13 2015-08-18 Globalfoundries Singapore Pte. Ltd. Semiconductor device including an n-well structure
US9099320B2 (en) * 2013-09-19 2015-08-04 Force Mos Technology Co., Ltd. Super-junction structures having implanted regions surrounding an N epitaxial layer in deep trench
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
CN104617133B (zh) * 2015-01-23 2018-02-06 上海华虹宏力半导体制造有限公司 沟槽型超级结器件的版图结构及其制造方法
CN117476468B (zh) * 2023-12-26 2024-03-22 北京智芯微电子科技有限公司 超结结构及其制造方法、超结半导体器件和半导体结构

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11330458A (ja) * 1998-05-08 1999-11-30 Toshiba Corp 半導体装置およびその製造方法
US6448160B1 (en) * 1999-04-01 2002-09-10 Apd Semiconductor, Inc. Method of fabricating power rectifier device to vary operating parameters and resulting device
US6475864B1 (en) * 1999-10-21 2002-11-05 Fuji Electric Co., Ltd. Method of manufacturing a super-junction semiconductor device with an conductivity type layer
JP4765012B2 (ja) * 2000-02-09 2011-09-07 富士電機株式会社 半導体装置及びその製造方法
JP3636345B2 (ja) * 2000-03-17 2005-04-06 富士電機デバイステクノロジー株式会社 半導体素子および半導体素子の製造方法
JP4764987B2 (ja) * 2000-09-05 2011-09-07 富士電機株式会社 超接合半導体素子
JP3899231B2 (ja) * 2000-12-18 2007-03-28 株式会社豊田中央研究所 半導体装置
JP2004055803A (ja) * 2002-07-19 2004-02-19 Renesas Technology Corp 半導体装置
JP4536366B2 (ja) * 2003-12-22 2010-09-01 株式会社豊田中央研究所 半導体装置とその設計支援用プログラム
JP4830360B2 (ja) * 2005-06-17 2011-12-07 株式会社デンソー 半導体装置およびその製造方法
US7928470B2 (en) * 2005-11-25 2011-04-19 Denso Corporation Semiconductor device having super junction MOS transistor and method for manufacturing the same
US8106453B2 (en) * 2006-01-31 2012-01-31 Denso Corporation Semiconductor device having super junction structure
US8658542B2 (en) * 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7595542B2 (en) * 2006-03-13 2009-09-29 Fairchild Semiconductor Corporation Periphery design for charge balance power devices
US7510938B2 (en) * 2006-08-25 2009-03-31 Freescale Semiconductor, Inc. Semiconductor superjunction structure
JP2008091450A (ja) * 2006-09-29 2008-04-17 Toshiba Corp 半導体素子
JP4331773B2 (ja) * 2007-03-20 2009-09-16 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US7960997B2 (en) * 2007-08-08 2011-06-14 Advanced Analogic Technologies, Inc. Cascode current sensor for discrete power semiconductor devices
US8928077B2 (en) * 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US8012806B2 (en) * 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices
US7629634B2 (en) * 2008-02-23 2009-12-08 Force Mos Technology Co., Ltd. Trenched MOSFET with trenched source contact
JP5546759B2 (ja) * 2008-08-05 2014-07-09 トヨタ自動車株式会社 半導体装置及びその製造方法
US20120273916A1 (en) * 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
JP5571306B2 (ja) * 2008-12-17 2014-08-13 ローム株式会社 半導体装置
IT1397574B1 (it) * 2008-12-29 2013-01-16 St Microelectronics Rousset Dispositivo a semiconduttore di potenza di tipo multi-drain e relativa struttura di terminazione di bordo
JP2011018764A (ja) * 2009-07-08 2011-01-27 Toshiba Corp 半導体装置
US9312330B2 (en) * 2009-07-15 2016-04-12 Fuji Electric Co., Ltd. Super-junction semiconductor device
US7800170B1 (en) * 2009-07-31 2010-09-21 Alpha & Omega Semiconductor, Inc. Power MOSFET device with tungsten spacer in contact hole and method
JP5002628B2 (ja) * 2009-08-25 2012-08-15 株式会社東芝 電力用半導体素子
KR101121574B1 (ko) * 2010-01-12 2012-03-06 (주) 트리노테크놀로지 전하 균형 전력 디바이스 및 그 제조 방법
JPWO2011099047A1 (ja) * 2010-02-09 2013-06-13 パナソニック株式会社 半導体装置およびその製造方法
US8264035B2 (en) * 2010-03-26 2012-09-11 Force Mos Technology Co., Ltd. Avalanche capability improvement in power semiconductor devices
JP2011243859A (ja) * 2010-05-20 2011-12-01 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
JP5614877B2 (ja) * 2010-05-28 2014-10-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5740108B2 (ja) * 2010-07-16 2015-06-24 株式会社東芝 半導体装置
CN103109350A (zh) * 2010-09-30 2013-05-15 飞思卡尔半导体公司 处理半导体晶片的方法、半导体晶片以及半导体器件
JP5719167B2 (ja) * 2010-12-28 2015-05-13 ルネサスエレクトロニクス株式会社 半導体装置
JP5757101B2 (ja) * 2011-02-17 2015-07-29 富士電機株式会社 超接合半導体素子
JP5738653B2 (ja) * 2011-03-31 2015-06-24 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 絶縁ゲート型半導体装置
JP5915076B2 (ja) * 2011-10-21 2016-05-11 富士電機株式会社 超接合半導体装置
TWI469351B (zh) * 2011-11-29 2015-01-11 Anpec Electronics Corp 具有超級介面之功率電晶體元件及其製作方法
KR101876573B1 (ko) * 2011-12-23 2018-07-10 매그나칩 반도체 유한회사 반도체 소자 및 그 제조 방법
JP5758365B2 (ja) * 2012-09-21 2015-08-05 株式会社東芝 電力用半導体素子
JP6142496B2 (ja) * 2012-10-12 2017-06-07 富士電機株式会社 半導体装置の製造方法
JP2014086569A (ja) * 2012-10-24 2014-05-12 Renesas Electronics Corp 縦型パワーｍｏｓｆｅｔ
TW201438232A (zh) * 2013-03-26 2014-10-01 Anpec Electronics Corp 半導體功率元件及其製作方法
JP6221436B2 (ja) * 2013-07-10 2017-11-01 富士電機株式会社 超接合ｍｏｓｆｅｔとその製造方法およびダイオードを並列接続させた複合半導体装置

Also Published As

Publication number Publication date
US20150054064A1 (en) 2015-02-26
CN103972096A (zh) 2014-08-06
US20140213023A1 (en) 2014-07-31

Similar Documents

Publication Publication Date Title
TWI548086B (zh) 溝渠式橫向擴散金屬氧化半導體元件及其製造方法
US10424654B2 (en) Power device with high aspect ratio trench contacts and submicron pitches between trenches
TWI388059B (zh) The structure of gold-oxygen semiconductor and its manufacturing method
TWI503984B (zh) 積體電路裝置及其製造方法
JP5551213B2 (ja) 半導体装置の製造方法
CN109786436B (zh) 集成芯片及其形成方法
KR100745917B1 (ko) 반도체 소자의 제조 방법
TW201440118A (zh) 半導體功率元件的製作方法
CN110957318A (zh) 一种半导体结构及其制作方法
CN108400166B (zh) 在端子降低表面电场区域中具有端子沟槽的功率晶体管
TWI572040B (zh) 溝槽型－垂直式雙擴散金氧半電晶體結構及其製造方法
TW201430957A (zh) 半導體功率元件的製作方法
TW201301359A (zh) 具有源極溝槽之溝槽式功率半導體元件的製造方法
US9431286B1 (en) Deep trench with self-aligned sinker
TWI450327B (zh) 功率半導體元件的製作方法
TW201440145A (zh) 半導體功率元件的製作方法
JP7263644B2 (ja) 半導体デバイスの製造方法
CN213660411U (zh) 超结器件
KR100853799B1 (ko) 트렌치 게이트 반도체 소자 및 그의 제조 방법
US20090140331A1 (en) Method of fabricating high voltage device
TWI490950B (zh) 溝渠式金屬氧化物半導體結構及其形成方法
US8853026B2 (en) Semiconductor device having deep wells and fabrication method thereof
JP2011155290A (ja) 半導体素子の製造方法
TWI511293B (zh) 雙溝渠式ｍｏｓ電晶體結構及其製造方法
CN112289861B (zh) 半导体结构及其制造方法