TW201430957A - 半導體功率元件的製作方法 - Google Patents

半導體功率元件的製作方法 Download PDF

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TW201430957A
TW201430957A TW102102915A TW102102915A TW201430957A TW 201430957 A TW201430957 A TW 201430957A TW 102102915 A TW102102915 A TW 102102915A TW 102102915 A TW102102915 A TW 102102915A TW 201430957 A TW201430957 A TW 201430957A
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epitaxial layer
layer
trench
forming
electrical property
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Yung-Fa Lin
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Anpec Electronics Corp
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    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
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    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
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    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs

Abstract

一種半導體功率元件的製作方法。先提供一半導體基底,具有複數個晶片區域以及晶片區域間的切割道區域。再於半導體基底上形成第一磊晶層。再於第一磊晶層表面形成硬遮罩層,於硬遮罩層中形成至少一開口,經由開口,蝕刻第一磊晶層,形成至少一溝槽,其中開口及溝槽橫跨複數個晶片區域及切割道區域,使得溝槽的兩端均不落在晶片區域內。接著去除硬遮罩層,再於溝槽中填滿一第二磊晶層,並使第二磊晶層覆蓋第一磊晶層。再將覆蓋在第一磊晶層上的第二磊晶層研磨掉,顯露出第一磊晶層。於第一及第二磊晶層上形成第三磊晶層。

Description

半導體功率元件的製作方法

本發明係有關一種半導體功率元件的製作方法,特別是有關於一種具有超級接面結構的半導體功率元件的製作方法。

已知,在功率元件中,其基底的設計通常為P型與N型半導體交替設置,因此在基底中會存在有多個垂直於基底表面的PN接面,且該些PN接面互相平行,又稱為超級接面結構,此種結構具有耐壓低阻抗之優點。

其中一種超級接面結構係利用蝕刻出深溝渠,再填入磊晶層之方式來製作,其具有製程上之簡化以及低成本之優點,然而這種技術仍技術問題需要克服,例如,深溝槽內之蝕刻能力以及後續磊晶製程所產生的缺陷。

因此本發明之目的,即提供一種改良的半導體功率元件的製作方法,利用跨晶片區域的溝槽磊晶製程,降低磊晶製程所產生的缺陷,並且可以形成功率元件所使用具有超級介面的基材。

為達上述目的,本發明提出一種半導體功率元件的製作方法,包含有:提供一半導體基底,具有第一電性,其上有複數個晶片區域以及介於該晶片區域之間的切割道區域;於該半導體基底上形成一第一磊晶層,具有上述第一電性;於該第一磊晶層表面形成一硬遮罩層;於該硬遮罩層中形成至少一開口;經由該開口,蝕刻該第一磊晶層,形 成至少一溝槽,其中該開口及該溝槽係橫跨該複數個晶片區域以及該切割道區域,使得該溝槽的兩端均不落在該晶片區域內;去除該硬遮罩層;於該溝槽中填滿一第二磊晶層,具有第二電性,並使第二磊晶層覆蓋該第一磊晶層;進行一化學機械研磨製程,將覆蓋在該第一磊晶層上的該第二磊晶層研磨掉,顯露出該第一磊晶層;以及於該第一及第二磊晶層上形成一第三磊晶層,具有上述第一電性。

為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特 舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。

10‧‧‧半導體基底

11‧‧‧磊晶層

11a‧‧‧磊晶層

12‧‧‧硬遮罩層

13‧‧‧磊晶層

22‧‧‧閘極氧化層

24‧‧‧閘極

30‧‧‧層間介電層

32‧‧‧阻障層

34‧‧‧金屬層

34a‧‧‧接觸件

100‧‧‧晶片區域

110‧‧‧切割道區域

112‧‧‧開口

122‧‧‧溝槽

122a‧‧‧溝槽兩端

130‧‧‧離子井

132‧‧‧源極摻雜區

230‧‧‧接觸洞

第1圖至第8圖為依據本發明一實施例所繪示的溝渠式功率電晶體元件之製造方法示意圖。

第9圖為依據本發明一實施例所繪示的溝渠式功率電晶體元件的平面示意圖。

請參閱第1圖至第8圖,其為依據本發明一實施例所繪示的溝渠式功率電晶體元件之製造方法示意圖。第1圖可以為第2圖中沿著切線I-I’所視剖面。首先,如第1圖及第2圖所示,提供一半導體基底10,其具有第一電性,例如N型重摻雜之矽晶圓,其可作為電晶體元件的汲極(drain)。在半導體基底10有複數個晶片區域100以及介於晶片區域100之間的切割道(scribe lane)區域110(見第2圖),上述溝渠式功率電晶體元件即形成在各個晶片區域100內。

首先,利用一磊晶製程於半導體基底10上形成一磊晶層11, 例如N型磊晶矽層。接著,可以在磊晶層11表面形成一硬遮罩層12,例如,氧化矽或者氮化矽。然後,利用微影、蝕刻等製程,於硬遮罩層12 中形成開口112。接著將光阻去除,然後,利用乾蝕刻製程,經由硬遮罩層12中的開口112,蝕刻磊晶層11至一預定深度,如此形成溝槽122。

本發明的主要特徵在於,如第2圖所示,上述形成的開口112 及溝槽122係橫跨複數個晶片區域100以及切割道區域110,使得各個溝槽122的兩端122a均不落在晶片區域100內,意即,各個溝槽122的兩端122a與晶片區域100不重疊。根據本發明實施例,各個直線條狀的溝槽122係在一方向(例如參考座標X軸)為連續的,且橫跨數個在該方向上的同列複數個晶片區域100。另外,如第9圖所示,溝槽122亦可以是呈現格柵狀或交錯的圖案,使直線條狀的溝槽122在不同的方向(例如參考座標X軸及參考座標Y軸)為連續的,且同樣橫跨數個在各方向上的複數個晶片區域100。

由於磊晶缺陷經常發生在溝槽122的兩端122a,這樣的做法 即可降低磊晶製程過程中形成在晶片區域100的介面缺陷。需注意的是,第2圖中的晶片區域100大小、數量以及溝槽122的數量、形狀僅為例示,本發明並非以此為限。此外,除了上述如第1圖至第4圖中的作法之外,也可以在N型基底10上先形成第一(P型)磊晶層11,蝕刻出溝槽122之後,填入第二(N型)磊晶層13,之後,可以保留高於第一(P型)磊晶層11上的N型區域(類似11a),或再研磨至第一(P型)磊晶層,再形成第三(N型)磊晶層11a。

需注意的是,若磊晶層11為N型,上述溝槽122蝕刻的深度 可以選擇貫穿或不貫穿磊晶層11,若磊晶層11為P型的話,則溝槽122蝕刻的深度必須貫穿磊晶層11。

如第3圖所示,接著去除硬遮罩層12,並進行磊晶製程,於 溝槽122中填滿磊晶層13,具有第二電性,例如P型磊晶矽層。根據本發明實施例,磊晶層11與磊晶層13具有相反的摻質電性。根據本發明實施例,磊晶層13可以覆蓋磊晶層11。

如第4圖所示,接著進行化學機械研磨(CMP)製程,將覆蓋在 磊晶層11上的磊晶層13研磨掉,顯露出磊晶層11。隨後,進行另一次的磊晶製程,形成磊晶層11a,具有上述第一電性,覆蓋住磊晶層11及磊晶層13。磊晶層11a電性與磊晶層11相同,與磊晶層13相反。根據本發明實施例,磊晶層11a為N型磊晶矽層。此時,即完成可用於製作超級接面結構的半導體基材。

如第5圖所示,接著,於磊晶層11a表面形成閘極氧化層22 以及閘極24。根據本發明實施例,閘極24可以是多晶矽閘極。根據本發明實施例,閘極24的圖案可以是直線型,並以微影製程分別將各個晶片區域100內的閘極圖案定義出來,加以蝕刻而成。

如第6圖所示,進行一離子佈植製程,在兩閘極24之間的磊 晶層11a中植入具有第二電性(例如P型)摻質,形成離子井130。後續可以進行熱驅入(thermal drive-in)製程。

如第7圖所示,利用光阻及微影製程,定義出源極摻雜區域, 然後,施以離子佈植,將第一電性(例如N型)摻質植入離子井130,形成源極摻雜區132。後續可以進行熱驅入製程。

最後,如第8圖所示,進行接觸洞及金屬化製程,包括形成 層間介電層30,於層間介電層30中蝕刻出接觸洞230,沈積阻障層32及金屬層34,並使金屬層34填滿接觸洞230,構成接觸件34a,接觸離子井130及源極摻雜區132。

以上所述僅為本發明之較佳實施例,凡依本發明申請專利範 圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。

10‧‧‧半導體基底

12‧‧‧硬遮罩層

100‧‧‧晶片區域

110‧‧‧切割道區域

122‧‧‧溝槽

122a‧‧‧溝槽兩端

Claims (9)

  1. 一種半導體功率元件的製作方法,包含有:提供一半導體基底,具有第一電性,其上有複數個晶片區域以及介於該晶片區域之間的切割道區域;於該半導體基底上形成一第一磊晶層,具有上述第一電性;於該第一磊晶層表面形成一硬遮罩層;於該硬遮罩層中形成至少一開口;經由該開口,蝕刻該第一磊晶層,形成至少一溝槽,其中該開口及該溝槽係橫跨該複數個晶片區域以及該切割道區域,使得該溝槽的兩端均不落在該晶片區域內;去除該硬遮罩層;於該溝槽中填滿一第二磊晶層,具有第二電性,並使第二磊晶層覆蓋該第一磊晶層;進行一化學機械研磨製程,將覆蓋在該第一磊晶層上的該第二磊晶層研磨掉,顯露出該第一磊晶層;以及於該第一及第二磊晶層上形成一第三磊晶層,具有上述第一電性。
  2. 如申請專利範圍第1項所述之半導體功率元件的製作方法,其中該第一電性為N型,該第二電性為P型。
  3. 如申請專利範圍第1項所述之半導體功率元件的製作方法,其中該第一、第二及第三磊晶層均為磊晶矽層。
  4. 如申請專利範圍第1項所述之半導體功率元件的製作方法,其中在形成該第三磊晶層後,另包含有以下步驟:於該第三磊晶層上形成一閘極氧化層以及複數閘極; 進行一離子佈植製程,在該複數閘極之間的該第三磊晶層中植入具有上述第二電性摻質,形成一離子井;以及於該離子井中形成一源極摻雜區。
  5. 如申請專利範圍第1項所述之半導體功率元件的製作方法,其中在形成該源極摻雜區後,另包含有以下步驟:形成一層間介電層;於該層間介電層中蝕刻出至少一接觸洞;以及沈積一阻障層及一金屬層,並使該金屬層填滿該接觸洞,構成一接觸件。
  6. 如申請專利範圍第1項所述之半導體功率元件的製作方法,其中該半導體基底係作為該半導體功率元件的汲極。
  7. 一種半導體功率元件的製作方法,包含有:提供一半導體基底,具有第一電性,其上有複數個晶片區域以及介於該晶片區域之間的切割道區域;於該半導體基底上形成一第一磊晶層,第二電性;於該第一磊晶層表面形成一硬遮罩層;於該硬遮罩層中形成至少一開口;經由該開口,蝕刻該第一磊晶層,形成至少一溝槽,其中該開口及該溝槽係橫跨該複數個晶片區域以及該切割道區域,使得該溝槽的兩端均不落在該晶片區域內;去除該硬遮罩層;以及於該溝槽中填滿一第二磊晶層,具有上述第一電性,並使第二磊晶層覆蓋該第一磊晶層。
  8. 如申請專利範圍第7項所述之半導體功率元件的製作方法,其中於該溝槽中填滿該第二磊晶層後,另包含有以下步驟:進行一化學機械研磨製程,將覆蓋在該第一磊晶層上的該第二磊晶層研磨掉,顯露出該第一磊晶層;以及於該第一及第二磊晶層上形成一第三磊晶層,具有上述第一電性。
  9. 如申請專利範圍第7項所述之半導體功率元件的製作方法,其中該第一電性為N型,該第二電性為P型。
TW102102915A 2013-01-25 2013-01-25 半導體功率元件的製作方法 TW201430957A (zh)

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